KR20080039095A - Method for manufacturing nand type flash memory device - Google Patents

Abstract

A method of manufacturing a NAND flash memory device is provided to control the height of a device isolation layer of a dummy cell region to get higher height than that of a cell region by using an etch mask which closes a dummy cell region and a peripheral circuit region, and only opens a memory cell region. A memory cell region(MC), a dummy cell region(DC) and a peripheral circuit region(PERI) are defined on a semiconductor substrate(110). A plurality of device isolation layers(115) are formed respectively at the memory cell region, dummy cell region and the peripheral region. The effective height of the device isolation layer, which is formed in the memory cell region, is controlled by performing an etching process using an etch mask which opens the memory cell region, and closes the dummy cell region and the peripheral circuit region.

Description

Manufacturing method of NAND flash memory device {METHOD FOR MANUFACTURING NAND TYPE FLASH MEMORY DEVICE}

1A to 1E are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11: tunnel oxide film

12, 112: polysilicon film for floating gate

13, 113: pad nitride film

14, 114: trench

15, 115: device separator

16, 116 photosensitive film pattern

18, 118: dielectric film

19, 119: polysilicon film for control gate

111: gate insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly to a memory cell array region in which memory cells are formed, a driving circuit (decoder) and a page buffer for driving the memory cells. The present invention relates to a method of manufacturing a NAND type flash memory device in which a dummy cell array that is not used for an actual device operation is formed between peripheral circuit areas in which a) and the like are formed.

Recently, the demand for flash memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

As a result, a NAND flash memory device in which a plurality of memory cells are connected in series to form a string is proposed for high integration of the memory device.

Unlike NOR-type flash memory devices, NAND flash memory devices read data sequentially and use a Fowler-Nordheim (FN) tunneling scheme. By injecting electrons into the floating gate or by emitting the injected electrons, the program and erase operations are performed in a manner of controlling the threshold voltage of the memory cell.

In general, in the manufacturing process of a NAND flash memory device having a line width of 70 nm or less, the floating gate is formed by using a Self Aligned Shallow Trench Isolation (SA-STI) or an Advanced SA-STI (ASA-STI) process. In this process, a step is generated between the memory cell array area and the peripheral circuit area due to various reasons such as the difference in the thickness of the tunnel oxide film (or the gate oxide film). In order to reduce the step, chemical mechanical polishing (CMP) The process is performed to achieve planarization of the device. The planarization process is one of the processes that are essentially performed because it can solve the problem that the resolution decreases due to the step of the structure in performing the photolithography process in the subsequent process. In the planarization process, a CMP process is generally performed to fill a material in a structure having a stepped level and to planarize an upper portion thereof.

However, although the CMP process has an advantage of obtaining excellent characteristics in terms of planarization, there is a process limitation in that the thickness of the target film must be uniformly applied during the CMP process. This is because so-called dishing occurs during the CMP process. This dishing phenomenon refers to a phenomenon in which the CMP target layer is locally turned off according to the pattern shape, size, or position of the CMP target layer, that is, the lower layer formed under the material layer.

In order to solve this dishing phenomenon, a NAND flash memory device additionally forms a dummy cell array that is not used for actual device operation between the memory cell array and the peripheral circuit region, and is formed in the same process as the memory cell array region.

Hereinafter, a method of manufacturing a NAND flash memory device according to the related art having a dummy cell array will be described.

1A to 1E are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to the prior art, and are cross-sectional views of an ASA-STI process.

First, as shown in FIG. 1A, a memory cell array region MC (hereinafter referred to as a memory cell region), a dummy cell array region DC (hereinafter referred to as a dummy cell region), and a peripheral circuit region PERI It provides a semiconductor substrate 10 defined by. In the memory cell region MC, an isolation layer (or a floating gate pattern) is formed at a higher density than that of the dummy cell region DC and the peripheral circuit region PERI. In the peripheral circuit region PERI, the device isolation layer is formed to have a larger width in the memory cell region MC and the dummy cell region DC. In the dummy cell region DC, the device isolation layer is formed at a lower density than that in the memory cell region MC.

Subsequently, the tunnel oxide layer 11, the floating silicon polysilicon layer 12, and the pad nitride layer may be formed on the substrate 10 including the memory cell region MC, the dummy cell region DC, and the peripheral circuit region PERI. 13) are deposited sequentially.

Next, a shallow trench isolation (STI) etching process is performed to etch the pad nitride layer 13, the polysilicon layer 12, the tunnel oxide layer 11, and the substrate 10 to form a plurality of trenches 14. At this time, the trench 14 is formed to have a different width according to each region (MC, DC, PERI). For example, the peripheral circuit region PERI is formed in the largest width, followed by the dummy cell region DC, followed by the memory cell region MC. In addition, the density of the trench 14 is higher in order of the memory cell region MC, the dummy cell region DC, and the peripheral circuit region PERI.

Subsequently, as shown in FIG. 1B, a high density plasma (HDP) film is deposited as an insulating film for device isolation so that a plurality of trenches 14 (see FIG. 1A) are completely embedded, and then a CMP process is performed. As a result, an isolation layer 15 is formed in the trench 14.

Subsequently, as shown in FIG. 1C, the pad nitride film 13 (see FIG. 1B) is removed.

Subsequently, a washing process is performed to remove the residue of the pad nitride film remaining without being completely removed.

A part of the device isolation film 15 is also etched by the pad nitride film 13 removing step and the cleaning step to have a profile similar to that of the same drawing.

Subsequently, as shown in FIG. 1D, the photoresist film is coated on the entire structure from which the pad nitride film 13 is removed, followed by an exposure and development process using a photo mask to form the photoresist pattern 16. . In this case, the photoresist pattern 16 has a structure in which the peripheral circuit region PERI is closed and the memory cell region MC and the dummy cell region DC are open.

Subsequently, an etching process 17 using the photoresist pattern 16 as an etching mask is performed to selectively control the height of the device isolation layer 15 of the memory cell region MC and the dummy cell region DC.

Subsequently, as shown in FIG. 1E, after the photoresist pattern 16 (see FIG. 1D) is removed, the dielectric film 18 and the polysilicon film 19 for the control gate are deposited on the upper surface of the entire structure.

However, the following problem occurs in the method of manufacturing the NAND flash memory device according to the prior art.

Specifically, as described with reference to FIG. 1D, in order to increase the coupling ratio of the memory device, the contact area between the dielectric film 18 and the polysilicon film 12 for floating gate should be increased. One of them is to etch the device isolation layer 15 formed in the memory cell region MC to control the EFH of the device isolation layer 15.

However, in the method of manufacturing a NAND flash memory device according to the related art, only the peripheral circuit region PERI is closed during the etching process 17, and other regions, that is, both the memory cell region MC and the dummy cell region DC are opened. Since the photoresist pattern 16 is used as an etching mask, the device isolation layer 15 formed in the dummy cell region DC having a lower pattern density of the device isolation layer 15 than that of the memory cell region MC is the memory cell region MC. More than the device isolation layer 15 formed in the etching is more etched to cause a problem that the height (H2) is controlled as low as 'H1'.

As described above, the step of the device isolation layer 15 between the memory cell region MC and the dummy cell region DC may be caused by the etching process 17. However, the direct cause may be due to the CMP process performed in FIG. 1B. In detail, the device isolation layer 15 formed in the dummy cell region DC adjacent to the peripheral circuit region PERI on which the device isolation layer 15 having a relatively wide width is formed may be a memory cell region relatively far from the peripheral circuit region PERI. More polishing than the element isolation film 15 formed in the MC (due to the dishing phenomenon described above). In general, the device isolation layer 15 formed in the dummy cell region DC after the CMP process has an EFH that is about 0 to about 100 μs lower than that of the device isolation layer 15 formed in the memory cell region MC.

Accordingly, the distance between the control gate polysilicon film 19 and the active region (channel region) deposited by the device isolation film 15 controlled relatively low in the dummy cell region DC and the active region (channel region) is controlled to be 120 Å or less. Even if there is no direct short between them, leakage current due to proximity effect is generated, and the program bias voltage applied to the control gate (approximately 18V) is dropped to the desired level. The device characteristics are degraded because the program bias voltage is not secured.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and in the manufacturing method of a NAND flash memory device having a dummy cell region formed between a memory cell region and a peripheral circuit region, control generated in the dummy cell region. It is an object of the present invention to provide a method for manufacturing a NAND flash memory device capable of preventing a leakage current between a gate and an active device.

According to an aspect of the present invention, a memory cell region, a dummy cell region, and a peripheral circuit region are defined to be adjacent to each other, and a plurality of the memory cell region, the dummy cell region, and the peripheral circuit region are respectively provided. Providing a semiconductor substrate having a device isolation layer formed thereon, and performing an etching process using an etch mask in which the dummy cell region and the peripheral circuit region are closed and the memory cell region is closed on the semiconductor substrate. A method of manufacturing a NAND flash memory device comprising the step of selectively etching the device isolation film formed in the to control the effective height.

According to another aspect of the present invention, there is provided a semiconductor substrate defined by a memory cell region, a dummy cell region, and a peripheral circuit region, and a gate insulating film and a floating gate on the semiconductor substrate. Forming a first polysilicon film and a pad nitride film, forming a plurality of trenches in the pad nitride film, the memory cell region, the dummy cell region, and the peripheral circuit region, respectively, and filling the plurality of trenches. Forming an isolation layer; removing the pad nitride layer; closing the dummy cell region and the peripheral circuit region on the semiconductor substrate from which the pad nitride layer is removed; Forming a small portion of the memory cell region by performing an etching process using the etching mask; Selectively recessing the separator, forming a dielectric film along the upper surface of the entire structure including the recessed device isolation film, and forming a second polysilicon film for the control gate on the dielectric film. A method of manufacturing a NAND flash memory device is provided.

As described above, in the method of manufacturing a NAND flash memory device according to the related art, a problem occurs because the height of the device isolation film formed in the dummy cell region is controlled to be low. An object of the present invention is to propose a method of controlling the height of the device isolation layer formed in the cell region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals (reference numerals) denote the same elements throughout the specification.

Example

2A to 2E are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention. For example, FIG.

First, as shown in FIG. 2A, a semiconductor substrate 110 defined as a memory cell region MC, a dummy cell region DC, and a peripheral circuit region PERI is provided. In the memory cell region MC, an isolation layer (or a floating gate pattern) is formed at a higher density than that of the dummy cell region DC and the peripheral circuit region PERI. In the peripheral circuit region PERI, the device isolation layer is formed to have a larger width in the memory cell region MC and the dummy cell region DC. In the dummy cell region DC, the device isolation layer is formed at a lower density than that in the memory cell region MC.

Subsequently, a gate insulating layer 111 in which FN tunneling occurs on the substrate 10 including the memory cell region MC, the dummy cell region DC, and the peripheral circuit region PERI, and the polysilicon layer 112 for floating gate. The buffer oxide film (not shown) and the pad nitride film 113 are sequentially deposited. Here, the gate insulating layer 111 is formed of a structure in which an oxide film and a nitride film are stacked in order to improve data retention characteristics, and the buffer oxide film is damaged when the polysilicon film 112 is damaged during the deposition process of the pad nitride film 113. It is formed to prevent that.

Subsequently, a plurality of trenches 114 are formed by etching the pad nitride layer 113, the buffer oxide layer, the polysilicon layer 112, the gate insulating layer 111, and the substrate 110 by performing an STI etching process. In this case, the trench 114 may be formed to have a different width according to each of the regions MC, DC, and PERI. For example, the peripheral circuit area PERI may be formed in the largest width, and then the dummy cell area DC and the memory cell area MC may be formed in the order. Of course, only a part of the dummy cell region DC and the memory cell region MC may be formed to have different widths, and the degree of freedom of overlapping with the photoresist pattern 116 used in the subsequent etching process 117 (see FIG. 2D). In consideration of the overlay margin, the polysilicon layer 112 adjacent to the memory cell area MC may be formed to have at least twice as much as other patterns. The trench 114 is formed at a high density in order of the memory cell region MC, the dummy cell region DC, and the peripheral circuit region PERI.

Subsequently, as illustrated in FIG. 2B, a CMP process is performed by depositing an HDP single layer or a PSZ (polisilazane) layer in a stacked structure as an insulating film for device isolation so that a plurality of trenches 114 (see FIG. 2A) are completely filled. As a result, an isolation layer 115 is formed in the trench 114.

Subsequently, as shown in FIG. 2C, the pad nitride film 113 (see FIG. 2B) is removed. In this case, the pad nitride layer 113 may be removed through an etching process using phosphoric acid (H ₃ PO ₄ ).

Subsequently, a washing process is performed to remove the residue of the pad nitride film remaining without being completely removed.

Subsequently, the pad nitride layer 113 may be removed to remove the exposed buffer oxide layer. In this case, the buffer oxide film may be left as it is without being removed. In this case, the buffer oxide film is removed during the etching process 117 (see FIG. 2D) to control the EFH of the subsequent device isolation film 115.

Subsequently, as shown in FIG. 2D, the photoresist film is coated on the entire structure from which the pad nitride film 113 is removed, and then the photoresist pattern 116 is formed by sequentially performing an exposure and development process using a photo mask. In this case, the photoresist pattern 116 has a structure in which the peripheral circuit region PERI and the dummy cell region DC are closed and only the memory cell region MC is opened.

Subsequently, an etching process 117 using the photoresist pattern 116 as an etching mask is performed to selectively recess only the device isolation layer 115 of the memory cell region MC to a predetermined depth. As a result, the EFH of the device isolation film 115 formed in the memory cell region MC is controlled.

Subsequently, as shown in FIG. 2E, after the photoresist pattern 116 (see FIG. 2D) is removed, the dielectric film 118 and the polysilicon film 119 for the control gate are deposited on the upper surface of the entire structure.

As described above, in the method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention, the height of the device isolation layer 115 formed in the dummy cell region DC may be set to the height of the device isolation layer 115 formed in the memory cell region MC. In order to control the height higher than the height, the etching mask used in the etching process 117 for adjusting the EFH of the device isolation layer 115 formed in the memory cell region MC is the memory cell region MC except the dummy cell region DC. It is formed in a structure that opens only the bay.

Although the technical spirit of the present invention has been described in detail in the embodiments, it should be noted that the above-described embodiments are for the purpose of description and not for the purpose of limitation. In particular, the embodiment of the present invention has been described only for the ASA-STI process, this can be applied to the SA-STI process as an example. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the etching process for adjusting the EFH of the device isolation layer formed in the memory cell region, the dummy cell region and the peripheral circuit region are closed and the dummy mask is opened by using the etching mask in which only the memory cell region is opened. By controlling the height of the device isolation layer formed in the cell region higher than the height of the device isolation layer formed in the memory cell region, it is possible to prevent the leakage current generated between the control gate and the active region in the dummy cell region, as in the prior art. The operating characteristics of the device can be improved.

Claims (6)

Providing a semiconductor substrate defined by a memory cell region, a dummy cell region, and a peripheral circuit region adjacent to each other, wherein a plurality of device isolation layers are formed in the memory cell region, the dummy cell region, and the peripheral circuit region, respectively; And The dummy cell region and the peripheral circuit region are closed on the semiconductor substrate, and the memory cell region is subjected to an etching process using an open etching mask to selectively etch an isolation layer formed in the memory cell region to control an effective height. Steps to Method of manufacturing a NAND flash memory device comprising a. Providing a semiconductor substrate defined by a memory cell region, a dummy cell region and a peripheral circuit region; Forming a gate insulating film, a first polysilicon film for a floating gate, and a pad nitride film on the semiconductor substrate; Forming a plurality of trenches in the memory cell region, the dummy cell region and the peripheral circuit region, respectively; Forming an isolation layer to fill the plurality of trenches; Removing the pad nitride film; Forming an etch mask in which the dummy cell region and the peripheral circuit region are closed and the memory cell region are open on the semiconductor substrate from which the pad nitride layer has been removed; Selectively recessing the device isolation layer formed in the memory cell region by performing an etching process using the etching mask; Forming a dielectric film along an upper surface of the entire structure including the recessed device isolation layer; And Forming a second polysilicon film for a control gate on the dielectric film Method of manufacturing a NAND flash memory device comprising a. The method of claim 2, And forming a buffer oxide film on the first polysilicon film after forming the first polysilicon film and before forming the pad nitride film. The method of claim 2, A NAND flash formed such that a width of a pattern formed in a boundary region between the dummy cell region and the memory cell region among the patterns of the plurality of first polysilicon films separated by the plurality of trenches has a larger width than the other patterns Method of manufacturing a memory device. The method of claim 4, wherein The end of the etching mask is formed to overlap the pattern formed in the boundary region of the dummy cell region and the memory cell region of the pattern of the first polysilicon layer. The method of claim 2, And forming a width of the device isolation layer formed in the peripheral circuit region to have a width greater than that of the device isolation layer formed in the memory cell region and the dummy cell region.

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