KR100452316B1 - Nonvolatile Semiconductor Device Manufacturing Method - Google Patents

Abstract

Disclosed is a method of manufacturing a nonvolatile semiconductor device in which a floating gate can be implemented in a size set by a design rule. A first conductive film and a buffer film are sequentially formed on the semiconductor substrate provided with the gate insulating film, an insulating film is formed thereon such that the surface of the buffer film is partially exposed, and then spacers are formed on the sidewalls of the insulating film, and The buffer film is etched using the insulating film and the spacer as a mask, and then the insulating film and the spacer are removed. Subsequently, in an oxidation process using the etched buffer film as a mask, an isolation insulating film is formed on the first conductive film, the buffer film is removed, and the lower conductive film is etched using the isolation insulating film as a mask. Forming a floating gate, and forming a tunneling insulating film on both edge portions of the isolation insulating film and the gate insulating film including the floating gate through an oxidation process, and then forming a predetermined portion on the isolation insulating film and the gate insulating film Over a predetermined portion, a control gate made of a second conductive film material is formed. As a result, the phenomenon in which the floating gate becomes larger than the design rule due to the buzz big generated by the oxidation process can be prevented, thereby realizing a highly integrated cell than the conventional case.

Description

Nonvolatile Semiconductor Device Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a non-volatile semiconductor device having a contactless, virtual ground structure. More specifically, the size of a floating gate is defined in a design rule. It relates to a non-volatile semiconductor device manufacturing method that can be implemented in the size set by the.

Nonvolatile semiconductor devices have the advantage of being capable of electrically erasing and storing data and preserving data even when power is not supplied, and have recently expanded its application in various fields.

Such nonvolatile semiconductor devices are classified into NAND type and NOR type according to the structure of the memory cell array, and each of them has advantages and disadvantages of high integration and high speed. Increasingly, applications are increasingly being used.

Among them, in the NOR-type nonvolatile semiconductor device directly related to the present invention, a plurality of memory cells constituted by a single transistor are connected in parallel to one bit line, and a drain is connected between a source connected to a bit line and a source connected to a common source line. Only one cell transistor is connected to the memory cell, so that the current of the memory cell is increased and high-speed operation is possible. However, due to the increase in the area occupied by the bit line contact and the source line, high integration of the memory device is difficult.

In the NOR type nonvolatile semiconductor device having the above characteristics, a memory cell is generally configured such that a floating gate and a control gate are stacked with an interlayer insulating film interposed therebetween, thereby storing data. A series of device operations related to over erase and read operations are performed in the following manner. At this time, the program related to the storage of data is made by the hot electron injection (HEI) or the Fowler-nordheim tunnel (FN) method, and the erasure related to erasing the data is performed by the FN tunnel method, here as an example In this case, we will look into the case where the program is implemented in the HEI method.

First, let's look at the program. When a voltage is applied between the bit line and the control gate to form a channel between the source and the drain, hot electrons are generated at the drain, which flows beyond the gate insulating film (or tunneling insulating film) barrier due to the voltage of the control gate. Is injected into the gate. As a result, a program is made and data is written to the erased cells.

As such, when the floating gate is filled with electrons, the threshold voltages of the memory cells are increased due to the electrons. Therefore, when the cell is read by supplying a supply voltage (3.3V or 5V) to the control gate connected to the word line, Because the threshold voltage prevents the channel from forming and no current flows, one state can be memorized.

On the other hand, if you want to erase again to store new information, you can ground the control gate and apply a high voltage to the source to supply a strong electric field across the gate insulating film between the floating gate and the substrate. It becomes thinner and the electrons stored in the floating gate in the FN tunnel manner penetrate through the thin insulating barrier and escape to the substrate at once. As a result, data is erased.

In this case, since there is no electron in the floating gate, the threshold voltage of the cell is lowered. Therefore, when the cell is read by applying a power supply voltage to the control gate, one state different from the first can be stored.

In other words, it can be seen that data reading is performed by applying an appropriate voltage to the bit line and the control gate of the selected cell to read the presence or absence of current in the memory cell transistor.

However, in the nonvolatile semiconductor device having the above structure, first, a memory cell is connected in parallel to a bit line, so that the threshold voltage (hereinafter referred to as Vth) of the selected cell transistor is applied to the control gate of the unselected cell ( For example, when the voltage is lower than 0 V, a malfunction occurs in which current flows regardless of whether the selected cell is turned on or off, and all cells are read as the on cells. Secondly, since excessive cell current flows from source to drain during HEI programming, there is a need for a high capacity pump that generates a voltage required for programming. do.

In order to solve this problem, recently, a nonvolatile semiconductor device having various structures called a split gate type has been proposed. 1 shows, for example, US Patent Application No. A cross-sectional view showing a single transistor structure of a nonvolatile semiconductor device disclosed in 5,045,488 is presented.

Referring to FIG. 1, a conventional nonvolatile semiconductor device having a split gate type structure has a floating gate 14a largely spaced apart from each other at predetermined portions of an active region on a semiconductor substrate 10 provided with a gate insulating film 12. ) Is formed, an isolation insulating film 20 is formed on the floating gate 14a, and a predetermined portion on the substrate 10 including the isolation insulating film 20 and one side of the floating gate 14a is formed. A tunneling insulating film 22 for data erasing is formed, and a control gate 24a is formed in a predetermined portion on the insulating films 20 and 22 so that the floating gate 14a is spaced apart from each other by a predetermined interval. Are respectively connected to the common source region 26 formed in the substrate 10, the channel region formed under the floating gate 14a, and the channel region formed under the control gate. It can be seen that it is configured to have a structure which is connected in series with each other on the substrate (10).

Therefore, the nonvolatile semiconductor device having the above structure is manufactured through the following sixth step as can be seen from the process flow chart shown in FIGS. 2A to 2F. For convenience, the process proceeds with respect to only one structure among the split floating gates connected to the common source line 26.

As a first step, as shown in FIG. 2A, the gate insulating film 12, the first conductive film 14 made of polysilicon, and the buffer film made of nitride are formed on the semiconductor substrate 10 having the gate insulating film 12. The buffer film 16 is sequentially formed, and then the photoresist pattern 18 is formed thereon so that the surface of the complete layer 16 is partially exposed.

As a second step, as shown in FIG. 2B, the buffer layer 16 is dry-etched using the photoresist pattern 18 as a mask, and the photoresist pattern 18 is removed.

As a third step, as shown in FIG. 2C, an isolation insulating film 20 is selectively formed only in a portion which is not protected by the buffer film 16 by an oxidation process using the buffer film 16 as a mask. The buffer film 16 is removed.

As a fourth step, as shown in FIG. 2D, the first conductive film 14 is dry-etched using the insulating film 20 as a mask to form a floating gate 14a made of polysilicon, and an oxidation process is performed. After the thin tunneling insulating film 22 is formed on the gate insulating film 12 including both edge portions of the insulating insulating film 20 and the floating gate 14a, the tunneling insulating film 22 and the isolation insulating film ( A second conductive film 24 made of polysilicon is formed on 20).

As a fifth step, as shown in FIG. 2E, the second conductive layer 24 is dry-etched using an etching mask defining a portion where the control gate is to be formed, thereby forming the control gate 24a made of polysilicon. The photoresist pattern 18 is formed on a predetermined portion of the isolation insulating film 20 including the control gate 24a by using a photolithography process, and then ion implanted with a high concentration of impurities onto the substrate 10. The source region 26 is formed in the inside.

As a sixth step, the process of the present process is completed by removing the photoresist pattern 18 as shown in FIG. 2F.

When the nonvolatile semiconductor device is fabricated as described above, the selection transistor of the memory cell transistor described above typically has a Vth of about 1.0 V, and the floating gate has a high Vth and erased in the case of a programmed cell. In the case of an old cell, it has a low Vth (in some cases, -Vth).

In this case, even though the transistor of the floating gate has -Vth (the channel is formed even when 0V is applied to the control gate) due to over erase, the selection transistor is turned off. It is possible to prevent the current from flowing regardless of on or off, thereby preventing malfunction of the device without managing Vth tightly.

When manufacturing a nonvolatile semiconductor device having the above structure, a program related to data storage is performed in the following manner. That is, when a high voltage is applied to the source region 26 of the memory cell, the floating gate is induced to a predetermined voltage by the coupling by the voltage. At this time, a predetermined voltage is applied to the control gate to When the channel is formed between the drains, the electrons generated at the drains are injected into the floating gate by the HEI method. As a result, a program is made and data is written to the erased cell.

In this process, if the voltage applied to the control gate is properly adjusted, the electric field in the vicinity of the floating gate edge can be increased, thereby increasing the program effect as well as flowing between the source and the drain. Since the current can be made small and power consumption is also reduced, a high-capacity pump is not required for programming by the HEI method.

On the other hand, the erase is applied by a high voltage to the control gate 24a by the electric field between the control gate 24a and the floating gate 14a, the electrons stored in the floating gate passes through the tunneling insulating film 22 in the FN tunnel method By moving out toward the substrate 10 at once, the data is erased.

In this case, data reading is performed by applying an appropriate voltage to the bit line and the control gate connected to the drain of the memory cell to read the current of the memory cell transistor.

However, the non-volatile semiconductor device, as mentioned above, has a number of advantages (e.g., no need for tight management of Vth and no need for a high-capacity pump for programming by the HEI method). In addition, due to the relationship between forming the floating gate and the gate of the selection transistor during device fabrication, the gate size of the memory cell becomes longer than that of the conventional nonvolatile semiconductor device, and thus has a disadvantage in that high integration of the semiconductor device is disadvantageous.

This drawback is that when the floating gate is formed, the insulating insulating film is grown thereon, and the size of the floating gate is increased due to the bird's beak generated by the oxidation process, which is larger than the design rule. In this case, when the size of the floating gate increases due to Buzz Big, high integration of the semiconductor device cannot be achieved. Therefore, in order to compensate for this, the size of the floating gate must be defined smaller in the circuit design. do. However, in order to reduce the width of the floating gate due to the limitation of the application of the photolithography (photolithography), it is necessary to proceed with the process using high-performance, high-cost equipment to improve this. This is difficult to apply at present because of the process cost increase.

Accordingly, an object of the present invention is to apply a photolithography process to proceed with the device manufacturing process to bring the size of the floating gate to the same as the design rules, thereby achieving a high integration of the nonvolatile semiconductor device To provide a manufacturing method.

In order to achieve the above object, in a first embodiment of the present invention, a step of sequentially forming a first conductive film and a buffer film on a semiconductor substrate provided with a gate insulating film, and a predetermined portion of the surface of the buffer film are exposed thereon. Forming an insulating film, forming a spacer on sidewalls of the insulating film, etching the buffer film using the insulating film and the spacer as a mask, removing the insulating film and the spacer, and etching the In the oxidation process using the buffer film as a mask, forming an isolation insulating film on the first conductive film, removing the buffer film, and etching the first conductive film under the etching using the isolation insulating film as a mask to form a floating gate. Both edges of the isolation insulating film through a forming step and an oxidation step And forming a tunneling insulating film on the gate insulating film including the floating gate, and forming a control gate of a second conductive film material over a predetermined portion on the isolation insulating film and a predetermined portion on the gate insulating film. A nonvolatile semiconductor device manufacturing method is provided.

In order to achieve the above object, in the second embodiment of the present invention, there is provided a process for forming a first conductive film on a semiconductor substrate provided with a gate insulating film, and an insulating film thereon so as to expose a predetermined portion of the surface of the first conductive film. Forming an isolation insulating film on the first conductive film by sequentially forming a buffer film, forming a spacer on sidewalls of the insulating film and the buffer film, and oxidizing the buffer film and the spacer as a mask, Removing the buffer layer, the insulating layer, and the spacer; forming a floating gate by etching the lower first conductive layer using the isolation insulating layer as a mask; and oxidizing the insulating layer. On the gate insulating film including both edge portions and the floating gate, a tunnel Forming an insulating film and, over a predetermined portion on a predetermined portion of the gate insulating film on the isolation insulating film, the nonvolatile semiconductor device manufacturing method comprising the step of forming the control gate of the second conductive film forming material is provided.

When the process proceeds as described above, the phenomenon in which the floating gate becomes larger than the design rule due to the buzz big generated by the oxidation process can be prevented, and thus, a cell having a smaller size can be realized.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, when forming an isolation insulating layer of a nonvolatile semiconductor device having a split gate type structure, an oxidation process is performed using a spacer made of polysilicon or an optical type of a floating gate is formed using an spacer made of an oxide film. By defining below the size that is allowed in each process and proceeding the process by oxidizing process, it is possible to prevent the phenomenon that the size of the floating gate is increased compared to the design rule due to the occurrence of buzz big As a technique with reference to FIGS. 3A to 3G and 4A to 4F, the following description will be made.

3A to 3G show a process purity diagram illustrating a method of manufacturing a nonvolatile semiconductor device according to a first embodiment of the present invention, and FIGS. 4A to 4F illustrate a nonvolatile semiconductor according to a second embodiment of the present invention. Process purity showing the device manufacturing method is shown.

First, the first embodiment will be described. In the above embodiment, the size of the floating gate is defined to be less than or equal to the size allowed by the photolithography process using a spacer made of an oxide film, and the process is performed in such a manner that the oxidation process is performed. If the description is divided into steps as follows.

As a first step, as shown in FIG. 3A, a gate insulating film 102 having a thickness of 70 to 150 Å is formed on the substrate 100 for insulation between the semiconductor substrate 100 and a floating gate to be formed later. The first conductive film 104 made of polysilicon and the buffer film 106 made of nitride film are formed thereon to have a thickness of 1000 to 2000 kPa and 200 to 1500 kPa, respectively. Subsequently, in order to define a small size of the floating gate, an insulating film 108 made of an oxide film material is formed on the buffer film 106 to a thickness of 1000 to 2000 micrometers, and a photoresist film is exposed thereon to expose a predetermined portion of the surface of the insulating film 108. The pattern 110 is formed.

As a second step, as shown in FIG. 3B, the photoresist pattern 110 is used as a mask to dry-etch the insulating film 108 below, the photoresist pattern 110 is removed, and then an oxide film or a polysilicon material is formed on the entire surface thereof. An arbitrary film of the thickness of 1000 ~ 2000Å, and anisotropic dry etching to form a spacer 112 of the oxide film (or polysilicon) material.

As a third step, as shown in FIG. 3C, the buffer layer 106 is etched using the insulating layer 108 and the spacer 112 as a mask, and the insulating layer 108 and the spacer 112 are subjected to a wet etching process. ).

As a fourth step, as shown in FIG. 3D, an oxidation process using an etched buffer layer 106 as a mask is performed. The isolation insulating layer 114 is selectively provided only on a portion which is not protected by the buffer layer 106. Is formed and the buffer film 106 is removed.

As a fifth step, as shown in FIG. 3E, the first conductive layer 104 is dry-etched using the isolation insulating layer 114 as a mask. As a result, it is possible to obtain the floating gate 104a of polysilicon material formed smaller than that of the conventional process. Subsequently, a tunneling insulating film 116 having a thickness of 50 to 200 Å is formed on the gate insulating film 102 including both edge portions of the isolation insulating film 114 and the floating gate 104a through an oxidation process. On the 116 and the isolation insulating film 114, a second conductive film 118 made of polysilicon is formed to a thickness of 1000 to 2000 kPa. The formation of the tunneling insulating film 116 as described above is intended to serve as an intermediate medium through which the electrons exit the substrate during insulation and erasure between the floating gate 104a and the control gate.

As a sixth step, as shown in FIG. 3F, the second conductive layer 118 is dry-etched using an etching mask defining a portion where the control gate is to be formed, thereby forming the control gate 118a made of polysilicon. The photoresist pattern 110 is formed on a predetermined portion of the isolation insulating layer 114 including the control gate 118a by using a photolithography process, and then ion implanted with a high concentration of impurities onto the substrate 100. The source region 120 is formed in the inside.

As a seventh step, the process of the present process is completed by removing the photosensitive film pattern 110 as shown in FIG. 3G.

In the case of manufacturing the nonvolatile semiconductor device as described above, the size of the floating gate 104a can be defined to be smaller than or equal to the size allowed by the photolithography process using the oxide film or the polysilicon spacer 112. Smaller cells can be implemented.

Next, a second embodiment of the present invention will be described. The embodiment is a case where the oxidation process is performed using a spacer made of polysilicon, and this is largely divided into six steps. Here, only the steps that proceed in the same manner as in the first embodiment will be briefly described, and description will be given focusing on the differentiation.

As a first step, as shown in FIG. 4A, a gate insulating film 202 having a thickness of 70 to 150 Å is formed on the semiconductor substrate 200, and a polysilicon first conductive film 204 and an oxide film are formed thereon. The insulating film 206 and the buffer film 208 made of a nitride film are formed to have a thickness of 1000 to 2000 kPa, 70 to 150 kPa, and 200 to 1500 kPa, respectively. Subsequently, the photoresist pattern 210 is formed thereon so that the surface of the buffer layer 208 is partially exposed.

As a second step, as shown in FIG. 4B, the buffer layer 208 and the insulating layer 206 are sequentially etched using the photoresist pattern 210 as a mask, the photoresist pattern 210 is removed, and then poly An arbitrary film of silicon is formed to a thickness of 1000 ~ 2000Å, and anisotropic dry etching to form a spacer 212 of a polysilicon material.

As a third step, as shown in FIG. 4C, an isolation insulating film 214 is formed by an oxidation process using the etched buffer film 208 and the spacer 212 as a mask, and the spacer 212 and the buffer film 208 are formed. ) And the insulating film 206 are removed. The oxidation process is performed in the state where the spacer 212 is present because the occurrence of buzz big in the isolation insulating layer 214 can be minimized during the oxidation process due to the polysilicon constituting the spacer.

As a fourth step, as shown in FIG. 4D, the first conductive layer 204 is dry-etched using the isolation insulating layer 214 as a mask. As a result, the floating gate 204a made of polysilicon can be obtained smaller than that of the conventional process. Subsequently, a tunneling insulating film 216 having a thickness of 50 to 200 Å is formed on the gate insulating film 202 including both edge portions of the isolation insulating film 214 and the floating gate 204a through an oxidation process. On the 216 and the isolation insulating film 214, a second conductive film 218 made of polysilicon is formed to a thickness of 1000 to 2000 mW.

As a fifth step, as shown in FIG. 3E, the second conductive layer 218 is dry-etched using an etching mask defining a portion where the control gate is to be formed, thereby forming the control gate 218a made of polysilicon. The photoresist pattern 210 is formed on a predetermined portion of the isolation insulating film 214 including the control gate 218a by using a photolithography process, and then a high concentration of impurities are ion-implanted onto the substrate 200 to source the region 220. ).

As a sixth step, the photoresist pattern 210 is removed as shown in FIG. 3F, thereby completing the process.

As such, when the nonvolatile semiconductor device is manufactured, the size of the floating gate 204a may be made smaller using the polysilicon spacer 212, and thus, a smaller cell may be realized. .

As described above, according to the present invention, an oxide film or a polysilicon spacer may be used to define the size of the floating gate to be smaller than or equal to a size allowed in the photoetch process, or a polysilicon spacer may be used as a buzz big. By forming an isolation insulating film in a manner that minimizes the occurrence of the occurrence, it is possible to prevent the floating gate from becoming larger than the design rule due to the buzz big generated by the oxidation process, thereby realizing a more integrated cell than in the conventional case. Will be.

1 is a cross-sectional view showing a conventional nonvolatile semiconductor device structure;

2A through 2F are process flowcharts illustrating the method of manufacturing the semiconductor device of FIG. 1;

3A to 3G are process flowcharts illustrating a method of manufacturing a nonvolatile semiconductor device according to a first embodiment of the present invention;

4A to 4F are process flowcharts illustrating a method of manufacturing a nonvolatile semiconductor device according to a second embodiment of the present invention.

Claims (19)

Sequentially forming a first conductive film and a buffer film on the semiconductor substrate provided with the gate insulating film; Forming an insulating film thereon such that the surface of the buffer film is exposed to a predetermined portion; Forming a spacer on sidewalls of the insulating film; Etching the buffer film using the insulating film and the spacer as a mask, and removing the insulating film and the spacer; An oxidation process using the etched buffer film as a mask, forming an isolation insulating film on a first conductive film, and removing the buffer film; Using the isolation insulating film as a mask to etch a first conductive film thereunder to form a floating gate; Forming a tunneling insulating film on the gate insulating film including both edge portions of the isolation insulating film and the floating gate through an oxidation process; And forming a control gate of a second conductive film material over a predetermined portion on the isolation insulating film and a predetermined portion on the gate insulating film. The method of claim 1, wherein the gate insulating layer is formed to a thickness of 70 to 150 kV. The method of claim 1, wherein the first and second conductive films are formed of polysilicon having a thickness of 1000 to 2000 GPa. The method of claim 1, wherein the buffer film is formed to a thickness of 200 to 1500 Å. The method of claim 1, wherein the insulating film is formed of an oxide film having a thickness of 1000 to 2000 GPa. The method of claim 1, wherein the forming of spacers on sidewalls of the insulating film comprises forming a random film on the buffer film including the insulating film, and performing anisotropic dry etching of the random film. Semiconductor device manufacturing method. 7. The method of claim 6, wherein the optional film is formed of an oxide film or polysilicon. 7. The method of claim 6, wherein the optional film is formed to a thickness of 1000 to 2000 GPa. The method of claim 1, wherein the insulating layer and the spacer are removed by a wet etching method. The method of claim 1, wherein the tunneling insulating layer is formed to a thickness of 50 to 200 μm. Forming a first conductive film on the semiconductor substrate provided with the gate insulating film; Sequentially forming an insulating film and a buffer film thereon such that the surface of the first conductive film is partially exposed; Forming a spacer on sidewalls of the insulating film and the buffer film; In an oxidation process using the buffer film and the spacer as a mask, forming an isolation insulating film on a first conductive film, removing the buffer film, the insulating film, and the spacer; Using the isolation insulating film as a mask to etch a first conductive film thereunder to form a floating gate; Forming a tunneling insulating film on the gate insulating film including both edge portions of the isolation insulating film and the floating gate through an oxidation process; And forming a control gate of a second conductive film material over a predetermined portion on the isolation insulating film and a predetermined portion on the gate insulating film. The method of claim 11, wherein the gate insulating layer is formed to a thickness of 70 to 150 kV. 12. The method of claim 11, wherein the first and second conductive films are formed of polysilicon having a thickness of 1000 to 2000 GPa. 12. The method of claim 11, wherein the insulating film is formed of an oxide film having a thickness of 70 to 150 GPa. 12. The method of claim 11, wherein the buffer film is formed to a thickness of 200 to 1500 kPa. The process of claim 11, wherein the forming of spacers on sidewalls of the insulating film and the buffer film comprises: forming a random film on the first conductive film including the insulating film and the buffer film; and anisotropic dry etching the optional film. Method for manufacturing a nonvolatile semiconductor device, characterized in that consisting of. 17. The method of claim 16, wherein the arbitrary film is formed of polysilicon. 17. The method of claim 16, wherein the arbitrary film is formed to a thickness of 1000 to 2000 microns. The method of claim 11, wherein the tunneling insulating layer is formed to have a thickness of 50 to 200 μm.

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