JPH0730001A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, in which a punch-through phenomenon is prevented and memory erasing is carried out efficiency without generation of an erroneous operation. CONSTITUTION:A floating gate 7 is formed on a control gate 3, and a thin film transistor 10 is formed on the floating gate 7. An auxiliary gate electrode 13 is formed on the above-mentioned thin film transistor 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a non-volatile memory.

[0002]

2. Description of the Related Art Conventionally, a non-volatile memory is known as one of semiconductor devices. FIG. 28 is a sectional view showing a conventional nonvolatile memory. Referring to FIG. 28, in the conventional nonvolatile memory, the source diffusion layer 102 and the drain diffusion layer 103 are formed on the main surface of the semiconductor substrate 101 at predetermined intervals. Semiconductor substrate 101 located between source diffusion layer 102 and drain diffusion layer 103
Floating gate 105 is formed on the main surface of via inter-gate-substrate insulating film 104. A control gate 107 is formed on the floating gate 105 via a gate insulating film 106.

Next, the operation of the conventional nonvolatile memory will be described with reference to FIG. First, in the write operation, the control gate 107 and the drain diffusion layer 10
A voltage is applied to 3. The source diffusion layer 102 is grounded.
As a result, a voltage determined by the ratio of the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the semiconductor substrate is applied to the floating gate 105. As a result, an inversion layer (channel) is formed on the surface of the semiconductor substrate 101. As a result, an electron current flows between the source diffusion layer 102 and the drain diffusion layer 103.

The electrons in the channel flow toward the drain diffusion layer 103 while receiving energy from the drain electric field. The potential barrier of some of the electrons accelerated in the channel and brought into a high energy state in the vicinity of the drain diffusion layer 103 becomes higher than the potential barrier of 3.9 eV of the gate-substrate insulating film 104. The electrons having a potential barrier higher than 3.9 eV are injected into the floating gate 105. As a result, the potential of the floating gate 105 decreases and the threshold voltage of the floating gate transistor seen from the control gate 107 increases. In this way, the write operation is performed.

Next, in the erase operation, the control gate 107 is grounded, the drain diffusion layer 103 is opened, and a high voltage is applied to the source diffusion layer 102. As a result, the electrons stored in the floating gate 105 are extracted toward the source diffusion layer 102. As a result, the potential of the floating gate 105 increases and the threshold voltage of the floating gate transistor seen from the control gate 107 decreases. In this way, the erase operation is performed. The high and low states of the threshold voltage during the write operation and the erase operation are stored as information in association with "1" and "0".

[0006]

FIG. 29 is a characteristic diagram for explaining a writing characteristic of a conventional non-volatile memory, and FIG. 30 is a characteristic diagram for explaining an erasing characteristic of a conventional non-volatile memory. is there. With reference to FIGS. 29 and 30, in the conventional nonvolatile memory, writing is performed for 100 μsec (10
^-4 sec), erase is 100 msec
(10 ^-1 sec). That is, the erase operation takes 1000 times as long as the write operation.

Therefore, in order to increase the circuit speed, it is necessary to shorten the erase time. In order to shorten the erasing time, the extraction efficiency should be increased.

In order to improve the extraction efficiency, the potential of the source diffusion layer 102 at the time of erasing is increased (the potential difference between the floating gate 105 and the source diffusion layer 102 is increased) or the film of the gate-substrate insulating film 104. Two methods of reducing the thickness can be considered.

However, if the extraction efficiency at the time of erasing is increased by the above-mentioned two methods, there arises a disadvantage that the injection efficiency at the time of erasing also increases. This will be described in detail below.

FIG. 31 is a sectional view showing the states of the depletion layer when the source potential of the source diffusion layer 102 at the time of erasing is high and when it is low. Referring to FIG. 31, when the source potential is increased to increase the extraction efficiency during erasing, the depletion layer around the source diffusion layer 102 extends to the drain diffusion layer 103 side. Carriers are thermally generated on the side of the drain diffusion layer 103 in the extended depletion layer, and the carriers are generated by the source electric field in the depletion layer.
Proceed while accelerating toward 2. Some of the carriers in the high energy state are injected into the floating gate 105 even though they are in the erased state. As a result, there is a problem that a malfunction occurs when erasing data.

Further, at the time of erasing, the floating gate 1
05 and the source diffusion layer 102 have a large potential difference,
The region where the floating gate 105 and the source diffusion layer 102 overlap (the region under the floating gate 105 of the source diffusion layer 102) is inverted. For this reason,
Carriers are generated by band-to-band tunneling. Holes of the generated carriers are generated along the electric field between the floating gate and the source, and the insulating film 104 between the gate substrates is formed.
Alternatively, it is injected into the floating gate 105.
When holes are injected into the inter-gate-substrate insulating film 104 as described above, there is a problem that the film quality of the inter-gate-substrate insulating film 104 is deteriorated and the reliability of the device is lowered.

The above-mentioned problems are caused by the inter-gate-substrate insulating film 1
The same occurs when the film thickness of 04 is reduced. Figure 32
FIG. 4 is a cross-sectional view showing states of a depletion layer when the thickness of the inter-gate-substrate insulating film 104 is thick and when it is thin. Referring to FIG. 32, when the film thickness of the inter-gate-substrate insulating film 104 is thin, the thickness of the depletion layer in the channel region is thicker than when it is thick. As a result, there are problems such as the above-mentioned malfunction at the time of erasing and deterioration of the film quality of the inter-gate-substrate insulating film 104.

Further, there is a problem that a punch through phenomenon occurs with the miniaturization of the element. The punch-through phenomenon is a phenomenon in which, in a normal transistor, the gate length becomes short, the depletion layer near the drain reaches the source when the drain voltage is applied, and a current proportional to the drain voltage that cannot be controlled by the gate voltage flows. Such a punch-through phenomenon also occurs when the source and the drain are exchanged.

FIG. 33 is a sectional view for explaining the punch-through phenomenon of the conventional nonvolatile memory. Referring to FIG. 33, in the conventional nonvolatile memory, since a high voltage is applied to the source diffusion layer 102 at the time of erasing, the source depletion layer 11
0 reaches the drain depletion layer 111, and a punch-through phenomenon occurs. When such a punch through phenomenon occurs, the control gate 107 and the floating gate 10
There is a problem in that a current that cannot be controlled by the voltage of 5 flows, leading to malfunction of the element.

The present invention has been made to solve the above problems, and an object of the present invention is to effectively prevent a punch-through phenomenon in a semiconductor device.

An object of the present invention is to improve the extraction efficiency during erasing in a semiconductor device without causing malfunction during erasing and deterioration of the film quality of the gate insulating film.

[0017]

A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a main surface, and a control electrode formed in a predetermined region on the main surface of the semiconductor substrate via a first insulating film. , A charge storage electrode formed on the control electrode via the second insulating film, and a thin film transistor formed on the charge storage electrode via the third insulating film.

According to another aspect of the semiconductor device of the present invention, a semiconductor substrate having a main surface, a control electrode formed in a predetermined region on the main surface of the semiconductor substrate via a first insulating film, and a control electrode on the control electrode are provided. A charge storage electrode formed via the second insulating film, a thin film transistor formed on the charge storage electrode via the third insulating film, and an auxiliary gate electrode formed on the thin film transistor. There is.

[0019]

In the semiconductor device according to the first aspect, the control electrode is formed on the semiconductor substrate, the charge storage electrode is formed on the control electrode, and the thin film transistor is formed on the charge storage electrode. When a nonvolatile memory is formed by such a semiconductor device, the thin film transistor becomes a memory cell transistor. Since the film thickness of the thin film transistor can be made approximately equal to the channel depth, the punch through phenomenon is effectively prevented.

In the semiconductor device according to the second aspect, the control electrode is formed on the semiconductor substrate, the charge storage electrode is formed on the control electrode, and the thin film transistor is formed on the charge storage electrode. The same effect as that of the first aspect can be obtained. Furthermore, since the auxiliary gate electrode is formed on the thin film transistor, a negative voltage is applied to the auxiliary gate electrode during the erase operation, so that a current path formed between the source region and the drain region during the erase operation. Is effectively blocked. As a result, no malfunction occurs even when a high voltage is applied to the source region or the gate insulating film is thinned during erasing.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a nonvolatile memory according to an embodiment of the present invention. FIG. 2 is a sectional view taken along the line AA of the nonvolatile memory shown in FIG. With reference to FIGS. 1 and 2, in the nonvolatile memory according to this embodiment, a polysilicon layer having a thickness of about 300 nm is formed on a semiconductor substrate 1 via an inter-gate-substrate insulating film 2 having a thickness of about 100 nm. Control gate electrode 3
Are formed. A floating gate 7 made of polysilicon having a thickness of about 100 nm is formed on the control gate 3 via an oxide film 4, a nitride film 5 and an oxide film 6 having a thickness of about 10 nm.

Sidewall oxide films 8 are formed on the sidewalls of the control gate 3, oxide film 4, nitride film 5, oxide film 6 and floating gate 7. An insulating film 9 having a thickness of about 10 nm is formed on the floating gate 7, the sidewall oxide film 8 and the substrate-gate insulating film 2. 1 on the insulating film 9
A thin film transistor 10 formed of a polysilicon layer having a thickness of about 00 nm is formed.

Channel region 10 of thin film transistor 10
A protective film 11 whose surface is flattened is formed so as to substantially cover the portions other than c. An oxide film 12 having a thickness of about 20 nm is formed on the protective film 11 and the channel region 10c of the thin film transistor 10. On the oxide film 12, a top gate (auxiliary gate) 1 whose end is located almost on the center line of the control gate 3
3 is formed.

In the present embodiment, as described above, the floating gate 7 is formed on the control gate 3 and the thin film transistor 10 is formed on the floating gate 7, so that the thin film transistor 10 becomes a memory cell transistor. The effect is obtained.

That is, since the thin film transistor 10 can have a film thickness of about the same as the channel depth,
The punch-through phenomenon, which has been a problem in the past, can be effectively prevented. Specifically, since the thin film transistor 10 can be made thin, the voltage flowing through the floating gate 7 can completely control the current flowing between the drain diffusion layer 10a and the source diffusion layer 10b. As a result, the punch-through phenomenon, which is a phenomenon in which a current that cannot be controlled by the voltage of the floating gate 7 flows, can be effectively prevented.

Further, in the present embodiment, the thin film transistor 1
Top gate (auxiliary gate) via oxide film 12
By forming 13, it is possible to solve the conventional problem that writing is simultaneously performed during the erase operation. That is, by applying a negative voltage to the top gate 13 during erasing, the thin film transistor 10
Holes having a polarity opposite to that of electrons can be induced in the current path inside. As a result, the current path formed between the source diffusion layer 10b and the drain diffusion layer 10a during erasing can be blocked. In this way, the drain diffusion layer 1 generated at the time of erasing data by the top gate 13
Since the current path between 0a and the source diffusion layer 10b can be effectively blocked, the source diffusion layer 10b can be erased at the time of erasing.
Even if a higher voltage is applied, the disadvantage that electrons are injected into the floating gate 7 due to the formation of a current path between the drain diffusion layer 10a and the source diffusion layer 10b as in the conventional case is prevented. be able to. Therefore, in this embodiment, a high voltage can be applied to the source diffusion layer 10b without causing a malfunction when erasing data. As a result, the erasing efficiency can be improved without causing a malfunction. As a result, it is possible to speed up the circuit by shortening the erase time.

As the voltage applied to the top gate 13, a voltage that does not invert the drain diffusion layer 10a side is applied. That is, if an inversion layer is formed on the surface by applying a voltage to the top gate 13, this becomes a channel (current path), so a voltage that does not invert the surface is applied to the top gate 13.

The relationship between the source applied voltage applied to the source diffusion layer 10b and the voltage applied to the top gate 13 at the time of erasing will be described below. When a negative voltage is applied to the top gate 13, it is pulled by this potential and a negative potential portion appears in the channel. If the negative potential of the channel at this time is V ₁ (V ₁ <0), the potential difference in the channel direction of the source diffusion layer 10 b is effectively equal to the source applied voltage V _S |
It is a value obtained by adding V ₁ |. If this potential difference V _S + | V ₁ | becomes too large, the junction of the source is destroyed, which is not preferable. If the junction breakdown voltage of the source is BV _S , then | V ₁
The maximum value of | is represented by the following equation (1) in consideration of a margin of about 2V.

| V ₁ | = BV _S −V _S −2 [V] (1) Referring to the above formula (1), the voltage applied to the top gate 13 is the potential at the end of the drain diffusion layer 10 a. Is preferably given so as to be the potential | V ₁ | of the above formula (1). Specifically, for example, the 16M flash EEPROM is a type of non-volatile memory, the negative potential of the channel | V ₁ | is the source junction breakdown voltage BV _S of formula (1) 12
It becomes a value obtained by substituting V and 9 V into the source applied voltage V _S. That is, the negative potential of the channel becomes | V ₁ | = 1 (V).

Here, when the thickness of the oxide film 12 serving as the gate oxide film of the top gate 13 is 10 nm or less, the voltage applied to the top gate 13 is applied to almost the channel, so that -1 is applied to the top gate 13. It is sufficient to apply the voltage of (V).

Further, in this embodiment, the insulating film between the control gate 3 and the floating gate 7 is formed in a three-layer structure consisting of the oxide film 4, the nitride film 5 and the oxide film 6. This is for the following reason. That is, in order to improve writing and erasing characteristics, it is preferable that the potential of the floating gate 7 is high. The potential of the floating gate increases as the capacitance between the control gate 3 and the floating gate 7 increases. The capacitance between the control gate 3 and the floating gate 7 can be increased by reducing the film thickness of the insulating film interposed between them or by using an insulating film having a high dielectric constant.

If the thickness of the insulating film is too thin, the life of the insulating film will be shortened. Also,
If the insulating film is entirely formed of the nitride film 5 having a high dielectric constant, the insulating property of the nitride film 5 is low, so that a leak current easily flows. Therefore, it has a three-layer structure in which both sides of the nitride film 5 are sandwiched by the oxide films 4 and 6 having high insulating properties.

As a result, the thickness of the insulating film can be reduced while suppressing the leak current as much as possible, and the dielectric constant of the insulating film can be increased. As a result, the capacitance between the control gate 3 and the floating gate 7 becomes high, and the potential of the floating gate 7 can be made higher than in the conventional case. As a result, the write / erase characteristics can be improved as compared with the conventional case.

Next, the operation of the nonvolatile memory of this embodiment will be described with reference to FIG. First, the write operation is the same as the conventional one. That is, a voltage is applied to the control gate 3 and the drain diffusion layer 10a, and the source diffusion layer 10b is grounded. As a result, a voltage determined by the ratio of the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the thin film semiconductor layer is generated in the floating gate 7. As a result, an inversion layer is formed on the surface of the channel region 10c of the thin film transistor 10 on the floating gate 7 side. As a result, electrons flow between the drain diffusion layer 10a and the source diffusion layer 10b. Among these electrons, electrons (hot electrons) accelerated to a high energy state by the drain electric field cross the potential barrier of the oxide film 9 and are injected into the floating gate 7.

In the erase operation, the control gate 3 is grounded, the drain diffusion layer 10a is opened, and a high voltage is applied to the source diffusion layer 10b. Further, a negative voltage is applied to the top gate 13. The extraction of the electrons stored in the floating gate 7 is the same as the conventional one.

Here, by applying a negative voltage to the top gate 13, holes having a polarity opposite to that of electrons can be induced in the current path in the thin film transistor 10. As a result, the current path can be electrically cut off. The thin film transistor 10 having a small film thickness
By using, it is possible to easily cause the potential of the top gate 13 to act even on the channel portion of the interface on the floating gate 7 side.

3 to 27 are a plan view, a sectional view and a perspective view for explaining a manufacturing process of the nonvolatile memory shown in FIGS. 1 and 2.

Next, the manufacturing process of the non-volatile memory will be described with reference to FIGS.

The manufacturing process described below is a manufacturing process of a memory cell transistor having a gate length of about 0.5 μm. Since the peripheral circuit section and the wiring section are the same as the conventional ones, the manufacturing process thereof is omitted.

(1) First, as shown in FIGS. 3 and 4, a P-type semiconductor substrate 1 is formed on the P-type semiconductor substrate 1 by thermal oxidation or the like.
The oxide film 2 having a thickness of about 0 nm is formed. An n-type polysilicon layer 3a is formed on oxide film 2 with a thickness of about 300 nm. Then, an oxide film 4a and a nitride film 5a each having a thickness of about 10 nm are formed on the polysilicon layer 3a.
And an oxide film 6a is formed. 100n on the oxide film 6a
An n-type polysilicon layer 7a is formed with a thickness of about m.

(2) Next, as shown in FIGS. 5 and 6, a resist 14 is formed on the polysilicon layer 7a so as to form the channel width of the floating gate. Only the polysilicon layer 7a is anisotropically etched using the resist 14 as a mask, and then the resist 14 is removed. As a result, the polysilicon layer 7b having the shape shown in FIGS. 7 and 8 is formed.

(3) Next, as shown in FIGS. 9 and 10, a resist 15 is formed by the photolithography technique so as to define the channel length of the floating gate. Then, using the resist 15 as a mask, the polysilicon layer 7 is formed.
b, the oxide film 6a, the nitride film 5a, the oxide film 4a, and the polysilicon layer 3a are anisotropically etched, and then the resist 15 is removed. As a result, the floating gate 7, the oxide film 6, the nitride film 5, and the oxide film 4 as shown in FIGS.
And the control gate 3 is formed.

(4) Next, as shown in FIGS. 14 to 16, an oxide film (see the dotted line in FIG. 16) is formed on the entire surface with a thickness of about 350 nm, and then the entire surface is anisotropically etched. The sidewall oxide film 8 is formed.

(5) Next, as shown in FIGS. 17 and 18, the oxide film 9 constituting the gate insulating film of the memory cell is formed on the floating gate 7, the sidewall oxide film 8 and the oxide film 6 to a thickness of about 10 nm. Form with thickness. Instead of the oxide film 9, a nitride film or a film having a two-layer structure of an oxide film and a nitride film may be used.

After that, a p-type polysilicon layer 10d having a thickness of about 100 nm is formed on the oxide film 9. A resist 16 is formed by photolithography so as to form a thin film transistor (TFT) portion on the polysilicon layer 10d. After the polysilicon layer 10d is anisotropically etched using the resist 16 as a mask, the resist 16 is removed. As a result, the polysilicon layer 10 for forming the thin film transistor as shown in FIGS.
e is formed.

(6) Next, as shown in FIGS. 21 and 22, a resist 17 having the same shape as the resist 15 formed in the steps described in FIGS. 9 and 10 is formed on the polysilicon layer 10e. The resist 17 can be easily formed by exposing using the same mask as that used for forming the resist 15 shown in FIGS. 9 and 10.

Using the resist 17 thus formed as a mask, arsenic or phosphorus is ion-implanted into the polysilicon layer 10e, and then the resist 17 is removed. As a result, the n-type drain diffusion layer 10a and the source diffusion layer 10b as shown in FIGS. 23 and 24 are formed.

(7) Next, as shown in FIGS. 25 and 26, a flattening process is performed to reduce the stepped portion of the TFT portion. That is, after depositing the protective film 11 having a thickness of 500 nm or more on the entire surface, heat treatment is performed to flatten the surface. Then, the flattened surface is etched back until the channel region 10c is exposed.

Thereafter, the oxide film 12 is formed to a thickness of about 20 nm.
To form. An n-type polysilicon layer 13 is formed on the oxide film 12.
a is formed with a thickness of about 300 nm.

Next, a resist 18 is formed on the polysilicon layer 13a by photolithography so that the end of the control gate 3 is located at the center of the control gate 3. The length of the resist 18 in the channel length direction needs to reach at least the end of the drain diffusion layer 10a. There is no problem if it becomes longer than that. Specifically, the gate length is 0.
In the 5 μm level memory cell, the resist 18 for forming the top gate 13 is also formed to have a length of 0.5 μm in the channel length direction.

By anisotropically etching the polysilicon layer 13a using such a resist 18, the top gate 13 as shown in FIG. 27 can be formed. After that, the resist 19 is removed.

(8) Although not shown, normally,
After the steps described above, a protective film having a thickness of 1000 nm or more is deposited on the entire surface, and the surface thereof is planarized by heat treatment. Then, after forming contact holes reaching the control gate 3, the top gate 13, the drain diffusion layer 10a and the source diffusion layer 10b, wiring is performed. As a result, the non-volatile memory of this embodiment is completed.

[0054]

According to the first aspect of the invention, the charge storage electrode is formed on the control electrode, and the thin film transistor is formed on the charge storage electrode, so that the film thickness is about the same as the channel depth. The thin film transistor can be used as a memory cell transistor. As a result, it is possible to effectively prevent the punch-through phenomenon that occurs when the memory cell transistor is formed on the semiconductor substrate.

According to the invention of claim 2, in addition to the effect of the invention of claim 1 described above, the following effect is further exhibited. That is, by further providing an auxiliary gate electrode on the thin film transistor, it is effective to form a current path in the thin film transistor during the erase operation by applying a negative voltage to the auxiliary gate electrode during the erase operation. To be prevented. Accordingly, a higher voltage can be applied to the source region of the thin film transistor without causing a malfunction during the erase operation. As a result, the erase efficiency can be improved without causing a malfunction during the erase operation, and the speed of the circuit can be increased by shortening the erase time.

[Brief description of drawings]

FIG. 1 is a plan view showing a nonvolatile memory according to an exemplary embodiment of the present invention.

2 is a cross-sectional view taken along the line AA of the nonvolatile memory shown in FIG.

FIG. 3 is a plan view for explaining the first step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

FIG. 4 is a cross-sectional view taken along the line AA of the nonvolatile memory in the first step of the manufacturing process shown in FIG.

5 is a plan view for explaining the second step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2. FIG.

FIG. 6 is a cross-sectional view taken along line BB of the nonvolatile memory in the second step of the manufacturing process shown in FIG.

FIG. 7 is a plan view for explaining a third step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

8 is a cross-sectional view taken along the line BB of the nonvolatile memory in the third step of the manufacturing process shown in FIG.

9 is a plan view for explaining a fourth step of the manufacturing process of the nonvolatile memory according to the embodiment shown in FIGS. 1 and 2. FIG.

FIG. 10 is a cross-sectional view taken along the line AA of the nonvolatile memory in the fourth step of the manufacturing process shown in FIG.

FIG. 11 is a plan view for explaining the fifth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

FIG. 12 is a perspective view for explaining a fifth step of the manufacturing process of the nonvolatile memory according to the embodiment shown in FIGS. 1 and 2.

FIG. 13 is a cross-sectional view taken along the line AA of the nonvolatile memory in the fifth step of the manufacturing process shown in FIGS. 11 and 12.

FIG. 14 is a plan view for explaining the sixth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

FIG. 15 is a perspective view for explaining the sixth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

16 is a cross-sectional view taken along the line AA of the nonvolatile memory in the sixth step of the manufacturing process shown in FIGS. 14 and 15. FIG.

FIG. 17 is a plan view for explaining the seventh step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

FIG. 18 is a cross-sectional view of the nonvolatile memory taken along the line BB in the seventh step of the manufacturing process shown in FIG. 17.

FIG. 19 is a plan view for explaining the eighth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

20 is a cross-sectional view taken along the line BB of the nonvolatile memory in the eighth step of the manufacturing process shown in FIG.

FIG. 21 is a plan view for explaining the ninth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2.

22 is a cross-sectional view taken along the line AA of the nonvolatile memory in the ninth step of the manufacturing process shown in FIG.

23 is a perspective view for explaining the tenth step of the manufacturing process of the nonvolatile memory of the embodiment shown in FIGS. 1 and 2. FIG.

24 is a cross-sectional view taken along the line AA of the nonvolatile memory in the tenth step of the manufacturing process shown in FIG.

FIG. 25 is a plan view for explaining the eleventh step of the manufacturing process of the nonvolatile memory according to the embodiment shown in FIGS. 1 and 2.

26 is a cross-sectional view taken along the line AA of the nonvolatile memory in the eleventh step of the manufacturing process shown in FIG.

27 is a cross-sectional view for explaining the twelfth step of the manufacturing process of the nonvolatile memory according to the embodiment shown in FIGS. 1 and 2. FIG.

FIG. 28 is a cross-sectional view showing a conventional nonvolatile memory.

FIG. 29 is a characteristic diagram for explaining a writing characteristic (writing time) of the conventional nonvolatile memory.

FIG. 30 is a characteristic diagram for explaining erasing characteristics (erasing time) of a conventional nonvolatile memory.

FIG. 31 is a cross-sectional view for explaining states of a depletion layer when the source potential applied in the erase operation of the conventional nonvolatile memory is high and low.

FIG. 32 is a cross-sectional view for explaining states of a depletion layer during an erase operation when the thickness of the inter-gate-substrate insulating film is thick and when it is thin.

FIG. 33 is a cross-sectional view illustrating a punch through phenomenon of a conventional nonvolatile memory.

[Explanation of symbols]

 1: semiconductor substrate 3: control gate 7: floating gate 10: thin film transistor (TFT) 10a: drain diffusion layer 10b: source diffusion layer 13: top gate In the drawings, the same reference numerals indicate the same or corresponding portions.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/786 9056-4M H01L 29/78 311 J

Claims (2)

[Claims] 1. A semiconductor substrate having a main surface, a control electrode formed in a predetermined region on the main surface of the semiconductor substrate via a first insulating film, and a second insulating film on the control electrode. A semiconductor device comprising: a charge storage electrode formed via the charge storage electrode; and a thin film transistor formed on the charge storage electrode via a third insulating film. 2. A semiconductor substrate having a main surface, a control electrode formed in a predetermined region on the main surface of the semiconductor substrate via a first insulating film, and a second insulating film on the control electrode. A semiconductor device, comprising: a charge storage electrode formed via the charge storage electrode; a thin film transistor formed on the charge storage electrode via a third insulating film; and an auxiliary gate electrode formed on the thin film transistor.