JP2797466B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of electrically writing and rewriting data optimally for floating gate electrical batch erasing.

<Prior Art> FIG. 3 is a longitudinal sectional view of a conventional electrically bulk erase type nonvolatile semiconductor memory device. The structure and operation of this nonvolatile semiconductor memory device will be described with reference to FIG.

For example, a memory cell (memory transistor) region that is electrically insulated from a region adjacent to the region by the field insulating film 3 is formed on the surface of the P-type silicon substrate 1.

In this memory cell area, the silicon substrate 1
N-type drain region 7a and source region separated from each other
7c are formed, and the drain region 7a and the source region 7c are formed.
The channel region of the memory cell is
7b is formed.

On the channel region 7b, a floating gate 5 is provided via a first gate insulating film 6, and on the floating gate 5, a gate electrode 9 is provided via a second gate insulating film 8, respectively. Have been.

The drain 7a, the control gate 9,
An extraction electrode (wiring) 11 from each electrode of the source 7c
a, 11b, and 11c have been taken out.

Here, the surface portion of the source region 7c in the first gate insulating film 6 is the tunnel injection region 4,
This is a structure in which a tunnel current flows between the floating gate 5 and the floating gate 5 due to the high voltage applied to 7c.

In such a conventional nonvolatile semiconductor memory device, writing is performed by applying a high voltage to the drain region 7a and the gate electrode 9, applying a ground potential to the source region 7c, and turning on the channel region 7b. Let it. As a result, although a current flows through the channel region 7b, the current causes the drain region 7b.
Hot electrons are generated near 7a, and some of the hot electrons are injected into the floating gate 5. Since electrons jump into the floating gate 5, a negative potential is always applied to the channel region 7b, so that the threshold voltage of the channel region 7b increases in the positive direction, and stored data is stored by the increase in the threshold value.

On the other hand, in erasing, a positive high voltage is applied to the source region 7c, and a ground potential is applied to the gate electrode 9 and the drain region 7a. As a result, the floating gate 5 and the tunnel injection region
, A tunnel current flows through the source region 7c, and as a result, electrons stored in the floating gate 5 are extracted. Therefore, the threshold voltage of the channel region 7b drops to the initial value.

In the drawing, 7d indicates a high breakdown voltage source region, and 10 indicates an interlayer insulating film.

<Problems to be Solved by the Invention> However, the above-described conventional nonvolatile semiconductor memory device has the following problems.

First, since a high voltage is applied when a tunnel current flows between the source of the memory transistor and the floating gate, the source must have a structure that can withstand the high voltage (hereinafter, high breakdown voltage). Conventionally, the source is formed as an impurity diffusion region on the surface of the silicon substrate, but in order to form a source with a high breakdown voltage, the impurity diffusion region must be formed deeply. However, when the impurity diffusion region is formed deep, the diffusion of the impurity into the channel region also increases, and the effect of shortening the channel length becomes significant. Therefore, reduction in the length of the memory transistor in the channel direction is limited.

A second disadvantage is that the first gate insulating film and the tunnel injection region are on the same plane.

Normally, in the tunnel injection region, a tunnel current flows through a thin silicon oxide film (tunnel oxide film) of 100 ° or less. In order to dispose the first gate insulating film and the tunnel implantation region on the same plane, the first gate insulating film and the tunnel oxide film are formed of the same film, or the first gate insulating film is Either a tunnel injection region is formed by adding a process to a part thereof.

However, in the former case, the first gate insulating film is
If it is less than {}, hot electrons will pass through the first gate insulating film of less than 100 ° during the write operation of the memory transistor. As a result, the quality of the first gate insulating film is greatly deteriorated due to a defect level generated by the passage of hot electrons, which immediately leads to the deterioration of the characteristics of the memory transistor.

On the other hand, the latter is disadvantageous in planar reduction because it is unavoidable to add a step including one-time mask alignment, and it is necessary to consider a manufacturing margin accompanying the mask alignment.

<Differences from Conventional Technology of the Invention> In contrast to the above-described conventional nonvolatile semiconductor memory device, in the nonvolatile semiconductor device according to the present invention, a first insulating film and a second insulating film are laminated. Formed in another layer,
Another difference is that the channel of the memory transistor is not formed in the silicon substrate but is formed in the silicon thin film on the insulating film.

<Means for Solving the Problems> In a nonvolatile semiconductor memory device according to the present invention, a conductive layer serving as a gate electrode of a memory transistor is provided on a semiconductor substrate, and a memory transistor is provided on the conductive layer via a first insulating film. A source region and a drain region are provided adjacent to the channel region, a floating gate electrode is provided on the channel region via a second insulating film, and a third gate region is provided on the floating gate electrode. An erase gate electrode is provided via a tunnel insulating film.

<Example> Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

In FIG. 1, a P-type silicon substrate 1 has a conductive layer 2 formed of an N-type impurity diffusion layer in a predetermined region on the surface thereof. That is, the conductive layer 2 is formed in a region surrounded by the field insulating film 3 on the surface of the silicon substrate 1.

Above the conductive layer 2, a silicon thin film is applied via a first gate insulating film 6. In this silicon thin film,
A channel 7b of the memory transistor is provided. The drain 7a and the source 7c of the memory transistor are formed adjacent to both sides of the channel 7b.

Here, the conductive layer 2 has a role as a gate electrode of the memory transistor.

On this memory transistor, a floating gate 5 is provided via a second gate insulating film 8. An erase gate 13 is provided on the floating gate 5 via a third insulating film (tunnel insulating film) 12.

Although not shown in the figure, a conductive layer (gate electrode)
2, the drain 7a, the source 7b, and the erase gate 13
The electrodes are insulated from each other by an interlayer film, and each is provided with an extraction electrode.

Next, write and erase operations of the nonvolatile semiconductor memory device of the present embodiment will be described.

Writing is performed by applying a positive high voltage to the conductive layer 2 and the drain 7a which are gate electrodes of the memory transistor.

As a result, the channel 7b is turned on, a current flows between the source 7c and the drain 7a of the memory transistor, and hot electrons are generated in the channel 7b.

Some of the hot electrons are injected into the conductive layer 2 and the floating gate 5, and the electrons injected into the floating gate 5 fix the potential of the floating gate 5 to negative.

A negative potential is applied to the channel 7b from the upper surface by the floating gate 5, and this negative potential shifts the channel threshold voltage of the memory transistor in the positive direction. As a result, stored data is stored.

On the other hand, erasing is performed by applying a high voltage to the erasing gate 13 and applying a ground potential to the drain 7a, the source 7c, and the conductive layer 2.

As a result, a tunnel current flows between the erase gate 13 and the floating gate 5, and as a result, the electrons accumulated in the floating gate 5 are extracted to the erase gate 13 side. As a result, the threshold voltage of the channel 7b drops to the initial value.

FIG. 2 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

In this embodiment, the device isolation of the memory transistor is performed by the trench-buried oxide film 14.

In this case, a conductive layer 2, a first gate oxide film 6, a silicon thin film, a second gate oxide film 8, a floating gate 5, a tunnel insulating film 12, and an erase gate 13 are formed on the silicon substrate 1. They are stacked in order.

After laminating them in this manner, a groove for element isolation is formed in the silicon substrate 1 by etching, and the groove is filled with the oxide film 14, whereby a memory cell can be manufactured.

The drain 7a, channel 7b, and source 7c of the memory transistor are formed on the silicon thin film.

Since the element isolation step is performed after the formation of the memory cell, the memory cell region and the element isolation region are formed in a self-aligned manner, which is extremely effective in reducing the size of the memory cell.

Further, there is an advantage that the number of times of photolithography can be greatly reduced.

<Effect of the Invention> As described above, the present invention is an electrically erasable rewritable nonvolatile semiconductor memory device,
By forming the injection region of hot electrons into the floating gate at the time of writing and the tunnel injection region at the time of erasing with different layers in the laminated structure, it is possible to reduce the fineness without deteriorating the gate insulating film at the time of writing. There is an effect that a memory transistor having a simple structure can be obtained.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 1 is a longitudinal sectional view of a conventional nonvolatile semiconductor memory device. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... First conductive layer, 3 ... Field insulating film, 4 ... Tunnel injection region, 5 ... Floating gate, 6 ... First gate insulating film, 7a ... Drain region 7b ... channel region, 7c ... source region, 8 ... second gate insulating film, 9 ... gate electrode, 10 ... interlayer insulating film, 11a ... drain extraction electrode, 11b ... gate extraction electrode, 11c: Source extraction electrode, 12: Tunnel insulating film, 13: Erase gate.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 29/788 H01L 29/792 H01L 27/115 H01L 21/8247

Claims (1)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, a conductive layer of an opposite conductivity type provided on the semiconductor substrate, and a first conductive layer on the conductive layer.
A semiconductor thin film laminated via the insulating film, a channel region of one conductivity type provided on the semiconductor thin film and disposed on the conductive layer, and provided on the semiconductor thin film so as to sandwich the channel region. Source and drain regions of opposite conductivity type, a floating gate laminated on the channel region via a second insulating film, and a floating gate laminated on the floating gate via a third insulating film. And an electrode for extracting the electric charge accumulated in the third insulating film as a tunnel current into the third insulating film.