JPH065875A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To provide a nonvolatile memory having a tunnel insulator consisting of a silicon nitride film and a silicon oxide film to decrease the erase voltage and decrease the film thickness on the side for read operation. CONSTITUTION:A nonvolatile memory comprises a field-effect transistor having a laminated structure on a p-type semiconductor substrate 10. The laminated structure includes a tunnel insulator formed of a silicon nitride film 12a and a silicon oxide film 12b, a floating gate electrode 14, an inner insulating film 16, and a control gate 18. The tunnel insulator for write operation, i.e., the silicon oxide, can be made sufficiently thin for effective injection of electrons. On the other hand, the tunnel insulator for erase operation, i.e., the silicon nitride, enables the extraction of electrons at lower voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device.

[0002]

2. Description of the Related Art Conventionally, an extremely thin oxide film has been used in a semiconductor integrated circuit, particularly in a silicon integrated circuit. In particular, in a non-volatile memory with a design rule of 1.0 nm or less (flash memory of 1 Mbit or more), a silicon oxide film (Si having a film thickness of 100 A ° or less
O ₂ ) is used as the tunnel oxide film.

In the flash memory having the thin oxide film as described above, the tunnel oxide film is damaged by rewriting, which eventually causes dielectric breakdown and limits the number of times data is rewritten. For this reason, the characteristics of the tunnel oxide film are extremely important factors in determining the operation of the flash memory, particularly the number of rewrites and the data storage retention time.

For a conventional non-volatile memory device, refer to Document I (Monthly, Semiconductor Director World).
d, 1991, April issue, p94-98). 7A and 7B are structural views for explaining a conventional nonvolatile memory device.

[0005] In the structure of (A) in FIG. 7, and the n ⁺ conductivity type source region 20 and the n ⁺ conductivity type drain region 22 is formed in a surface portion of the p-type semiconductor substrate 10. Further, a low-concentration n ⁻ layer 24 is provided below the source region for suppressing band-to-band tunnel leak, while below the drain region 22 to improve writing efficiency, This is an example in which the p ⁺ layer 26 is provided.

Further, on the p-type semiconductor substrate 10, the tunnel oxide film 12, the floating gate electrode 14, and the insulating film 16 are provided in the range between the source region 20 and the drain region 22.
And a structure in which the control gate 18 is stacked.

Next, FIG. 7B is an example in which the surface of the p-type semiconductor substrate is not provided with the n ⁻ layer 24 and the p ⁺ layer 26. Otherwise, the configuration is similar to that of FIG. That is, the tunnel oxide film 12, the floating gate electrode 14, the insulating film 16 and the control gate 18 are formed on the substrate.

Next, an operating method of the conventional non-volatile memory device will be described by taking the structure of FIG. 7A as an example.

First, in reading information, when a large number of electrons are injected into the floating gate electrode 14, electrons do not flow into the channel region because the channel is not inverted. Therefore, no current flows between the source / drain regions. That is, it is turned off.

On the other hand, when electrons are not injected into the floating gate electrode 14, the channel can be easily inverted and a current can flow between the source / drain regions. That is, it is turned on.

As described above, the nonvolatile memory device is turned on or off depending on the amount of electrons injected into the floating gate.
The operation of F is repeated.

Next, injection (writing) of electrons from the drain region 22 to the floating gate electrode 14 and extraction (erasing) of electrons from the floating gate electrode 14 to the source region 20 will be described.

First, injection of electrons from the drain region 22 to the floating gate electrode 14 is carried out in the drain region 22 by the substrate 10.
A reverse bias positive voltage (about 5V) is applied to the control gate so that the potential of the floating gate becomes about 10V. At this time, the electrons flowing out of the source region 20 are accelerated from the source region potential to the drain region potential, and some of them are injected into the floating gate electrode 14.

Next, when electrons are extracted from the floating gate electrode 14, by applying a positive high voltage to the source region 20, a tunnel current flows through the tunnel oxide film 12 to the source region 20 side, and electrons in the floating gate are removed. It is extracted into the source region 20.

As described above, writing and erasing of information in the flash memory is performed through the tunnel oxide film.

[0016]

However, in the conventional non-volatile memory device described with reference to FIGS. 2A and 2B, since the writing and erasing of information are repeatedly performed, the stress applied to the tunnel oxide film is also increased. It increases in proportion to the number of times information is rewritten.

Further, this stress has a correlation between the film thickness and the data retention period. For example, as the stress increases, the data retention characteristic deteriorates.

The deterioration of the operating characteristics is manifested in the dielectric breakdown of the tunnel oxide film and the increase of leak current. In addition, the deterioration of the tunnel oxide film is caused by the floating gate
Occurs remarkably when electrons are extracted into the gate region, and the dielectric breakdown decreases as the tunnel oxide film becomes thinner.
It appears as an increase in leak current.

On the other hand, if the thickness of the tunnel oxide film is increased, the electric field applied to the tunnel oxide film can be reduced.
In addition, the number of rewrites can be increased and the data retention period can be lengthened.

However, as described above, the tunnel current is used when the device is operated, especially in the erase operation. Therefore, if the tunnel oxide film is made thick, this tunnel current cannot be generated unless a high voltage is applied between the source and the floating gate at the time of erasing. Therefore, there is a problem in that it is necessary to form a booster circuit having a large area in the semiconductor circuit. Further, there is a limit to the thinning of the tunnel oxide film, and the limit value is generally expected to be 80 to 90 A °.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to form a tunnel oxide film which lowers the voltage applied between the source floating gates at the time of erasing. Another object of the present invention is to provide a semiconductor non-volatile memory in which a tunnel oxide film is formed so that the reliability of the tunnel oxide film is improved during writing and erasing.

[0022]

In order to achieve this object, according to the present invention, a semiconductor substrate of a first conductivity type,
A second conductive type first and second impurity region provided on the semiconductor substrate and spaced apart from each other, and formed on the semiconductor substrate between the first and second impurity regions of the semiconductor substrate. A first insulating film, a first conductive layer provided on the first insulating film, a second insulating film provided on the first conductive layer, and a second insulating film provided on the second insulating film. In the nonvolatile memory device having a second conductive layer, the first insulating film is composed of a silicon nitride film on the first impurity region side and a silicon oxide film on the second impurity region side. It is characterized by being.

[0023]

According to the structure of the present invention, the first insulating film (this insulating film is referred to as a tunnel insulating film) has the silicon oxide film (SiO ₂ film) and the silicon nitride film (Si ₃ film) arranged side by side.
And it includes the N ₄ film) and. Then, when erasing information, electrons are extracted from the first conductor layer (floating gate) to the second impurity region (source region) through the silicon nitride film. The electric field strength required for this purpose is determined by the silicon oxide film (Si
It can be made lower than in the case of O ₂ film). Further, at the time of erasing information, the silicon nitride film has a larger leak current than the silicon oxide film, so that electrons can be easily extracted to the source region side.

On the other hand, when writing information, electrons are injected from the second impurity region (drain region) into the first conductor layer (floating gate) through the silicon oxide film. Therefore, the dielectric breakdown charge can be increased even if the silicon oxide film is thinner than the silicon nitride film.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. The nonvolatile memory device of the present invention will be described here. However, in these FIGS. 1 to 4, the shape of each component,
Only the size and the layout relationship are shown schematically. Further, in these drawings, the same components as those of the conventional one are denoted by the same reference numerals, and in the following description, the description thereof will be partially omitted.

FIG. 1 is a sectional view showing the structure of the main part of a non-volatile memory device used for explaining the present invention.

In this non-volatile memory device, a semiconductor substrate 10 of the first conductivity type, for example, a p conductivity type and a specific resistance of 5Ω.
cm, plane orientation (100) on a silicon substrate (hereinafter referred to as p-conductivity type semiconductor substrate), first insulating films 12a and 12
b (hereinafter, 12a is referred to as a silicon nitride film and 12b is referred to as a silicon oxide film, and a combination of the silicon nitride film and the silicon oxide film is referred to as a tunnel insulating film), and a first conductor layer 14 (hereinafter, referred to as floating). A gate electrode), a second insulating film 16 (hereinafter referred to as an interlayer insulating film), and a second conductor layer 18 (hereinafter referred to as a control gate electrode) are sequentially stacked.

The p-conductivity type semiconductor substrate has first and second impurity regions 20 and 22. here,
The second conductivity type impurity region 20 may be referred to as a source region, and the other second conductivity type impurity regions 22 may be referred to as a drain region. Furthermore, an n ^- layer 24 is provided below the source region 20, while a p ^- layer 26 is provided below the drain region 24. In the present invention, the tunnel insulating film 12 is formed into the second conductivity type first and second impurity regions 20 and 22.
The structure is provided on the substrate 10 over the space. Then, in this embodiment, a silicon nitride film is provided on the first impurity region 20 side, and a silicon oxide film is formed on the second impurity region 22.
It is in the state where it is located on the side and both 12a and 12b are juxtaposed in a plane.

Next, the manufacturing process of the present invention will be described with reference to FIGS.

P conductive type semiconductor substrate 10 ((A) of FIG. 2)
Above, in an atmosphere of ammonia (NH ₃ ) gas, 120
A thermal nitriding treatment is performed at 0 ° C. for 100 minutes to form a first preliminary layer 11 of a silicon nitride film (Si ₃ N ₄ film) having a film thickness of 50 A ° (angstrom) ((B) of FIG. 2). afterwards,
A resist material is applied on the first preliminary layer 11 of the silicon nitride film to form a resist layer ((C) of FIG. 2).

Next, using a well-known hot etching technique, the resist layer 13 is patterned with the first preliminary layer 11 of the silicon nitride film left, to form a resist pattern 13a ((in FIG. 2). D)).

Next, using the resist pattern 13a as a mask, the exposed portion of the first preliminary layer 11 of the silicon nitride film is removed to form the second preliminary layer 11a of the silicon nitride film, and a part of the surface of the substrate 10 is removed. It is exposed ((A) of FIG. 3).

After that, the resist pattern 13a is removed, and the patterned second preliminary layer 1 of the silicon nitride film is formed.
1a is exposed (not shown).

Next, the structure formed on the substrate 10 is heat-treated and oxidized in an oxidizing gas atmosphere. The oxidizing gas at this time is preferably formed, for example, with a flow rate ratio of oxygen (O ₂ ) gas and nitrogen (N ₂ ) gas of 1: 1. The heat treatment conditions at this time are 1000 ° C. and 1
5 minutes. In addition, in the oxidation process at this time, the second preliminary layer 11a is hardly oxidized, but only the exposed portion of the substrate 10 is oxidized to form the first silicon oxide film (SiO ₂ film) having a thickness of about 50 A °. The preliminary layer 11b is the second preliminary layer 11a.
Are formed side by side (FIG. 3B).

The thermal oxidation process is preferably controlled so that the film thickness at this time is substantially the same as that of the second preliminary layer 11a.

After that, the substrate 10 is quickly transferred to a silicon thin film forming apparatus, and a large number of layers are formed on the second preliminary layer 11a of the silicon nitride film and the first preliminary layer 11b of the silicon oxide film by using, for example, a normal CVD technique. Crystalline silicon thin film layer 14
To form. Subsequently, phosphorus (P) is diffused in the polycrystalline silicon thin film layer 14 to form a preliminary electrode layer 14a for forming an n ⁺ conductivity type floating gate electrode (FIG. 3C).

Next, a film thickness of 35n is formed on the preliminary electrode layer 14a.
A preliminary insulating layer 16a for the second insulating film having a thickness of about m is formed by a high temperature oxidation method, and then the preliminary electrode layer 1 is formed on the insulating film.
The preliminary gate electrode layer 18a for forming the control gate electrode is formed by using the same method as that for forming 4a (FIG. 3D).

Then, a preliminary insulating film for a mask is formed on the preliminary gate electrode layer 18a, and patterning is performed so that the preliminary insulating film corresponding to a portion to be an electrode remains, and a mask 19 is formed. Utilizing the hot etching technique and the dry etching technique, etching is performed until the surface of the substrate 10 is reached to obtain a structure as shown in FIG. The layers remaining after this etching are the silicon nitride film 12a and the silicon oxide film 12 respectively.
b, the floating gate electrode 14, the second insulating film 16, and the control gate electrode 18. The two films 12a and 12b form the tunnel insulating film 12. Both films 12a,
When viewed from above the substrate, 12b is in a state of being provided side by side adjacently on the substrate 10 (FIG. 4A).

Next, the silicon nitride film 12a and the silicon oxide film 12b, the floating gate electrode 14, the interlayer insulating film 16,
The periphery of the control gate electrode 18 is masked (not shown) with, for example, a resist material, and then ion implantation and activation are performed to form a source region 20 and a drain region 22 of the n ⁺ conductive layer on the substrate 10. To form. In order to improve the implantation efficiency, for example, boron (B) ions are implanted to form the p ⁻ layer 24 under the source region 20, and further, for example, arsenic (As) ions are implanted to form the drain region. An n ⁻ layer 26 is formed underneath (FIG. 4B).

The main part of the non-volatile memory device is formed through the manufacturing process as described above.

In the present invention, the ratio of the lengths m and n of the silicon nitride film forming the first insulating film and the silicon oxide film is 50:50, but a slight silicon nitride film is formed on the source region 20 side. If formed, the function of the element can be sufficiently fulfilled. This is because the electrons that escape from the floating gate electrode 14 to the source region 20 when erasing information are performed in only a small part of the tunnel insulating film.

Next, the voltage-current characteristics of the silicon nitride film and the silicon oxide film will be described. FIG. 5 is a curve showing the characteristics of the silicon nitride film and the silicon oxide film with the electric field strength (unit of MV / cm) on the horizontal axis and the leakage current density (unit of A / cm ² ) on the vertical axis. . Where curve I
Represents a silicon nitride film, and curve II represents a silicon oxide film. However, the curve I and the curve II are values when the film thickness is 4.5 nm. As can be understood from this figure, when the leak current density is 10 ⁻⁶ A / cm ² , the electric field strength of the silicon oxide film is about 8 MV / cm, whereas the silicon nitride film decreases to about 4 MV / cm. Therefore, by providing the nitride film on the side of the source region where the erasing operation is performed, erasing can be performed at a lower voltage than before. Therefore, in the present invention, since the silicon nitride film is used on the source side, a current flows by pool Frenkel conduction, and the same current can be extracted under a lower voltage than that of the silicon oxide film. Further, since the silicon nitride film has a large leak current density induced by a high electric field as compared with the silicon oxide film, it is easy to extract electrons, and as a result, long-term reliability can be secured.

Next, the dielectric breakdown charge characteristics of the tunnel insulating film will be described.

In FIG. 6, the horizontal axis indicates the thickness of the tunnel insulating film (A
° Unit: A ° is a symbol representing Ongstrom,
The dielectric breakdown charge Q _BD (unit: C / cm ² ) is plotted on the vertical axis,
It is a figure showing the characteristic of gate positive polarity and gate negative polarity by dependence on film thickness. Here, curve I represents the gate positive electrode characteristic of the silicon oxide film, curve II represents the negative electrode characteristic of the silicon oxide film, III represents the gate positive electrode characteristic of the silicon nitride film, and IV represents the negative electrode of the silicon nitride film. . However,
The injection current density is ± 100 A / cm ² .

As can be understood from this figure, when the gate positive electrode is applied, that is, in the write operation,
The dielectric breakdown charge characteristics of the silicon oxide film increase as the film thickness decreases. On the other hand, when the gate negative electrode is applied, that is, during the erase operation, the dielectric breakdown charge characteristic of the silicon oxide film is extremely reduced when the film thickness is reduced.

On the other hand, looking at the film thickness dependence of the silicon nitride film, the film thickness is 60 A °, and the dielectric breakdown charges for the positive electrode and the negative electrode are 40 to 30 A °.

From this fact, when a silicon oxide film is used on the write side, that is, when a positive potential is applied to the drain region side, even if the tunnel oxide film is thinned, it will be compared to a silicon nitride film. , The breakdown charge value increases. Therefore, the life characteristics of the tunnel oxide film can be extended.

On the other hand, when a silicon nitride film is used on the side to be erased, that is, when the potential of the negative electrode is applied to the source region, the dielectric breakdown field value is 30 C / cm ^{2 due to} the negative polarity of the tunnel oxide film thickness of 60 A °. , Silicon oxide film 7C / c
The difference is 23 C / cm ² compared to m ² . From this result, if the silicon nitride film is used for erasing information, even if the thickness of the tunnel oxide film is thinned, there is almost no effect on the reduction of the dielectric breakdown charge, and the erasing operation is stabilized.

[0049]

As is apparent from the above description, according to the non-volatile memory device of the present invention, since the silicon oxide film is used as a part of the tunnel insulating film, the floating from the drain region occurs when writing information. The dielectric breakdown charge due to the thinning when electrons are injected into the gate can be increased as compared with the case of the silicon nitride film. Therefore, it is possible to improve the long-term reliability of information.

On the other hand, according to the structure of the present invention, since the silicon nitride film is used as a part of the tunnel insulating film, the electric field strength is higher than that of the silicon oxide film when electrons are extracted from the floating gate to the source region at the time of erasing information. Can be lowered.
Therefore, when a negative potential is applied to the source region during the erase operation to extract electrons from the floating gate to the source region, the erase operation can be performed at a low voltage.

Therefore, by using the non-volatile memory device of the present invention, it is possible to lower the voltage for writing and erasing data and to improve the reliability of the information reading characteristic. In addition, the data retention time can be extended.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a nonvolatile memory device according to an embodiment.

FIG. 2 is a diagram which is used for describing a manufacturing process of the present invention.

FIG. 3 is a diagram for explaining the manufacturing process of the present invention following FIG. 2;

FIG. 4 is a diagram for explaining the manufacturing process of the present invention following FIG.

FIG. 5 is a diagram showing current-voltage characteristics according to the type of tunnel insulating film used in the present invention.

FIG. 6 is a diagram showing dielectric breakdown charge characteristics of the tunnel insulating film used in the present invention.

FIG. 7 is a cross-sectional view of a conventional nonvolatile memory device.

[Explanation of symbols]

10: p conductive type semiconductor substrate 12: first insulating film (tunnel insulating film) 12a, 12b: silicon nitride film and silicon oxide film (Si ₃ N ₄ film and SiO ₂ film) 14: floating gate electrode 16: interlayer insulation film 18: a control gate electrode 20: source region 22: a drain region 24: n ^- layer 26: p ^- layer

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G11C 16/02 16/04 H01L 27/115 29/62 G 9055-4M 8728-4M H01L 27/10 434

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, first and second impurity regions of a second conductivity type which are provided in the semiconductor substrate and are separated from each other, and the first and second semiconductor substrates of the semiconductor substrate. A first insulating film formed on the semiconductor substrate, a first conductor layer provided on the first insulating film, and a first conductor layer provided on the first conductor layer across the two impurity regions. In a non-volatile memory device having a second insulating film and a second conductor layer provided on the second insulating film, the first insulating film may be a silicon nitride film on the first impurity region side and the second impurity film. A non-volatile memory device comprising a region-side silicon oxide film.