JPH11176954A - Non volatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a non-volatile semiconductor memory device which is improved in data holding characteristic. SOLUTION: A semiconductor memory device 10 is equipped with a memory device 18 and a protective diode 20. The memory device 18 has a tunnel oxide film 24, a floating gate 26, an insulating layer 28, and a control gate 30 which are sequentially laminated above a p-type well 14. The protective diode 20 is formed of an n-type semiconductor diffused layer 34 and a p-type well 14. The control gate 30 of the memory device 18 is formed crossing over the forming region of the protective diode 20 and brought into contact with an n-type semiconductor diffused layer 34. The protective diode 20 is actuated, when charge (process induced charge) is accumulated above the tunnel oxide film 24 to generate a prescribed potential difference, whereby the control gate 30 is electrically connected to a semiconductor substrate 12 to make the accumulated charge (process induced charge) flow to the semiconductor substrate 12, and the tunnel oxide film 24 is prevented from deteriorating in film quality.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a stacked nonvolatile semiconductor memory device in which a floating gate and a control gate are stacked, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, FAMOS (Floating) has been used as a writable and erasable nonvolatile semiconductor memory device.
gate Avalanche injection
MOS transistor). However, since FAMOS needs to be irradiated with ultraviolet light to erase the written contents, in recent years, it has been possible to electrically write and erase, and in addition to the fact that the writing voltage can be lowered and the writing speed is extremely high, , A stacked nonvolatile semiconductor memory device in which a floating gate and a control gate for controlling injection and emission of electrons to and from the floating gate are stacked
OS (Stacked gate Avalanche)
injection MOS transisto
r) has come to be widely adopted.

In a conventional method of manufacturing a stacked nonvolatile semiconductor memory device (stacked flash memory), first, boron ions are implanted into a surface layer of a p-type semiconductor substrate to form a p-type well made of a p-type semiconductor. Then, a surface oxide film (SiO 2) is formed on the surface of the p-type well by a CVD method or the like.
Silicon nitride film through a ₂ film) (silicon nitride film Si ₃ N
₄ ) and a resist film is formed. Thereafter, the silicon nitride film and the resist film in the element isolation region for isolating each element are removed by a photoetching method or the like, and boron ions are implanted to form a channel stopper in the element isolation region.

Next, after removing the resist film, a field oxide film for element isolation is formed in the element isolation region by selective oxidation using the silicon nitride film as a mask. Thereafter, after removing the silicon nitride film and the surface oxide film (SiO ₂ film), a tunnel oxide film made of silicon oxide (SiO ₂ ) is formed in the element formation region by a thermal oxidation method or the like, and an n-type polysilicon film is deposited. To form a floating gate. Thereafter, a control gate made of an n-type polysilicon film is formed via an insulating layer made of a so-called ONO film sandwiching the silicon nitride film in a sandwich manner between two silicon oxide films. Next, a floating gate and a control gate electrode are formed by a photoetching method. Further, after forming a resist film having openings in the source formation region and the drain formation region, ions such as phosphorus and arsenic are implanted to form a source region and a drain region made of an n-type semiconductor.

[0005]

However, the above-mentioned conventional manufacturing method involves etching at the time of formation of the floating and control gate electrodes, ion implantation into the source formation region and the drain formation region, and further, the connection hole in the subsequent steps. When plasma or ion beam is applied during plasma etching when forming holes or forming aluminum wiring, charges (Process-Induced Charge) are accumulated above the tunnel oxide film with small capacitance. . As a result, a potential difference is generated between the upper and lower semiconductor substrates of the tunnel oxide film, thereby deteriorating the film quality of the tunnel oxide film and making it easier for electrons to leak. Leakage through the film causes a problem that data retention characteristics of the nonvolatile semiconductor memory device deteriorate.

The problem of the deterioration of the data retention characteristics of such a nonvolatile semiconductor memory device is that when information is erased, the information is erased at once with ultraviolet rays and electrically rewritten, that is, a so-called EPROM (electrically program-mablle read). onl
y memory) or a so-called EEPROM (electrically erasable
Read only memory) also occurs.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to improve the retention characteristics of a nonvolatile semiconductor memory device.

[0008]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device having a memory element having a floating gate and a control gate. It is provided between a control gate and a semiconductor substrate, and operates by a potential difference between the control gate and the semiconductor substrate which is larger than any of a writing voltage, a reading voltage, and an erasing voltage applied to the control gate. It is characterized in that a protection switch unit for conducting is provided.

According to the present invention having the above-described structure, an ion beam is irradiated by etching or ion implantation into a source / drain formation region, and a charge (Process-Induced Char) is applied.
When the ge) is accumulated, the protection switch section is activated to conduct the control gate and the semiconductor substrate, so that the accumulated charge flows to the semiconductor substrate having a large capacity, and the potential difference generated in the tunnel oxide film can be reduced. . For this reason,
The deterioration of the quality of the tunnel oxide film is prevented, the leakage of electrons injected into the floating gate is prevented, and the data retention characteristics of the nonvolatile semiconductor memory device can be significantly improved, and the reliability can be improved. In addition, since the protection switch section is operated by a potential difference larger than any of the write voltage, the read voltage and the erase voltage applied to the control gate, it does not affect the write operation or the read operation at all. . Further, even if an unexpected unexpected voltage is applied to the control gate, voltage breakdown of the tunnel oxide film can be prevented, and the reliability of the nonvolatile semiconductor memory device can be improved.

If the protection switch is formed as a protection diode comprising a well formed on the semiconductor substrate and a diffusion layer, the protection switch having a predetermined operating voltage can be easily formed without requiring any special process. . And
If the diffusion layer is formed by diffusing the impurities in the control gate into the well, the diffusion layer can be formed during the annealing of the control gate, and the protection diode can be easily formed. Further, by forming the diffusion layer with a channel stopper interval, current can be prevented from flowing from the diffusion layer to the channel stopper, and a predetermined operating voltage of the protection diode can be reliably ensured.

Further, a plurality of storage elements can be formed, and a selection transistor for selecting an arbitrary storage element for performing a writing operation, reading, or erasing can be provided. By providing the selection transistor in this manner, excessive erasure of the storage element can be prevented, and punch-through due to miniaturization can be prevented, so that a highly reliable storage device can be obtained. By providing the second protection switch between the selection gate of the selection transistor and the semiconductor substrate, accumulation of electric charge (Process-Induced Charge) at the time of ion implantation or etching is prevented, Deterioration of the gate insulating film can be prevented.

The method for manufacturing a nonvolatile semiconductor memory device described above is a method for manufacturing a nonvolatile semiconductor memory device having a storage element having a floating gate and a control gate, wherein the first conductive type semiconductor substrate is provided on the first conductive type semiconductor substrate.
Forming a channel stopper and a field oxide film in the well of the conductivity type and the element isolation region; forming a tunnel oxide film on the well of the first conductivity type; and forming a first polycrystalline film on the tunnel oxide film. Depositing silicon and etching it into a predetermined shape to form a floating gate; forming an insulating layer on the floating gate; forming an insulating film in a formation region of the protection diode; Forming a contact hole in the insulating film by etching and providing a contact hole in the insulating film by etching, and depositing a second polycrystalline silicon to cover the insulating layer and the contact hole by etching. Forming a control gate by patterning into a shape of Heat treatment of the substrate, said first through said contact hole impurities in the control gate
Forming a second conductivity type diffusion layer by diffusing it into the conductivity type well.

When a selection transistor is provided, a gate insulating film of the selection transistor can be formed when the insulating film of the storage element is formed, and a selection gate of the selection transistor can be formed when the control gate is formed. . Further, the second between the select gate and the semiconductor substrate
When the protection switch section is provided, an insulating film is formed in a formation region of the second protection diode connected to the selection transistor when forming the gate insulation film, and a formation region of the second protection diode is formed when forming the contact hole. Preferably, a second contact hole is formed in the insulating film, a select gate is provided to cover the second contact hole, and impurities in the select gate are diffused into the first conductivity type well during heat treatment of the semiconductor substrate.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 1A and 1B are views showing the structure of a nonvolatile semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. Sectional view along
(C) is an equivalent circuit diagram. In FIG. 1, the semiconductor memory device 10 has a p-type well 14 formed on a p-type semiconductor substrate 12, for example, as a first conductivity type semiconductor substrate, as shown in FIG. Furthermore, p-type well 1
4, a plurality of element formation regions are defined by a field oxide film 16 formed in the element isolation region.
A memory element (memory cell) 18 and a protection diode 20 serving as a protection switch are formed in these element formation regions.

Each of the storage elements 18 is arranged in a matrix, and diffusion layers 21 and 22 of an n-type semiconductor (n ⁺ ) of a drain region and a source region are formed above a p-type well 14. As shown in FIG. 1A, a tunnel oxide film 24 made of a silicon oxide film (SiO ₂ ) is provided thereon. A floating gate 26 made of an n-type semiconductor (n-type polysilicon) is provided above the tunnel oxide film 24, and an insulating layer 2 made of an ONO film is provided thereon.
A control gate 30 made of an n-type semiconductor (n-type polysilicon) is provided with the control gate 8 interposed therebetween. Then, the contact 32 with the bit line 46 made of the aluminum wiring shown in FIG. 1C is formed in the diffusion layer 21.

The protection diode 20 is formed by a diffusion layer 34 formed of an n-type semiconductor serving as a cathode and formed on the p-type well 14 and a p-type well 14 serving as an anode. The control gate 30 forms a word line, extends beyond the region where the protection diode 20 is formed, and is provided above the p-type well 14.
It is in contact with a diffusion layer 34 made of a mold semiconductor via a contact hole 36.

As will be described later in detail, the diffusion layer 34 is formed by removing impurities in the control gate 30 from the p-type well 1.
4 is formed.

As shown in FIG. 1B, the diffusion layer 34 is formed at a predetermined gap g from a channel stopper 38 provided below the field oxide film 16.
A predetermined operating voltage of the protection diode 20 can be reliably obtained. In the case of this embodiment, the gap g is about 0.3 to 0.8 μm,
4 and the channel stopper 38, a write voltage (10 to 13V), a read voltage (1 to 6V) or an erase voltage (10 to 13V) applied to the control gate 30.
V), which is activated when a potential difference of 14 V or more is generated, and the control gate 30 and the semiconductor substrate 12 are electrically connected. And the protection diode 20
Are provided for each cell array (word line).

The upper part of the control gate 30 is covered with an interlayer insulating film 40 made of a silicon oxide film or the like. A connection hole 42 for connecting the control gate 30 to the aluminum wiring 44 via a contact 42 is formed at an appropriate position in the interlayer insulating film 40. In addition,
The source of the storage element 18 is, as shown in FIG.
Connected to source line 31.

In the semiconductor memory device 10 according to the first embodiment thus configured, the control gate 3
Steps after polycrystalline silicon forming 0 is deposited, for example, etching for forming a floating gate and a control gate electrode, ion implantation into a source formation region and a drain formation region, and further opening of a connection hole When charges (Process-Induced Charge) are accumulated on the top of the tunnel oxide film 24 at the time of etching for patterning the aluminum wiring into a predetermined shape or the like,
Since the control gate 30 is connected to the p-type well 14 through the formation region of the protection diode 20, charges flow to the semiconductor substrate 12 through this connection. Therefore, the tunnel oxide film 24 is not affected by a large potential difference, so that the film quality is prevented from deteriorating.
The leakage of the electrons injected into the semiconductor device can be prevented. Therefore, the data retention characteristics of the semiconductor memory device 10 can be greatly improved, and a highly reliable nonvolatile semiconductor memory device can be obtained.

That is, after writing data to the semiconductor memory device 10 and the conventional stacked memory device, 25
When left in a constant temperature room at 0 ° C., as shown in FIG.
In the conventional storage device (conventional example), the data retention rate rapidly decreases with the passage of time, whereas in the case of the semiconductor storage device 10 (embodiment) according to the above embodiment, 500
After the elapse of time, the data retention rate hardly decreased.

In addition, the protection diode 20 is
4 is formed with a gap g from the channel stopper 38, and operates when a potential difference larger than a write voltage, a read voltage, and an erase voltage to the storage element 18 is generated. , And erase operation. Further, even if an abnormally high voltage acts on control gate 30, voltage breakdown of tunnel oxide film 24 is prevented. In addition, since the control gate 30 is directly connected to the protection diode 20, the semiconductor memory device 10 does not require an aluminum wiring for connecting the two, and the structure can be simplified.
The manufacturing process can be simplified.

FIGS. 3 and 4 are views for explaining a method of manufacturing the semiconductor memory device 10 according to the first embodiment. First, FIG.
As shown in FIG. 1A, boron ions are implanted into the surface layer of the p-type semiconductor
4 is formed, and an oxide film (SiO 2) is formed on the well 14.
_A silicon nitride (silicon nitride Si ₃ N ₄ ) film 50 is formed by a CVD method or the like via a _second film), a resist film 52 is formed in an element formation region, and a silicon nitride film in an element isolation region is formed by a photoetching method or the like. And 50 are removed.

Next, after removing the resist film 52, FIG.
As shown in (b), a resist film 52 is formed on the silicon nitride film 50 in the element formation region. At this time, in the element formation region, the region where the protection diode 20 is formed is:
A resist film 52 is formed from the edge of the peripheral portion of the silicon nitride film 50 to the peripheral portion separated by a predetermined gap. Thereafter, the resist film 52 is used as a mask to irradiate an ion beam 54,
A channel stopper 38 is formed by implanting boron ions into the element isolation region. The predetermined gap from the edge of the peripheral portion of the silicon nitride film 50 corresponds to the above-mentioned gap g, and is set so that a predetermined operating voltage of the protection diode 20 can be reliably obtained. In the case of this embodiment, the gap g
Is about 0.3 to 0.8 μm as described above.

Next, after removing the resist film 52, thermal oxidation is performed using the silicon nitride film 50 as a mask.
As shown in (c), the field oxide film 16 is formed by selectively oxidizing the element isolation region. Thereafter, the oxide film (SiO ₂ film) and the silicon nitride film 50 on the p-type well 14 are removed by wet etching, and a predetermined thickness is formed on the p-type well 14 by a thermal oxidation method or the like. At the same time, a tunnel oxide film 24 made of a silicon oxide film or the like having an appropriate thickness and an insulating film 56 made of a silicon oxide film or the like are simultaneously formed in a region where a protection diode is formed.

After the formation of the p-type well 14 and the channel stopper 38, the p-type well 14 and the channel stopper 3 are formed in addition to the method of forming the field oxide film 16.
As another forming method of No. 8, there is a method of forming a p-type well 14 and a channel stopper 38 after forming a field oxide film.

A p-type well 14, a channel stopper 38,
After forming the tunnel oxide film 24 and the insulating film 56, polycrystalline silicon is deposited on the p-type well 14 to a predetermined thickness,
Phosphorus is doped into an n-type semiconductor, and the floating gate 26 having a predetermined shape is formed by photoetching using the resist film as a mask (FIG. 3).
(D)). The doping of polycrystalline silicon with phosphorus can be performed by ion implantation into the deposited polycrystalline silicon, or by introducing phosphorous chloride (POCl ₃ ) as a carrier gas. Next, p-type well 1
A so-called ONO film, in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated, is deposited on the upper part of the substrate 4 and is etched into a predetermined shape by a photo-etching method to form an insulating layer 28 on the floating gate 26. I do.

Thereafter, as shown in FIG. 4E, a resist film 58 is formed above the well 14 by a photoetching method, and then the insulating film 56 is selectively removed through the through hole 60. A contact hole 36 is formed. Then, as shown in FIG.
Then, a polycrystalline silicon layer is deposited, phosphorus is diffused in the same manner as described above, and this is patterned into a predetermined shape by a photoetching method to form a control gate 30 made of an n-type semiconductor. Next, the n-type semiconductor substrate 12 on which the control gate 30 is formed is subjected to a heat treatment, and the impurity (phosphorus) contained in the control gate 30 is diffused into the upper part of the p-type well 14 so that n serving as a cathode of the protection diode 20 is formed. A mold diffusion layer 34 is formed.

After the floating gate and the control gate electrode are formed by the photo-etching method in the same manner as in the prior art, phosphorus and arsenic are ion-implanted into the source forming region and the drain forming region to form an n-type diffusion layer. The semiconductor memory device 10 is formed by forming an interlayer insulating film, forming a contact, and forming an aluminum wiring.

FIGS. 5A and 5B are structural views of the semiconductor memory device according to the second embodiment, wherein FIG. 5A is a plan view and FIG.
FIG. 3A is a cross-sectional view along the line BB in FIG. In FIG. 5, in the semiconductor storage device 61, the storage element 18 has the control gate 30 connected to the p-type semiconductor substrate 12 via the protection diode 20 not shown in FIG. is there. Then, as shown in FIG. 5A, a selection gate 64 of the selection transistor 62 is provided in parallel with the control gate 30. The selection transistor 62 selects an arbitrary storage element 18 for performing a writing operation, a reading operation or an erasing operation. As shown in FIG.
A gate oxide film (gate insulating film) 66 made of a silicon oxide film is provided between the gate oxide film and the gate oxide film. An n-type diffusion layer 68 serving as a drain region is provided on one side of the selection gate 64.
Is formed. In addition, reference numeral 70 shown in (b) denotes an aluminum wiring constituting a source line.

In the second embodiment constructed as described above, since the storage element 18 and the selection transistor 62 are integrally formed, excessive erasure of the storage element can be prevented, and punch-through due to miniaturization is prevented. You can also. When manufacturing the semiconductor storage device 61,
The gate oxide film 66 is the same as the insulating film 56 shown in the first embodiment.
The selection gate 64 is formed simultaneously with the control gate 30.

A second protection diode (not shown), which is a second protection switch section, is formed between the selection gate 64 of the selection transistor 61 and the semiconductor substrate 12, and charges on the transistor 61 side (Process-Induced). Charge) can be prevented from deteriorating the gate oxide film 66. Then, the second protection diode can be formed in the same step as the step of forming the protection diode 20 described above.

FIGS. 6A and 6B show the third embodiment, wherein FIG. 6A is a plan view thereof, and FIG. 6B is a cross-sectional view taken along line CC of FIG. The semiconductor memory device 72 according to the third embodiment has a structure as shown in FIG.
The n-type diffusion layer 34 forming the protection diode 20 and the control gate 30 are connected by an aluminum wiring 44. That is, the protection diode 20 is formed on the side of the control gate 30. A contact hole 74 is formed in the interlayer insulating film 40 provided over the p-type well 14 at a position corresponding to the diffusion layer 34, and the aluminum wiring 44 is diffused through the contact hole 74. Connected to layer 34.

The aluminum wiring 44 is connected to the contact 42
Is connected to the control gate 30 via the.

In the third embodiment configured as described above, accumulation of charges (Process-Induced Charge) in the process after the formation of the aluminum wiring 44 is prevented, and deterioration of the film quality of the tunnel oxide film 24 is prevented. Can be.

As described above, a so-called flash memory capable of electrically erasing and rewriting information has been described as an embodiment. However, the present invention is not particularly limited to a flash memory. A so-called EPROM (Electrically Programmable Read Only)
memory) or a so-called EEPROM (electrically erasable rewrite) that can be electrically erased and rewritten.
The present invention is also effective in ad only memory).

In the case of an EPROM, the protection diode may be set to operate when a potential difference larger than a write voltage and a read voltage to the storage element occurs.

[0039]

As described above, an ion beam is irradiated by etching, ion implantation into a source / drain formation region, and the like, and a charge (Process-Induced Charge) is obtained.
When the charge is accumulated, the protection switch section is activated and the control gate and the semiconductor substrate are electrically connected, so that the accumulated charge (Process-Induced Charge) flows to the semiconductor substrate having a large capacity, and the potential difference generated in the tunnel oxide film is reduced. can do. As a result, the quality of the tunnel oxide film is prevented from deteriorating, the leakage of electrons injected into the floating gate can be prevented, and the data retention characteristics of the nonvolatile semiconductor memory device can be significantly improved, and the reliability can be improved. it can. In addition, since the protection switch section operates by a potential difference larger than any of the write voltage, the read voltage, and the erase voltage applied to the control gate, it has no effect on the write operation, the read operation, and the erase operation. Nothing. Further, even if an unexpected unexpected voltage is applied to the control gate, voltage breakdown of the tunnel oxide film can be prevented, and the reliability of the nonvolatile semiconductor memory device can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. FIG.
(C) is an equivalent circuit diagram.

FIG. 2 is a diagram comparing the data retention rates when the embodiment of the present invention and the conventional example are kept at a high temperature.

FIG. 3 is an explanatory diagram of a part of a step of manufacturing the semiconductor memory device according to the first embodiment.

4 is an explanatory diagram of a part of a process of manufacturing the semiconductor memory device according to the first embodiment, and is an explanatory diagram of a process subsequent to FIG. 3;

FIGS. 5A and 5B are structural views of a semiconductor memory device according to a second embodiment, wherein FIG. 5A is a plan view and FIG.
It is sectional drawing along the BB line of FIG.

FIGS. 6A and 6B are structural views of a semiconductor memory device according to a third embodiment, wherein FIG. 6A is a plan view thereof and FIG.
FIG. 5 is a sectional view taken along the line CC of FIG.

[Explanation of symbols]

 Reference Signs List 10 semiconductor storage device 12 p-type semiconductor substrate 14 p-type well 16 field oxide film 18 storage element 20 protection switch section (protection diode) 24 tunnel oxide film 26 floating gate 28 insulating layer 30 control gate 34 diffusion layer 38 channel stopper 44 aluminum wiring 56 Insulating film 61 Semiconductor memory device 62 Selection transistor 64 Select gate 66 Gate insulating film (gate oxide film) 72 Semiconductor memory device

Claims (9)

[Claims] 1. A nonvolatile semiconductor memory device having a storage element having a floating gate and a control gate, wherein a write voltage and a read voltage are provided between the control gate and a semiconductor substrate and applied to the control gate. And a protection switch unit that operates by a potential difference between the control gate and the semiconductor substrate which is higher than any one of an erase voltage and an electrical connection between the control gate and the semiconductor substrate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said protection switch section is a protection diode comprising a well formed above said semiconductor substrate and a diffusion layer. Semiconductor storage device. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said diffusion layer is formed by diffusing an impurity in said control gate into said well. 4. The non-volatile semiconductor memory device according to claim 2, wherein said diffusion layer is formed with a gap from a channel stopper provided below a field oxide film formed between said diffusion layer and said memory element. The nonvolatile semiconductor memory device, wherein the gap has a width that can withstand all of the write voltage, the read voltage, and the erase voltage. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said semiconductor substrate comprises:
A nonvolatile semiconductor memory device comprising: a plurality of storage elements; and a selection transistor for selecting an arbitrary storage element for performing a write, read, or erase operation. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said selection transistor has a second protection switch portion formed between a selection gate and said semiconductor substrate. Non-volatile semiconductor storage device. 7. A method of manufacturing a nonvolatile semiconductor memory device having a storage element having a floating gate and a control gate, comprising: a first conductivity type well on a first conductivity type semiconductor substrate; a channel stopper in an element isolation region; Forming a field oxide film; forming a tunnel oxide film on the first conductivity type well; depositing first polycrystalline silicon on the tunnel oxide film and etching it into a predetermined shape; Forming an insulating layer on the floating gate, forming an insulating film in a region where the protection diode is formed, and providing a resist film over the insulating film to form a predetermined shape. Providing a contact hole in the insulating film by patterning and etching; and contacting the insulating layer with the contact layer. Forming a control gate by depositing a second polycrystalline silicon covering the tohole and patterning the same into a predetermined shape; and heat-treating the semiconductor substrate on which the control gate has been formed to remove impurities in the control gate. Forming a second-conductivity-type diffusion layer by diffusing the first-conductivity-type well through a contact hole. 8. The method for manufacturing a nonvolatile semiconductor memory device according to claim 7, wherein said storage element is formed in a plurality, and a write, read, or erase operation is performed when said insulating film is formed. A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a gate insulating film of a selection transistor for selecting an element; and forming a selection gate of the selection transistor when forming the control gate. 9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein, when forming the gate insulating film,
Forming an insulating film in a formation region of a second protection diode connected to the selection transistor, forming a second contact hole in the formation film of the second protection diode when forming the contact hole; A method for manufacturing a nonvolatile semiconductor memory device, wherein a gate is provided so as to cover a second contact hole, and an impurity in a select gate is diffused into the first conductivity type well during heat treatment of the semiconductor substrate.