JPH0851164A - Non-volatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a non-volatile semiconductor storage device having a structure being easily manufactured. CONSTITUTION:A source region 13 and a drain region 12 are formed into one conductivity type semiconductor substrate 11, and active regions isolated by element isolation insulating films 14 are formed onto the semiconductor substrate 11. A gate insulating film 15 is shaped onto a specified channel region held by the source region 13 and the drain region 12 and brought into contact with the source region 13, and a floating gate electrode 16 is formed onto the gate insulating film 15. A simultaneously formed control gate electrode 20 and an erasing gate electrode 21 are arranged onto the floating gate electrode 16 through an inter-layer insulating film 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional electrically writable non-volatile memory (EPROM) is located between a source region and a drain region, insulated from a channel region in a semiconductor substrate, and arranged so as to cover the channel region. Has an electrically floating conductive gate electrode (floating gate electrode),
Further, a control gate electrode is arranged so as to cover the floating gate electrode. However, the control gate electrode is insulated from the floating gate electrode.

The threshold voltage of such an electrically writable nonvolatile memory transistor is controlled by the amount of charge held in the floating gate electrode. That is, by injecting electrons from the channel region into the floating gate electrode through the thin gate insulating film, the transistor is in a writing state.

The method of reading the state of the transistor is to apply an operating voltage between the source region and the drain region of the transistor and to the control gate electrode, and detect the level of the current flowing between the source region and the drain region at that time. It is done by doing.

Early EPROM devices erase the accumulated charge by irradiating them with ultraviolet light. Recently, a transistor cell is an electrically erasable EEPROM (Electrically Erasable and Programmable EEPROM).
ble ROM) is widely used. Early EEPRO
M has a structure in which electric charges are transferred from the floating gate electrode of the transistor to the source region through a dielectric layer having a very thin tunnel phenomenon, thereby electrically erasing. More recently, EEPROM memory cells have been configured with an independent third erasing gate electrode.
For example, it is proposed in Japanese Patent Publication No. 1-50116. The erasing gate electrode is arranged on the surface of the floating gate electrode so as to extend to a plurality of adjacent memory transistors via a thin insulating film that can serve as a tunneling medium. Therefore, when an appropriate voltage is applied to the erase gate electrode, a plurality of memory transistors are erased at the same time. A cell array composed of such an EEPROM is generally called a flash type EEPROM cell array.

FIG. 6 is a sectional view of a conventional EEPROM cell. FIG. 7A is a plan view of a conventional EEPROM cell,
(B) is a cross-sectional view taken along the line AA 'of (A), (C) is B of (A).
It is a -B 'sectional view.

In FIGS. 6 and 7, 1 is a semiconductor substrate, 2 is a drain region, 3 is a source region, 4 is a gate insulating film, 5 is a floating gate electrode, 6 is an interlayer insulating film, 7 is a control gate electrode, 8 Is a silicon oxide film used for element isolation, 9
Is an erase gate electrode.

In the EEPROM of FIG. 6, the drain region 2
Is applied to generate hot electrons (high energy electrons) by the electric field between the drain region 2 and the source region 3. By applying a voltage to the control gate electrode 7 with the hot electrons, electrons are efficiently injected into the floating gate electrode 5. From this, writing to the memory transistor is performed. On the other hand, erasing is performed in the source region 3
Electrons stored in the floating gate electrode 5 are tunneled to the source region 3 by applying a voltage to the source region 3. As a method of reading the state of the transistor, an operating voltage is applied between the source region 3 and the drain region 2 of the transistor and the control gate electrode 7. It is performed by detecting the level of the current flowing between the source region 3 and the drain region 2 at that time. The EEPROM having the structure of FIG. 6 is called a stack gate type EEPROM.

The writing and reading methods of the EEPROM of FIG. 7 are similar to those of the EEPROM of FIG. 6, but erasing is performed by applying a voltage to the erase gate electrode 9. The EEPROM having the structure shown in FIG. 7 is a three-layer PS type EE.
Called PROM.

A stack gate type EEPROM having such a multi-layer electrode has a simple cell structure, a small cell area, and is suitable for a large capacity. However, since the tunneling phenomenon is used for erasing, the gate insulating film 4 must be thin. In addition, since the same gate insulating film 4 is used during writing, the reliability of the gate insulating film 4 deteriorates,
The number of rewrites decreases. Further, when erasing a plurality of memory transistors simultaneously, the erasing state differs depending on each memory transistor. Therefore, a certain memory transistor may become a normally-on type transistor (overerased) in a state where it is erased too much, which causes erroneous reading. Therefore, in recent years, a three-layer PS type EEPRO having a structure as shown in FIG. 7 is provided with an erase gate electrode 9 exclusively for erasing in order to increase the number of times of rewriting, and a split gate in order to solve the problem of overerase.
M is invented.

[0011]

However, in the conventional three-layer PS type EEPROM as described above, it is necessary to separately form the three-layer gate electrodes 5, 7, 9 and the number of steps increases, which is a solution. There were some issues to be solved. Further, since the structure is complicated, there is a problem that the step becomes very large and it is difficult to manufacture.

The present invention solves the above-mentioned conventional problems, and provides a nonvolatile semiconductor memory device and its manufacturing method which can simplify the manufacturing method by simultaneously forming a control gate electrode and an erase gate electrode. The purpose is to provide.

[0013]

To achieve this object, a semiconductor memory device according to the present invention has a source region and a drain region provided in a semiconductor substrate of one conductivity type, and is sandwiched between the source region and the drain region. A gate insulating film is formed on a predetermined channel region in contact with the region, a floating gate electrode is provided on the gate insulating film, and at least a control gate electrode and an erase gate electrode are provided on the floating gate electrode via an interlayer insulating film. I have it.

In order to achieve this object, a method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming a source region and a drain region in one conductivity type semiconductor substrate, and a step of sandwiching the source region and the drain region between the source region and the drain region. A step of forming a gate oxide film on a predetermined channel region in contact with the gate insulating film, a step of forming a floating gate electrode on the gate insulating film, a step of forming an interlayer insulating film on the floating gate electrode, and a step of forming an interlayer insulating film on the interlayer insulating film. The method further includes at least a step of simultaneously forming a control gate electrode and an erase gate electrode.

[0015]

According to the manufacturing method of the present invention, since the control gate electrode and the erase gate electrode are formed at the same time, the process can be simplified. In addition, the step can be reduced, which facilitates manufacturing.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of this embodiment, FIG. 1B is a sectional view taken along the line AA 'of FIG. 1A, and FIG. 1C is a sectional view taken along the line BB' of FIG.

The semiconductor substrate 11 is a P-type impurity-doped silicon substrate having a low concentration. In the semiconductor substrate 11,
A drain region 12 and a source region 13 are formed. Sandwiched between the drain region 12 and the source region 13,
A floating gate electrode 16 made of a polysilicon film is formed on a predetermined channel region in contact with the source region 13 with a silicon oxide film 15 which can be a gate insulating film interposed therebetween. A control gate electrode 20 is formed on the floating gate electrode 16 via an interlayer insulating film 17. The erase gate electrode 21 is formed simultaneously with the control gate electrode 20, and is formed so as to straddle the adjacent floating gate electrodes 16 with the interlayer insulating film 17 interposed therebetween.

Next, referring to the process sectional views of FIGS. 2 (A) to 5 (A) and 2 (B) to 5 (B), regarding one embodiment of a specific manufacturing method of the present invention. While explaining. Figure 2
(A) to FIG. 5 (A) are process cross-sectional views of the AA ′ cross-section part in FIG. 1, and FIG. 2 (B) to FIG. 5 (B) are process cross-sectional views of the BB ′ cross-section part in FIG. 1. Is.

First, as shown in FIGS. 2 (A) and 2 (B),
In the semiconductor substrate 11, using the photoresist as a mask,
Arsenic ions are implanted to form the drain region 12 and the source region 13. Next, a silicon oxide film is deposited and formed to a thickness of about 500 nm by a vapor phase growth method, and patterning is performed by a known photoetching technique using a photoresist to form a silicon oxide film 14 used for element isolation. To do.

Next, as shown in FIGS. 3 (A) and 3 (B),
The semiconductor substrate 11 is oxidized by 30 nm to form a silicon oxide film 15 that can serve as a gate insulating film. Next, a phosphorus-doped polysilicon film is deposited to a thickness of 300 nm on the entire surface of the semiconductor substrate 11 by a known vapor deposition method. The floating gate electrode 16 is formed by patterning this using a known etching technique using a photoresist.

Next, as shown in FIGS. 4A and 4B, a silicon oxide film is deposited to a thickness of 20 nm on the floating gate electrode 16 by a known vapor phase growth method to form an interlayer insulating film. 1
Form 7. Next, a phosphorus-doped polysilicon film 18 of 300 nm is deposited on the entire surface by a known vapor phase growth method. Next, a resist mask pattern 19 for forming a control gate and an erase gate is formed.

Next, as shown in FIGS. 5A and 5B, the control gate electrode 20 is formed by using a known photoetching technique.
And the erase gate electrode 21 is formed at the same time. As a result, the nonvolatile semiconductor memory device as shown in FIGS. 5A and 5B is completed.

As described above, in this embodiment, the process can be simplified by forming the control gate electrode 20 and the erase gate electrode 21 at the same time. Further, the step can be reduced, and the manufacturing is easy.

[0025]

According to the present invention, in the nonvolatile semiconductor memory device having the erase gate, the manufacturing process can be simplified and the step can be reduced, so that the manufacturing is facilitated. Become.

[Brief description of drawings]

1A is a plan view of an embodiment of a nonvolatile semiconductor memory device of the present invention, FIG. 1B is a sectional view taken along the line AA ′ of FIG. 1A, and FIG. 1C is a sectional view taken along the line BB ′ of FIG. Figure

2A and 2B are process cross-sectional views of an embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention, where FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1A and FIG. BB 'of (A)
Sectional view

3A and 3B are process cross-sectional views of an embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention, where FIG. 3A is a cross-sectional view taken along the line AA ′ in FIG. 1A and FIG. BB 'of (A)
Sectional view

4A and 4B are process cross-sectional views of an embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention, where FIG. 4A is a cross-sectional view taken along the line AA ′ of FIG. 1A and FIG. BB 'of (A)
Sectional view

5A and 5B are process cross-sectional views of one embodiment of the method for manufacturing a nonvolatile semiconductor memory device of the present invention, where FIG. 5A is a cross-sectional view taken along the line AA ′ of FIG. 1A and FIG. BB 'of (A)
Sectional view

FIG. 6 is a sectional view of a conventional nonvolatile semiconductor memory device.

7A is a plan view of a conventional nonvolatile semiconductor memory device, FIG. 7B is a sectional view taken along line AA ′ of FIG. 7A, and FIG. 7C is a sectional view taken along line BB ′ of FIG.

[Explanation of symbols]

 11 semiconductor substrate 12 drain region 13 source region 14 silicon oxide film 15 gate insulating film 16 floating gate electrode 17 interlayer insulating film 18 polysilicon film 19 resist pattern 20 control gate electrode 21 erase gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (2)

[Claims] 1. A source region and a drain region are provided in a semiconductor substrate of one conductivity type, and a gate insulating film is formed on a predetermined channel region which is sandwiched between the source region and the drain region and is in contact with the source region. A nonvolatile semiconductor memory device comprising a floating gate electrode on the gate insulating film, and at least a control gate electrode and an erase gate electrode on the floating gate electrode via an interlayer insulating film. 2. A step of forming a source region and a drain region in a one conductivity type semiconductor substrate, and a gate oxide film is formed on a predetermined channel region which is sandwiched between the source region and the drain region and is in contact with the source region. A step of forming a floating gate electrode on the gate insulating film,
Forming an interlayer insulating film on the floating gate electrode;
A method of manufacturing a nonvolatile semiconductor memory device, comprising at least a step of simultaneously forming a control gate electrode and an erase gate electrode on the interlayer insulating film.