JPH10223782A - Non-volatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device whose memory can be electrically erased and which can be formed on the same substrate where a usual bipolar transistor and a CMOS transistor are formed without growing complicated in structure and making a manufacturing process complex. SOLUTION: A non-volatile semiconductor memory device is equipped with a well 308 whose conductivity type is opposite to that of a substrate 301 and which is formed on one side of the substrate 301 which is isolated from the other side by a field oxide film 302, a control electrode diffusion layer 305 which is of the same conductivity type with the substrate 301 and formed in the well 308, a source 303 and a drain 304 comprised in a memory transistor formed in the other side of the substrate 301, and a floating gate electrode 307 formed on a channel region between the source 303 and the drain 304 and the control electrode in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a single-layer EEPROM memory cell suitable as a redundant circuit of a mask ROM memory device.

[0002]

2. Description of the Related Art A typical EPROM as a nonvolatile semiconductor memory device electrically writes data and erases the data by irradiating ultraviolet rays or the like. There are several types of EPROMs, such as bipolar transistors and CMOs.
Further EPROMs have been proposed which can suppress an increase in the number of steps when they are formed on the same substrate as an S transistor or the like.

The structure of a conventionally proposed single-layer EPROM will be described with reference to a partial sectional perspective view of FIG. 7 and a plan view of FIG. In FIG. 8, a gate oxide film, which will be described later, is omitted for easy understanding.

A field oxide film 102 made of a thick oxide film for element isolation is formed on the surface of a p-type substrate 101 by a selective oxidation method (for example, a LOCOS method). On the surface on one side (the front side in FIG. 7), n ⁺ regions 103 and 104 serving as source and drain regions are formed across the channel region, and correspondingly, on the opposite side of the field oxide film (FIG. 7). A control gate electrode 105, which is an n ⁺ region, is formed on the substrate surface on the back side in FIG. The gate oxide film 1 is formed on the control gate electrode 105, the channel region, the source region 103, and the drain region 104.
06 is further formed on the gate oxide film so as to cover all of the control gate electrode 105, part of the field oxide film 102, and all of the channel region, and overlap with part of the source region 103 and the drain region 104. A floating gate electrode 107 is formed.

Therefore, by employing such a structure, the control gate electrode 105 and the source / drain region layers 103 and 104 for supplying electrons to the floating gate 107 controlled by the control gate electrode 105 are in the same layer. Will be formed.

Next, the writing and erasing operations of the EPROM 100 will be described. First, writing is performed by applying a relatively high potential control voltage (up to 7
v), the source region 103 is set to the ground potential GND, and a program voltage (電 圧 5 V) is applied to the drain region 104. At this time, since the floating gate electrode 107 rises to a certain voltage due to capacitive coupling with the control gate electrode 105, the floating gate electrode 107, the source region 103,
The nonvolatile memory transistor formed of the drain region 104 is turned on, and a channel current flows to generate hot carriers near the drain. Some of the hot carriers are injected into the floating gate electrode 107 through the gate oxide film, and writing is performed.

Next, in erasing, by irradiating ultraviolet rays from the outside, electrons are extracted from the floating gate electrode, and all memory transistor cells can be erased collectively.

Such a one-layer EPROM cell has a mask R
It is often used as a redundant circuit cell (redundancy cell) of an OM (MROM).
Referring to FIG. 9, the configuration of a single-layer EPROM cell when the cell is configured as a virtual ground cell will be described.

Referring to FIG. 9, an MROM cell region surrounded by a field oxide film 102 is provided on a p-type substrate 101.
A buried n ⁺ layer 109 made of a stripe pattern is formed on this surface, and serves as a source and a drain of the MROM cell.

The buried n ⁺ layer 109 is formed by ion-implanting, for example, As ions, which are n ⁺ impurities, using a resist as a mask. After the ions are implanted, the gate is oxidized to form a gate oxide film 106. Is done. Next, the gate electrode 10 is formed on the gate oxide film 106.
7, the basic structure of the virtual ground MROM cell is formed.

When a single EPROM cell is mounted as a redundancy cell of the virtual ground MROM, the control gate electrode 10 of the single-layer EPROM described with reference to FIGS.
5, the source region 103 and the drain region 104
It is formed simultaneously with the embedded n ⁺ layer 109 of the OM cell.

As described above, in the prior art, when a writable storage device cell is mounted on the same substrate as a bipolar transistor and a CMOS transistor, an ultraviolet erasing type EPROM has been manufactured to suppress an increase in the number of manufacturing steps.

However, a single layer EPROM of an ultraviolet erasing type
In this case, during the manufacturing process, charge-up occurs due to ion implantation or the like, and the floating gate potential of the product is not constant. In order to prevent this, it is necessary to perform ultraviolet erasing in the manufacturing process, or to use ultraviolet-permeable one as an interlayer film on the EPROM to perform ultraviolet erasing in the final step over several hours. There is a problem that it takes time.

Therefore, in order to collectively erase data in a short period of time, it is necessary to use the EPROM as an EEPROM, that is, to electrically erase the data.

There are two methods for using the EEPROM, that is, for realizing electrical erasure. In the first method, a relatively low positive voltage is applied to the source, a negative voltage is applied to the control gate electrode, and the electrons in the floating gate electrode are generated by the Fowler-Nordheim tunnel effect. This is a method of assisting release to

The second method is a method of applying a high positive voltage to the source so as not to require the assistance of a negative control voltage and tunneling electrons in the floating gate electrode to the source. That is, in this method, the control gate electrode of the n-type diffusion layer formed on the p-type substrate is set to GND, a high voltage (（10 V) is applied to the source region, the drain region is opened, and electrons in the floating gate electrode are discharged. This is a method of extracting to the source region.

[0017]

However, in this method, since a high voltage needs to be applied between the source region and the control gate electrode, it is necessary to provide a high breakdown voltage structure between the source region and the control gate electrode, for example, a GDD structure. However, such a high breakdown voltage structure has a drawback that it is contrary to the demand for miniaturization.

Under such circumstances, the EEPR shown in FIG.
This will be described more specifically with reference to a perspective view of the OM cell 200.

As in the case of FIG.
Reference numeral 00 denotes a p-type semiconductor substrate 20 having a field oxide film 202 formed by a selective oxidation method (LOCOS method).
1, a source region 203 and a drain region 204 that are n-type diffusion layers, and a control gate electrode 205 that is an n-type diffusion layer adjacent to the source region 203 and the drain region 204 via a field oxide film 202. And a floating gate electrode 2 formed so that a source region 203, a drain region 204, and a part of a control gate electrode 205 are overlapped via an insulating film 206 on a substrate surface.
07 are formed.

Since an electric field of about 10 MV / cm is required to emit electrons through the gate oxide film 206 by tunneling, if the thickness of the gate oxide film 206 is 10 nm, a voltage of 10 V is required. Is required to be 10 V or more. In order to withstand this high potential, the source diffusion layer must have a high breakdown voltage structure. As shown in FIG. 10, the n ⁺ layer 203 forming the source region is replaced with the n ⁻ layer 20.
8 must be covered.

In order to form the n ⁻ layer 208, in the manufacturing process, one resist patterning and one n ^{− layer}
Although ion implantation can be formed only by adding an additional layer to the EPROM process, the n ⁻ layer 208 cannot be formed in a self-aligned manner with respect to the source region 203 and the drain region 204 where tight alignment is required. For this reason,
A margin for alignment is required, which is against the demand for miniaturization.

Further, when overprinting of ions in the buried ^{n +} layer 109 and the same resist patterning of MROM cell shown in FIG. 9, n in the buried ^{n +} layer 109 of MROM cells that are simultaneously formed ^- ion implantation Is performed, and M
There is a problem that the ROM cell cannot be miniaturized.

As described above, the second method in which electrons in the floating gate are tunnel-emitted to the source by applying a high positive voltage to the source so as not to require the assistance of the gate voltage has a problem in terms of miniaturization. is there.

Therefore, the present invention realizes an electrically erasable nonvolatile semiconductor memory device which can be formed on the same substrate as a normal bipolar and CMOS transistor without complicating the structure and process, and a method of manufacturing the same. The purpose is to:

[0025]

A nonvolatile semiconductor memory device according to the present invention is provided on a surface of a semiconductor substrate of a first conductivity type and defines a field oxide film defining an element region, and the field oxide film of the semiconductor substrate. A source region and a drain region formed of a first diffusion layer of a second conductivity type formed on one side of a surface portion of the semiconductor substrate separated by a channel region and separated by the field oxide film; A second diffusion layer of the second conductivity type formed as a well on the other side of the surface portion of the semiconductor substrate; and a third diffusion layer of the first conductivity type serving as a control gate electrode and formed in the second diffusion layer. A thin insulating film formed on the surface of the semiconductor substrate, through which electrons can pass by an applied voltage, the entire surface of the control gate electrode and the channel region, and the source region and the drain. It is characterized in that a floating gate electrode disposed formed above a portion of the region.

As described above, since the control gate electrode of the non-volatile memory device cell is formed of a diffusion layer of the same conductivity type as the substrate in a well formed of a diffusion layer of the conductivity type opposite to the substrate,
A control electrode can be formed with high accuracy, and a nonvolatile semiconductor memory device that can be electrically erased while realizing miniaturization can be provided.

In a method for manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a field oxide film on a substrate of a first conductivity type by a selective oxidation method, and a step of separating the field oxide film by the field oxide film. A step of selectively forming a second conductivity type well in a region where a control electrode is to be formed on one side of the semiconductor substrate; a step of implanting first conductivity type ions into the well; Selectively implanting ions of the second conductivity type into the source and drain formation regions of the memory transistor on the other side of the semiconductor substrate, forming a thin oxide film to be a gate oxide film over the entire surface, and forming an electrode over the entire surface. A floating gate electrode is formed by depositing a material and performing patterning to partially overlap the source and drain formation regions and between the two, and on the control electrode formation region. Comprising a degree, by heat treatment, the implanted ions are diffused, and a step of forming a source region, a drain region, a control electrode to become diffusion layer, respectively.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a sectional perspective view of a one-layer EEPROM cell 300 according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. In this figure, FIG. 7 or FIG.
0, the field oxide film 302 for device isolation formed of a thick oxide film on the surface of the p-type substrate 301 is LOC.
It is formed by the OS method or the like. One side (front side in FIG. 1) of the semiconductor substrate separated by the field oxide film
N ⁺ regions 303 serving as source and drain regions
And 304 are formed across the channel region;
Correspondingly, an n ^- well 308 is formed in the substrate on the opposite side of the field oxide film (on the far side in FIG. 1).
A control gate electrode 305 which is ap ⁺ region is formed therein. The control gate electrode 305, the channel region and the source region 303, and the drain region 30
4, a gate oxide film 306 is formed, and further covers the entire control gate electrode 305, a part of the field oxide film 302, and the entire channel region on the gate oxide film.
Part 311 of source region 303 and drain region 30
Floating gate electrode 30 so as to overlap with part 312 of
7 are formed. The end of the n ^- well partially reaches below the field oxide film 302. On the other hand, the control gate electrode 305 is formed in a region defined by the field oxide film.

As in the case of FIG. 7, by employing such a structure, the control gate 306 and the source / drain region layer 303 for supplying electrons to the floating gate electrode 307 controlled by the control gate electrode 305 are provided. , 304
Are formed in the same layer.

FIGS. 3 to 6 are sectional views showing steps of a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.
Is used as a redundancy cell of a virtual ground mask ROM (MROM) having a single-layer polysilicon wiring structure.

First, as shown in FIG.
The resist is patterned so that the region where the control gate electrode is to be formed is opened, phosphorus is selectively implanted, an oxidation-resistant nitride film is formed in the element region, and oxidation is performed to form a field oxide film. Form 302 and n ^- well 308. The end of the n ^- well 308 formed at this time reaches almost the center of the lower surface of the field oxide film 302.
Further, the nitride film is removed, and a thermal oxide film 321 serving as a gate oxide film is formed on the surface of the semiconductor substrate.

Next, a resist 322 is provided on the oxide film 306, and is patterned by a lithography process so that an end of the resist opening is located on the field oxide film. Using this resist 322 as a mask, n ^- well 3
08 with a dose of 1 × 15 cm ⁻² and 49BF ₂ ⁺ p
Type ions are implanted into the silicon substrate 301 at an angle of 0 degrees to form an implanted layer 323. After that, resist 32
Remove 2.

Next, as shown in FIG.
M serving as source and drain regions and RO
Resist 3 having an opening in a portion serving as a buried layer in M region
24, and 1 × is formed using this resist 324 as a mask.
At a dose of 15 cm ^-2 , 75 As ⁺ n-type ions are implanted into the silicon substrate 301 at an angle of 0 ° to form an ion implanted layer 325. After that, the resist 324
And oxide film 321 is removed.

Next, as shown in FIG. 5, a gate oxide film 306 is formed on the surface of the silicon substrate 301 by performing a thermal oxidation process.
Is formed, and tungsten polycide is deposited on the gate oxide film 306 to perform patterning.
A floating gate electrode of OM and a polycide electrode 307 to be a gate electrode of MROM are obtained.

As described above, the floating gate electrode is connected to the normal MO.
By forming a common tungsten polycide layer with the gate electrode of the S transistor, the EEPROM can be replaced with a normal bipolar and CMO without complicating the structure and process.
It can be formed over the same substrate as the S transistor.

Next, a heat treatment is performed to make the already formed 49BF ₂ ⁺ p-type ion-implanted layer 323 and 75 As ⁺
The ions in the n-type ion implantation layer 325 are diffused to form a single layer EP.
A source region 303 and a drain region 304 of the ROM, a diffusion layer 305 serving as a control gate electrode, and a buried region 309 of the ROM portion are formed.

Next, as shown in FIG. 6, an oxide film 326 is deposited on the entire silicon substrate to make contact with the source region 303, the drain region 304, the control gate electrode 307, and the gate polycide 307 of the ROM portion. After aluminum is deposited, aluminum is deposited and then patterned to obtain a wiring 327, on which an insulating protective film 328 is deposited. As a result, a more electrically erasable and erasable EEPROM is completed. In this EEPROM,
The source 303 and the drain 304 can be formed simultaneously with the buried n ⁺ diffusion layer 309 of the MROM cell, and the control gate diffusion layer 305 is constituted by the p ⁺ diffusion layer formed in the n ⁻ well 308. It is the characteristic.

A method of electrically writing and erasing data in the one-layer EEPROM 200 will be described.

For writing, the control gate electrode 305
Then, a control voltage (７7 V) is applied to the n ^- well 308, a program voltage (〜5 V) is applied to the drain region 304 with the source region 303 set to GND. At this time, the floating gate electrode 307 rises to a certain voltage due to capacitive coupling with the control electrode 305, the nonvolatile memory transistor is turned on, a channel current flows, and hot carriers are generated near the drain. Some of the hot carriers pass through the oxide film and are injected into the floating gate electrode 307 (Fowler-Nordheim tunnel phenomenon), so that writing is performed.

For erasing, the n ^- well 308 is set to GND, and a negative control voltage (to
-10v) is applied. The drain region 304 is open, and a positive voltage (up to 7 V) is applied to the source region 303. At this time, the floating gate electrode 307 has a negative potential and a potential difference from the source region 303 causes the floating gate electrode 307 to have a negative potential.
The electrons injected into the floating gate electrode
Fowler-Nordheim tunnel current between source regions flows to perform erasure.

As described above, the one-layer EEPROM according to the present embodiment uses the first method described above, namely, applying a relatively low positive voltage to the source, applying a negative voltage to the control gate electrode, and applying a negative voltage to the control gate electrode. This method employs a method in which electrons in the floating gate electrode are tunneled to the source by assisting the control voltage.

In the structure of the one-layer EEPROM according to the present invention, the p ⁺ diffusion layer 305 serving as a control gate diffusion layer is formed in the n ⁻ well 308 as compared with the conventional one, and the number of steps for this is increased. . However, the p ⁺ diffusion layer 30
The increase in the number of steps for forming 5 is one time of resist patterning and one time of ion implantation, which is the same as the case where the n ⁻ layer 208 of FIG. 10 is conventionally formed for increasing the breakdown voltage. Further, the source 303 and the drain 304 can be formed simultaneously with the n ⁺ layer 309 buried in the MROM cell, which does not violate the demand for miniaturization of the MROM cell.

Further, in the one-layer EEPROM of this embodiment,
Although the n ⁻ well 308 and the p ⁺ diffusion layer 305 cannot be formed in a self-aligned manner, they do not need to be strictly controlled for alignment, and therefore, non-self-aligned is sufficient.

As described above, the nonvolatile semiconductor memory device according to this embodiment does not impair the miniaturization and does not require complicated steps, as compared with the device used by the second method.

[0046]

According to the nonvolatile semiconductor memory device of the present invention, since the control gate electrode is provided in the well, miniaturization is possible even when mounted on the same chip as the virtual ground MROM cell. Becomes

Further, according to the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the process is not complicated.
A nonvolatile semiconductor memory device can be formed on the same substrate as a normal bipolar and CMOS transistor.

[Brief description of the drawings]

FIG. 1 is a sectional perspective view showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a plan view showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 3 is a sectional view showing a method for manufacturing a one-layer EEPROM according to the present invention.

FIG. 4 is a sectional view showing a method for manufacturing a one-layer EEPROM according to the present invention.

FIG. 5 is a sectional view showing a method for manufacturing a one-layer EEPROM according to the present invention.

FIG. 6 is a sectional view showing a method for manufacturing a one-layer EEPROM according to the present invention.

FIG. 7 is a cross-sectional perspective view showing a configuration of a conventional one-layer EPROM.

FIG. 8 is a plan view showing a conventional one-layer EPROM.

FIG. 9 is a cross-sectional view showing a virtual ground MROM cell on which a conventional one-layer EPROM is mounted.

FIG. 10 is a perspective view showing a conventional one-layer EPROM.

[Explanation of symbols]

101, 201, 301 p-type Si substrate 102, 202, 302 field oxide film 103, 203, 303 source region 104, 204, 304 drain region 105, 205, 305 control gate electrode 106, 206, 306 gate oxide film 107, 207 , 307 Floating gate electrode 109 MROM embedded n + diffusion layer 308 n ^- well 326 Oxide film 327 Metal wiring 328 Insulation protection film

Claims (9)

[Claims] A field oxide film provided on a surface of a semiconductor substrate of a first conductivity type and defining an element region; and a channel formed on one side of a surface of the semiconductor substrate separated by the field oxide film of the semiconductor substrate. A source region and a drain region formed of a first diffusion layer of a second conductivity type formed at a distance from each other, and a well formed on the other side of the semiconductor substrate surface portion separated by the field oxide film; 2nd conductivity type second
A diffusion layer; a third diffusion layer of a first conductivity type serving as a control electrode formed in the second diffusion layer; and a thin insulating film formed on the surface of the semiconductor substrate and through which electrons can pass by an applied voltage. And a floating gate electrode disposed and formed on the entire surface of the control gate electrode and the channel region and above a part of the source region and the drain region. 2. The nonvolatile semiconductor memory device according to claim 1, wherein an end of said well reaches a lower portion of said field oxide film. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device is an electrically erasable nonvolatile semiconductor memory device. 4. The non-volatile semiconductor memory device according to claim 3, wherein a non-rewritable semiconductor memory device is formed adjacently. 5. The non-volatile semiconductor memory device according to claim 4, wherein said floating electrode also serves as a gate wiring of said non-rewritable semiconductor memory device. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said floating gate electrode is made of polycide in which a refractory metal silicide is deposited on a polysilicon film. 7. A method according to claim 1, wherein the first conductivity type substrate is selectively oxidized on a substrate.
Forming a field oxide film; selectively forming a second conductivity type well in a control electrode formation region on one side of the semiconductor substrate separated by the field oxide film; A step of implanting ions of one conductivity type; a step of selectively implanting ions of second conductivity type into a source / drain formation region of a memory transistor on the other side of the semiconductor substrate separated by the field oxide film; Forming a thin oxide film to be a gate oxide film on the entire surface; depositing an electrode material on the entire surface and patterning the electrode material so as to partially overlap the source and drain formation planned regions, and the control electrode planned region A step of forming a floating gate electrode thereon and a heat treatment are performed to diffuse the implanted ions, thereby forming a source region, a drain region, and a diffusion layer serving as a control electrode. Method of manufacturing a nonvolatile semiconductor memory device including the step of respectively forming. 8. When selectively implanting ions of a second conductivity type into a region where a source and a drain of a memory transistor are to be formed,
At the same time, the second region is also set to the buried diffusion layer planned region of the non-rewritable semiconductor memory device provided adjacent to the memory transistor.
8. The method according to claim 7, wherein conductive type ions are implanted. 9. The nonvolatile semiconductor memory according to claim 8, wherein said floating gate electrode is formed by patterning together with a gate wiring of said non-rewritable semiconductor memory device. apparatus.