KR950006232B1 - Flash eeprom cell and manufacturing method thereof - Google Patents
Flash eeprom cell and manufacturing method thereof Download PDFInfo
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- KR950006232B1 KR950006232B1 KR1019910022064A KR910022064A KR950006232B1 KR 950006232 B1 KR950006232 B1 KR 950006232B1 KR 1019910022064 A KR1019910022064 A KR 1019910022064A KR 910022064 A KR910022064 A KR 910022064A KR 950006232 B1 KR950006232 B1 KR 950006232B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
Description
제1도는 종래의 스택-게이트형 플레쉬 EEPROM의 단면도.1 is a cross-sectional view of a conventional stack-gate type flash EEPROM.
제2도는 본 발명의 플래쉬 EEPROM 셀의 단면도.2 is a cross-sectional view of the flash EEPROM cell of the present invention.
제3a 내지 3f도는 본 발명의 플래쉬 EEPROM의 제조 공정도.3A to 3F are process drawings of the flash EEPROM of the present invention.
제4a 내지 4c도는 본 발명의 플래쉬 EEPROM의 동작원리를 나타낸 등가회고도.4A to 4C are equivalent gray levels illustrating the operation principle of the flash EEPROM of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 터널 산화화(SiO2)1: Semiconductor Substrate 2: Tunnel Oxidation (SiO 2 )
2' : 게이트 산화막 3 : 플로팅 게이트전극2 ': gate oxide film 3: floating gate electrode
4 : 층간 절연막 5 : 제어 게이트전극4 interlayer insulating film 5 control gate electrode
6 : 소오스전극 7 : 드레인 전극6 source electrode 7 drain electrode
8 : 중첩영역 9 : 채널8: overlapping area 9: channel
10 : 필드 산화막 11 : 액티브 영역10: field oxide film 11: active region
12 : 감광막패턴 13 : 제1폴리실리콘12 photosensitive film pattern 13: first polysilicon
14 : 중간 절연막 15 : 금속층14 intermediate film 15 metal layer
본 발명은 이.피롬(Erasable programmable Read-Only Memoryh ; 이하 EEPROM이라 칭함)과 이.이.피롬(Electrically Erasable programmable Read-Only Memory ; 이하 EEPROM이라 칭함)의 장점을 모두 가진 플래쉬 EEPROM 및 그 제조방법에 관한 것이며, 특히 반도체기판 상부의 게이트 산화막과 터널 산화막의 두께를 다르게 하여 순수 불휘발성 기억소자 뿐만 아니라, 내부 회로에 플래쉬 EEPROM을 포함시킬 수 있는 피.엘.디(Programmable Legic Dvice ; PLD), 에프.피.지.에이(Field Programmable Gate Array ; EPGA) 등과 같은 소자에 적용될 수 있는 플래쉬 EEPROM 및 그 제조방법에 관한 것이다.The present invention provides a flash EEPROM having both advantages of E. pyrom (Erasable Programmable Read-Only Memoryh) and E. E. pyrom (EEPROM) and its manufacturing method. In particular, the Programmable Legic Dvice (PLD), which can include flash EEPROM in internal circuits as well as pure nonvolatile memory devices by varying the thickness of the gate oxide film and the tunnel oxide film on the semiconductor substrate, The present invention relates to a flash EEPROM that can be applied to a device such as a field programmable gate array (EPGA), and a manufacturing method thereof.
제1도는 종래 기술에 의해 제조된 플레쉬 EEPROM 셀의 단면도이다.1 is a cross-sectional view of a flash EEPROM cell manufactured by the prior art.
소오스전극(6)는 플로팅게이트(3)에 축적된 전자를 소거시키는 역활을 담당하며, 소오스전극(6)에 고전압이 인가될때 소오스전극(6)를 보호하기 위해 DDD 구조(6')(Double Diffusec Drain)로 되어 있다. 게이트산화막(2)은 소오스전극(6)와의 중첩영역(8)에서 터널링(Tunnelling)되 데이타가 소거되도록 100A 정도의 얇은 산화막을 형성되어 있다. 즉, 플로팅 게이트(3)에 축적된 전하가 소오스전극(6)의 고전압에 의해 게이트 산화막(2)과 소오스전극(6)와의 중첩영역(8)을 통하여 터널링되어 소거가 이행된다.The source electrode 6 plays a role of erasing electrons accumulated in the floating gate 3, and the DDD structure 6 ′ (Double) to protect the source electrode 6 when a high voltage is applied to the source electrode 6. Diffusec Drain). The gate oxide film 2 is tunneled in the overlap region 8 with the source electrode 6 to form a thin oxide film of about 100A so as to erase data. That is, the charge accumulated in the floating gate 3 is tunneled through the overlapping region 8 between the gate oxide film 2 and the source electrode 6 by the high voltage of the source electrode 6, and the erase is performed.
한편 "써넣기"(wite 또는 program)는 EPROM에서와 동일한 방법으로 이행된다. 즉, 제어 게이트(5)와 드레인전극(7)에 정(Positive)의 고전압을 인가할때, 드레인전극(7)부근의 채널(9)에서 발생한 고에너지를 가진 열전자(hot elecrton)가 게이트 산화막(2)의 포텐셜 장벽을 뛰어 넘어 플로팅 게이트(3)에 주입되어 상주함으로 "써넣기"가 이행된다.Meanwhile, "write" (wite or program) is implemented in the same way as in EPROM. That is, when positive positive voltage is applied to the control gate 5 and the drain electrode 7, hot elecrton having high energy generated in the channel 9 near the drain electrode 7 is formed by the gate oxide film. "Writing" is performed by jumping over the potential barrier of (2) and being injected into the floating gate 3 and resident.
종래의 플래쉬 EEPROM은 EPROM과 같이 고집적화가 용이하고, EEPROM셀과 같이 자외선없이 전기적으로 소거할 수 있는 장점을 가지고 있으나, 게이트 산화막(2)이 100A 내지 250A 정도로 박막화되므로 개서(rewriting) 횟수가 제한되는 단점을 가진다.Conventional flash EEPROM has the advantage that it is easy to be highly integrated like EPROM and can be electrically erased without UV like EEPROM cell, but the number of rewriting is limited because the gate oxide film 2 is thinned to about 100A to 250A. Has its drawbacks.
즉, 제어 게이트전극(5)과 드레인전극(7)에 고전압을 인가하여 드레인전극(7) 부근 발생하는 고에너지를 가진 열전자(hot electron)를 게이트 산화막(2)의 포텐셜 장벽을 넘게하여 플로팅게이트에 주입시킬 때, 열전자에 의해 박막의 게이트 산화막(2)은 EPROM 셀의 게이트 산화막 두께보다 얇으므로, 열화가 가속되어, 개서횟수가 EPROM의 1/10 내지 1/1000까지 줄어 들게 되어 103내지 105이 되는 단점을 가진다.That is, a high voltage is applied to the control gate electrode 5 and the drain electrode 7 so that hot electrons having high energy generated near the drain electrode 7 are crossed over the potential barrier of the gate oxide film 2 and the floating gate. injection when the gate oxide film 2 of the film by hot electrons is therefore thinner than a gate oxide film thickness of the EPROM cell, the deterioration is accelerated, the rewrite count is picked reduced to 1/10 to 1/1000 of the EPROM 10 to 3 Has the disadvantage of being 10 5 .
따라서, 본 발명은 산화막의 두께를 다르게 하여 게이트 산화막의 열화에 대한 내성을 EPROM에서의 내성수준을 증가시켜, 개서횟수를 증가시키는 플레쉬 EEPROM을 제공하는 것을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a flash EEPROM which increases the number of times of rewriting by increasing the resistance level in the EPROM by varying the thickness of the oxide film.
본 발명의 다른 목적은 두번의 열산화 공정으로 두께가 다른 게이트 사화막과 터널 산화막을 형성하여 소자동작의 신뢰성을 향상시킬 수 있는 플레쉬 EEPROM의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a flash EEPROM capable of improving the reliability of device operation by forming gate oxide films and tunnel oxide films having different thicknesses in two thermal oxidation processes.
따라서, 본 발명에 따른 플레쉬 EEPROM에 의하여, 반도체기판의 일측에 형성되어 있는 소오스전극과, 상기 반도체기판의 타측에 형성되어 있는 드레인전극과, 상기 소오스전극에서 상기 드레인전극 방향으로 일정부분의 반도체기판에 중첩되는 터널 산화막과, 상기 터널 산화막이 형성되지 않은 반도체기판상에 중첩되며, 상기 터널 산화막 보다 두껍게 형성된 게이트 산화막과, 상기 터널 산화막 및 게이트 산화막 상에 형성되어 있는 플루팅 게이트전극과, 상기 플루팅 게이트전극과 중첩되도록 형성되어 있는 제어게이트전극과, 상기 플루팅 게이트전극과 제어 게이트전극의 사이에 개재되어 있는 층간절연막을 구비하는 것을 특징으로 한다.Accordingly, the flash EEPROM according to the present invention includes a source electrode formed on one side of the semiconductor substrate, a drain electrode formed on the other side of the semiconductor substrate, and a portion of the semiconductor substrate in the direction from the source electrode to the drain electrode. A tunnel oxide film superimposed on the tunnel oxide film, a gate oxide film formed on the semiconductor substrate on which the tunnel oxide film is not formed, and thicker than the tunnel oxide film, a fluting gate electrode formed on the tunnel oxide film and the gate oxide film, and the flue. And an interlayer insulating film interposed between the fluting gate electrode and the control gate electrode.
또한 본 발명에 따른 플레쉬 EEPROM의 제조방법은 반도체 기판의 액티브영역상에 게이트 산화막을 형성하는 단계와, 후에 형성될 소오스 전극에 인접된 게이트산화막의 일측을 제거하여 반도체기판을 노출시키는 단계와, 상기 노출된 반도체 기판 상부에 터널 산화막을 형성하는 단계와, 상기 터널 산화막 및 게이트 산화막 상부에 제1폴리실리콘층을 형성하는 단계와, 상기 제1폴리실리콘층 상부에 층간절연막을 형성하는 단계와, 상기 층간절연막 상부에 제2폴리실리콘층을 형성하는 단계와, 상기 제1폴리실리콘층과 제2폴리실리콘층에서 터널 산화막 및 게이트 산화막에 걸쳐지는 게이트전극으로 예정되어 있는 부분이 남도록 패턴닝하여 제1폴리실리콘층 패턴으로된 플로팅 게이트전극과 제2폴리실리콘층 패턴으로된 제어 게이트전극을 형성하는 단계와, 상기 플로팅 게이트전극과 제어 게이트전극 양측의 반도체 기판에 소오스전극과 드레인전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, the method of manufacturing a flash EEPROM according to the present invention comprises the steps of forming a gate oxide film on an active region of a semiconductor substrate, exposing a semiconductor substrate by removing one side of the gate oxide film adjacent to a source electrode to be formed later; Forming a tunnel oxide film over the exposed semiconductor substrate, forming a first polysilicon layer over the tunnel oxide film and the gate oxide film, forming an interlayer insulating film over the first polysilicon layer; Forming a second polysilicon layer on the interlayer insulating layer, and patterning the first polysilicon layer and the second polysilicon layer so as to leave a portion defined as a gate electrode spanning the tunnel oxide film and the gate oxide film; Forming a floating gate electrode having a polysilicon layer pattern and a control gate electrode having a second polysilicon layer pattern And, to the semiconductor substrate of the floating gate electrode and control gate electrode on both sides, it characterized in that it comprises a step of forming a source electrode and a drain electrode.
이하 첨부된 도면으로 본 발명은 더욱 상세하게 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명에 의해 제조된 플레쉬 EEPROM 셀의 단면도를 도시한 것이다.2 shows a cross-sectional view of a flash EEPROM cell fabricated by the present invention.
먼저, 반도체기판(1)상에 서로 일정간격 이격되어 소오스전극(6)과 그레인전극(7)이 형성되어 있으며, 상기 반도체기판(1)상에 서로 두께가 다른 게이트산화막(2')과 터널 산화막(2)이 형성되어 있고, 그 상부에 플로팅 게이트전극(3)과 제어 게이트전극(5)이 서로 중첩되어 형성되어 있으며, 상기 플루팅 게이트전극(3)과 제어 게이트전극(5)의 사이에는 층간절연막(4)이 개재되어 있다.First, the source electrode 6 and the grain electrode 7 are formed on the semiconductor substrate 1 by being spaced apart from each other by a predetermined distance, and the gate oxide film 2 'and the tunnel having different thicknesses on the semiconductor substrate 1 are formed. An oxide film 2 is formed, and a floating gate electrode 3 and a control gate electrode 5 overlap each other, and are formed between the fluting gate electrode 3 and the control gate electrode 5. The interlayer insulating film 4 is interposed.
제1도에 도시된 게이트 산화막(2)의 두께를 제2도에서는 소오스전극(6) 부근과 드레인전극(7) 부근을 서로 다르게 형성한다. 즉, 소오스전극(6) 부근의 게이트 산화막(이하, 터널 산화막(2)이라 함)의 두께를 100A정도로 하고 드에인 전극(7)부근의 게이트 산화막(2')은 EPROM에서 사용되는 정도의 두께인 150A 내지 400A정도로 형성한다. 따라서 "써넣기" 동작으로 인한 게이트 산화막(2')의 열화에 대한 내성이 EPROM에서의 내성 정도로 증가한다.The thickness of the gate oxide film 2 shown in FIG. 1 is different from that of the source electrode 6 and the drain electrode 7 in FIG. That is, the thickness of the gate oxide film (hereinafter referred to as the tunnel oxide film 2) near the source electrode 6 is about 100A, and the gate oxide film 2 'near the drain electrode 7 is about the level used in the EPROM. It is formed to a thickness of about 150A to 400A. Therefore, the resistance to deterioration of the gate oxide film 2 'due to the " write " operation increases to the extent of resistance in the EPROM.
제3a 내지 f도는 본 발명에 의해 제조되는 플래쉬 EEPROM셀의 제조공정도이다.3a to f are manufacturing process diagrams of the flash EEPROM cell manufactured according to the present invention.
제3a도에 있어서는 실리콘 반도체기판(1)의 일측에 LOCOS(Local Oxidation Of Silicon) 공정의 소자분리방법에 의해 형성된 필드 산화막(10)을 형성하고, 반도체기판(1)의 액티브 영역(11)상에 게이트 산화막(2')을 성장시킨다. 이때 상기의 소자분리방법은 LOCOS법이 아닌 SEPOX(Selective polysilicon Oxidation) 등과 같은 다른 방법에 의해서도 가능하며, 상기 필드 산화막(10)의 두께는 "써넣기"와 "소거"시에 사용되는 고전압에 의해 두께가 결정되며, 통상 4000A 내지 10000A 정도가 사용된다. 또한, 상기 게이트 산화막(2')의 두께는 "써넣기"시에 인가되는 고전압에 따라 결정되는데, 150A 내지 400A 정도가 된다.In FIG. 3A, the field oxide film 10 formed by the element isolation method of the LOCOS (Local Oxidation Of Silicon) process is formed on one side of the silicon semiconductor substrate 1, and the active region 11 of the semiconductor substrate 1 is formed. On the gate oxide film 2 '. In this case, the device isolation method may be performed by another method such as Selective Polysilicon Oxidation (SEPOX), and the like, but not by the LOCOS method. Is determined, usually about 4000A to 10000A is used. Further, the thickness of the gate oxide film 2 'is determined depending on the high voltage applied at the time of "writing", which is about 150A to about 400A.
제3b도에 있어서는 상기 게이트산화막(2')에 상에 터널 산화막이 성장될 부분(2")을 노출시키는 감광막 패턴(12)을 형성한 후, 상기 감광막패턴(12)에 의해 노출되어 있는 게이트산화막(2)을 식각한다.In FIG. 3B, a photosensitive film pattern 12 is formed on the gate oxide film 2 'to expose a portion 2 "on which the tunnel oxide film is to be grown, and then the gate exposed by the photosensitive film pattern 12 is formed. The oxide film 2 is etched.
제3c도에 있어서는, 상기 감광막패넌(12)을 제거하고, 식각되어 노출된 반도체기판(1)상에 터널 산화막(2)을 성장시킨다. 이때, 터널 산화막(12)의 성장과 함께 게이트 산화막(2')도 함께 약간 성장함으로, 게이트 산화막(2')의 두께는 최초 성장시 이를 고려하여 목표로 하는 두께 보다 작은 값을 가지도록 한다. 여기서, 터널링에 사용되는 터널 산화막(2)의 두께는 90~110Å 범위내의 값을 가진다.In FIG. 3C, the photoresist film pann 12 is removed, and the tunnel oxide film 2 is grown on the etched and exposed semiconductor substrate 1. At this time, the gate oxide film 2 'also grows slightly with the growth of the tunnel oxide film 12, so that the thickness of the gate oxide film 2' is smaller than the target thickness in consideration of the initial growth. Here, the thickness of the tunnel oxide film 2 used for tunneling has a value within the range of 90 to 110 kPa.
그다음 상기 구조의 전표면에 제1폴리실리콘층(13)을 CVD(Chemical Vapor Deposition)법으로 도포한다.Then, the first polysilicon layer 13 is applied to the entire surface of the structure by CVD (Chemical Vapor Deposition) method.
제3d도에 있어서는, 산화막 또는 산화막-질화막-산화막(Oxide-Nitride-Oxide)의 적층 구조로된 층간절연막(4)을 상기 제1폴리실리콘층(13) 상에 형성한 후, 상기 층간절연막(4) 상부에 제2폴리실리콘층(13')을 형성한다.In FIG. 3D, an interlayer insulating film 4 having a laminated structure of an oxide film or an oxide film-nitride-oxide film is formed on the first polysilicon layer 13, and then the interlayer insulating film ( 4) A second polysilicon layer 13 'is formed on the top.
그후, 상기 제2폴리실리콘층(13')에서 게이트전극으로 예정되어 있는 부부상에 감광막패턴(12)을 형성한다.Thereafter, the photosensitive film pattern 12 is formed on the couple of the second polysilicon layer 13 'which is supposed to be a gate electrode.
제3e도에 있어서는, 상기 감광막패턴(12)에 의해 노출되어 있는 제2폴리실리콘층(13')에서 제1폴리실리콘층(13)까지 순차적으로 식각하여 제2폴리실리콘층(13') 패턴으로된 제어 게이트전극(5)과 제1폴리실리콘층(13) 패턴으로된 플루팅 게이트전극(3)을 형성하고, 상기 감광막패턴(12)을 제거한다.3E, the second polysilicon layer 13 ′ is sequentially etched from the second polysilicon layer 13 ′ to the first polysilicon layer 13 exposed by the photosensitive film pattern 12. The control gate electrode 5 and the fluting gate electrode 3 having the first polysilicon layer 13 pattern are formed, and the photoresist pattern 12 is removed.
그다음 상기 제어 게이트전극(5)과 플루팅 게이트전극(3) 양측의 반도체기판(1)에 불순물을 확산시켜 소오스전극(6)과 드레인전극(7)을 형성한다.Then, impurities are diffused into the semiconductor substrate 1 on both sides of the control gate electrode 5 and the fluting gate electrode 3 to form the source electrode 6 and the drain electrode 7.
제3f도에 있어서, 제3e도에 형성된 EEPROM셀의 전표면에 중간 절연막(14)을 형성한 후, 금속층(15)을 형성시킨 상태를 도시하고 있으며, 제조완료까지의 공정은 일반적인 방법에 따른다.In FIG. 3F, the intermediate insulating film 14 is formed on the entire surface of the EEPROM cell formed in FIG. 3E, and then the metal layer 15 is formed. The process up to the completion of manufacturing is in accordance with a general method. .
제4a 내지 c도는 본 발명의 플래쉬 EEPROM의 동작원리를 나타낸 등가회로도이다.4a to c are equivalent circuit diagrams showing the operation principle of the flash EEPROM of the present invention.
제4a도는 소거시의 각 단자별 인가전압상태를 도시하고 있다.4A shows an applied voltage state for each terminal during erasing.
즉, 소오스전극(6)단에 고전압을 인가하여 플로팅 게이트(3)에 축적된 전하를 끌어내는데, 상기 소오스전극(6)단은 블럭 혹은 섹터 단위로 고전압을 가할 수 있으므로, 플래쉬 소거가 가능하다. 제어 게이트(5)단은 통산 플로팅 상태나 접지 상태가 되어 있으나 소거의 효율을 높이기 위해 음의 전압을 인가하기도 한다.That is, a high voltage is applied to the source electrode 6 end to draw out the charge accumulated in the floating gate 3. The source electrode 6 end may apply a high voltage in units of blocks or sectors, and thus flash erasing is possible. . The control gate 5 stage is normally in a floating state or a ground state, but a negative voltage may be applied to increase the erase efficiency.
제4b도는 "써넣기" 상태를 4c도는 "읽어내기"상태를 나타내는데 EPROM의 일반적인 원리와 같으므로 상세한 설명은 생략하기로 한다.Figure 4b shows the "write" state and Figure 4c shows the "read" state, which is the same as the general principle of the EPROM, so a detailed description thereof will be omitted.
본 발명에 의한 플래쉬 EEPROM 셀은 소오스전극 부근의 "소거"시에 사용되는 터널 산화막을 얇은 박막을 하고, "써넣기"시에 사용되는 게이트 산화막을 두껍게 하여 열전자에 의한 열화를 지연시켜, 개서(rewriting) 횟수를 증가시킬 수 있는 효과를 가지므로, 개서횟수의 부족으로 사용할 수 없었던 응용분야까지 확대적용이 가능하게 되었다.In the flash EEPROM cell according to the present invention, a thin thin tunnel oxide film used at the time of "erasing" near the source electrode is made thick, and a gate oxide film used at the time of "writing" is thickened to delay deterioration due to hot electrons, thereby rewriting. As it has the effect of increasing the number of times, it is possible to extend the application to applications that could not be used due to the lack of rehabilitation times.
또한, 본 발명은 EPROM에도 적용이 가능하다. 즉, 소오스전극 부근의 게이트 산화막의 두께를 얇게 하고 , 드레인 전극 부근의 게이트 산화막의 두께를 두껍게 구성하여 자외선을 이용하여 정보를 소거할시 시간을 단축시킬 수 있는 효과를 가질 수 있다.The present invention is also applicable to EPROM. That is, the thickness of the gate oxide film in the vicinity of the source electrode may be reduced, and the thickness of the gate oxide film in the vicinity of the drain electrode may be increased to reduce the time when erasing information using ultraviolet rays.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019910022064A KR950006232B1 (en) | 1991-12-03 | 1991-12-03 | Flash eeprom cell and manufacturing method thereof |
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| KR1019910022064A KR950006232B1 (en) | 1991-12-03 | 1991-12-03 | Flash eeprom cell and manufacturing method thereof |
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