JPH06104451A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a title device which can execute write and erase of information without using step-up circuits and improves a tunnel oxide film. CONSTITUTION:This device has a gate electrode structure buried in a P-type silicon substrate 11. A tunnel oxide film 16 is formed on the inner wall of a groove 15 formed in the surface of the P-type silicon substrate 11. Source and drain regions 18, 17 are separated by the groove 15 and electrically connected by a channel layer formed in the surface of the silicon substrate contacting the side wall of this groove 15. A floating gate electrode 19 is formed on the surface of the tunnel oxide film 16. A control gate electrode 20 is formed on the floating gate electrode 19 via an insulation layer. Write and erase actions are executed by current flowing between the source or drain region in a vicinity of the open edge of the groove 15 and the floating gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device capable of electrically writing and erasing information.

[0002]

2. Description of the Related Art A nonvolatile semiconductor device is a device in which information is written by injecting electrons into a floating gate surrounded by an insulator, and stored information can be retained for a long period of time without being supplied with electric energy from the outside. Is. Recently, as this type of semiconductor memory device, a nonvolatile semiconductor memory (or flash type nonvolatile memory) device having a function of electrically erasing written information collectively has been used in various electronic circuit systems. It's coming.

A conventional non-volatile semiconductor memory device, for example, as shown in FIG. 4, has N ⁺ conductivity type source and drain regions 34 formed on the surface of a P type silicon substrate 31,
33, and a floating gate electrode 38 formed on the channel region between the source / drain regions with a tunnel oxide film 36 interposed. The P-type conductive layer 32 below the region 33 is formed to improve the writing efficiency, and further the source region 3 is formed.
The N ⁻ -type conductive layer 35 under 4 is formed to suppress the band-to-band tunnel current generated in the erase operation.

Generally, in the information read operation, in the nonvolatile semiconductor memory device, when a large number of electrons are injected into the floating gate electrode 38, the channel region on the surface of the P-type silicon substrate 31 is not inverted, so that the N ⁺ source region is not inverted. No current flows between the region 33 and the N ⁺ drain region 34, and the state is turned off. On the other hand, when electrons are not injected into the floating gate electrode 38, the channel region is easily inverted, so that a current flows between the source and the drain to turn on.

Electron injection (writing) to the floating gate electrode
In operation, a positive reverse bias voltage (about 5 V) is applied between the drain region 33 and the substrate 31, and the control gate electrode 3
A high voltage is applied to 9 so that the floating gate voltage becomes about 10V. As a result, the electrons flowing out of the source region 34 pass through the tunnel oxide film 36 and the floating gate electrode 38.
Information is written.

On the other hand, in the electron extracting (erasing) operation, when a positive voltage is applied to the source region 34, a tunnel current flows to the source and drain regions, electrons in the floating gate electrode are extracted to the source region 34, and information is written. Erased.

[0007]

In the above flash type nonvolatile semiconductor device, the tunnel oxide film has a very thin film thickness. For example, in a flash type nonvolatile memory device of 1 Mbit or more, the silicon oxide film of 10 nm or less is used. (SiO ₂ ) is used. The characteristics of the oxide film are important factors for determining the number of times of rewriting of the nonvolatile memory device and the information storage retention time. When information writing and erasing operations are performed, the tunnel oxide film receives stress, and this stress increases in proportion to the number of times information is rewritten. The film thickness of the tunnel oxide film and the information retention period have a mutual relationship, and when the stress of the tunnel oxide film increases, the information retention property deteriorates and the number of effective rewrites decreases. Generally, when a tunnel oxide film having a large thickness (for example, 20 nm) is used, the electric field applied between the oxide films is reduced, the number of effective rewrites can be increased, and the data retention period can be extended. However,
Since the erase operation is performed by using the tunnel current, a high voltage must be applied between the source region and the floating gate 21 region. Therefore, it is necessary to incorporate a booster circuit occupying a large area into the nonvolatile memory device. Although it is necessary to thin the tunnel oxide film in order to reduce the information erasing voltage, there are problems that the tunnel oxide film easily causes dielectric breakdown and the leakage current increases when the tunnel oxide film is thinned.

An object of the present invention is to provide a non-volatile semiconductor memory device that does not require a booster circuit for erasing information.

Another object of the present invention is to provide a semiconductor nonvolatile semiconductor memory device capable of improving the reliability of the tunnel oxide film.

[0010]

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention is a semiconductor substrate of the first conductivity type having a groove on its surface, and a sidewall of the groove via the groove. Formed on the surface of the semiconductor substrate so as to be in contact with the first and second regions of the second conductivity type, the first insulating film formed on the surface of the groove, and formed on the surface of the first insulating film in the groove. A first conductive layer formed on the surface of the first conductive layer, a second insulating layer formed on the surface of the first conductive layer, and a second conductive layer formed on the surface of the second insulating layer. It is characterized by things.

The first conductivity type semiconductor substrate is a P type silicon substrate, and the first and second regions of the second conductivity type are N type impurity diffusion regions.

In the above nonvolatile semiconductor memory device, electrons are injected at the time of writing data and emitted at the time of erasing data through the first insulating layer around the opening end of the groove.

In the above nonvolatile semiconductor memory device, the first insulator layer and the second insulator layer are silicon oxide film layers, and the first and second conductor layers are polysilicon layers. In the above nonvolatile semiconductor memory device, the first insulator layer is 1
It has a film thickness of 0 to 20 nm.

The flash type nonvolatile semiconductor memory device of the present invention comprises a first conductivity type silicon substrate having a groove on the surface, and a first conductive type silicon substrate formed on the surface of the silicon substrate through the groove and in contact with the sidewall of the groove. A two-conductivity type drain and source region, a first insulating film formed on the sidewall surface of the groove, a first conductor layer formed on the surface of the first insulating film in the groove, and a first conductive film. It is characterized in that it has a second insulator layer formed on the surface of the body layer and a second conductor layer formed on the surface of the second insulator layer.

In the above flash type nonvolatile semiconductor memory device, electrons are injected during a data write operation and emitted during an erase operation through the first insulating layer around the opening end of the groove.

[0016]

In the nonvolatile semiconductor memory device according to the present invention, a groove is formed on the surface of the semiconductor substrate, and the tunnel oxide film, the floating gate electrode, the control gate electrode formed in the groove, and the outer wall of the groove are adjacent to each other. Since the source and drain regions are formed, electrons can be floating gated by locally increasing the electric field between the source and drain regions and the floating gate electrode near the opening end of the groove. Therefore, writing and erasing operations can be performed at a low voltage.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a flash type nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a flash type memory device according to the present invention.

In FIG. 1, a nonvolatile semiconductor memory device 1
Reference numeral 0 has a P-type silicon semiconductor substrate 11, and a field oxide film 12 made of thick silicon oxide that defines a memory cell region on the surface of this substrate. For example, a concave groove 15 is formed on the surface of the silicon substrate 11 in the memory cell region. An N type drain region 17 and a source region 18 are formed on the surface of the substrate 11 between the side wall of the groove 15 and the field oxide film 12. Conductive layer 13a extending on the surfaces of drain region 17 and field oxide film 12 and conductive layer 13b extending on the surfaces of source region 18 and field oxide film 12 are formed. Via the opening of the groove,
A thin gate oxide film layer 16 is formed on the surfaces of conductive layers 13a and 13b from the inner wall of the groove. Oxide layer 1 in the groove
6 is formed of a silicon oxide layer having a film thickness of 10 to 15 nm, for example, and is called a tunnel oxide film. The floating gate electrode 19 is formed on the gate oxide film 16. Next, a thermally grown oxide film is formed on the floating gate electrode, and then the gate electrode is formed. An intermediate insulating film 2 is formed on the front surface of the structure.
2 is formed. Electrodes 23a and 23b are formed for electrically connecting to conductive layers 13a and 13b, respectively, through intermediate insulating film 22. In the nonvolatile semiconductor memory device according to the present invention, the tunnel current is mainly N
It is injected from the mold diffusion region into the floating gate 19 through the tunnel oxide film 16 near the opening end of the concave groove.

Information writing and erasing operations of the flash type nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. 2 (a) and 2 (b).

To perform the write operation, FIG.
As shown in (a), a ground potential is applied to the control gate electrode 21, and a positive pulse potential (+ 5V) is applied to the source 18 and the drain 17 by the pulse power supply PG. As a result, the electric field density at the opening end of the groove region increases, so that tunnel current is easily generated. Therefore, electrons can be injected into the floating gate 19 without raising the power supply potential.

In order to perform the erase operation, as shown in FIG. 2B, the source 18, the drain 17, and the substrate 11 are formed.
To the control gate 21, and a negative pulse potential (-5 V) is applied to the control gate 21 by the pulse power supply PG. As a result, the electrons accumulated in the floating gate 19 become a Fowler-Nordheim current and are extracted to the source 18 side.

In the nonvolatile semiconductor memory device according to the present invention, the tunnel oxide film 16 has a thickness of 10 to 15 nm and the injection voltage is low, so that an induced current due to a high electric field stress is not generated.

Next, a method of manufacturing the flash type nonvolatile semiconductor memory device shown in FIG. 1 will be described with reference to FIGS.
This will be described with reference to the process chart of (e).

In FIG. 3A, first, a semiconductor substrate,
For example, a P-type silicon substrate 11 having a non-resistance of 5 to 7 Ω · cm and a plane orientation (100) is prepared. Silicon substrate 11 for forming active regions or memory cell regions
A field oxide film 12 is formed on the surface by using a known local oxidation technique. Then, a polysilicon layer 13 having a thickness of 0.1 to 0.3 μm is formed on the entire surface including the surface of the memory cell region. This treatment is performed by a chemical vapor deposition (CVD) method in which silane (SiH ₄ ) is thermally decomposed. After that, N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the polysilicon layer 13. At this time, the ion implantation conditions are an acceleration energy of about 20 to 50 keV and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ ions / c.
m ² .

After that, as shown in FIG. 3B, a photoresist layer having a thickness of 0.5 to 1 μm is formed on the entire surface of the polysilicon layer 13, and then the photoresist layer is selectively patterned to form the mask layer 14. Form. The mask layer 14 is formed so as to expose the surface of the silicon substrate in the vicinity of the open end of the groove 15. Using the mask layer 14 as an etching mask, the polysilicon layer 13 is selectively removed by a reactive ion etching (RIE) method using SiO ₂ gas or the like, and subsequently, a silicon substrate is anisotropically etched. 11 is removed and the depth is 0.2-0.5μ
The groove 15 of m is formed.

Next, as shown in FIG. 3C, after removing the mask layer 14, a heat treatment is performed in a nitrogen gas atmosphere at 900 ° C., for example. This heat treatment process is performed on the polysilicon film 1
A gentle slope is formed at the end of 3. Further, by this step, the N-type impurity doped in the polysilicon film 13 is diffused into the silicon substrate 11 immediately thereunder to form the N ⁺ source region 18 and the drain region 17. 900 ° C
The heat treatment time is usually 30 to 60 minutes. This thermal diffusion process is determined by the impurity concentration of the silicon substrate, the depths of the source and drain regions 18, 17 and the N-type impurity concentration in the polysilicon film 13. Next, the structure is heat-treated in a dry oxygen gas atmosphere to obtain a film thickness of 10
~ 15nm thermally grown silicon oxide film (tunnel oxide film)
16 is formed on the inner wall surface of the groove 15. In this step, since the silicon oxide film 16 on the polysilicon film 16 is doped with N-type impurities, it is formed to have a thickness of about 1.5 to 2 times the thickness of the tunnel oxide film 16.

Next, as shown in FIG. 3D, about 200 nm of polysilicon is deposited on the entire surface of the silicon substrate including the tunnel oxide film 16 in the trench 15 by a CVD method, and then a polysilicon layer is formed by a diffusion method. The phosphorus concentration of 19 is 10 ²⁰
Phosphorus diffusion is performed to the order of cm ^-3 . As a result, the polysilicon layer 19 is converted into a conductive layer.

Next, as shown in FIG. 3 (e), a normal CV is used.
ONO (Oxide-Nitride-Oxid) is formed on the surface of the polysilicon layer 19 by the D method and the thermal oxidation process.
e) Form the film 20. Subsequently, a conductive polysilicon layer 21 is formed on the surface of the ONO 20 layer. The polysilicon layers 19 and 21 and the ONO layer 20 are selectively removed by a photolithography process and an etching process to form the floating gate electrode 19 and the control gate electrode 21.

Next, an intermediate insulating film layer is formed on the entire surface of the structure. Then, the intermediate insulating film and the silicon oxide film 16
Are selectively removed to form a contact hole, and the surface of the polysilicon conductive layer 13 is exposed. Finally, a metal material such as aluminum having a thickness of about 1 μm is vapor-deposited on the entire surface of the substrate and then patterned to form an electrode 23 in ohmic contact with the conductive layer 13.

As described above, the nonvolatile semiconductor memory device having the gate structure formed in the concave groove portion according to the present invention shown in FIG. 1 is formed.

[0032]

As described above, since the nonvolatile semiconductor memory device according to the present invention has a buried type gate electrode structure, a tunnel between the floating gate electrode near the end of the opening of the groove and the source or drain is formed. A high electric field can be locally generated in the oxide film. Therefore, the electron injection and electron emission operations for writing and erasing data can be executed at a low voltage, and the booster circuit can be eliminated. Therefore, it becomes possible to operate the nonvolatile semiconductor memory device with one power supply.

Further, the nonvolatile semiconductor memory device according to the present invention can perform the writing and erasing operations at a low voltage by using the tunnel oxide film having the same thickness as in the prior art. Therefore, stress deterioration of the tunnel oxide film is suppressed, and the number of times data is written and erased repeatedly and the data retention characteristic of the nonvolatile semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2A is a diagram for explaining an information writing operation of the nonvolatile semiconductor memory device according to the present invention, and FIG. 2B is a diagram for explaining an information erasing operation of the nonvolatile semiconductor memory device according to the present invention.

FIG. 3 is a diagram showing a manufacturing process of a flash nonvolatile semiconductor memory device according to the present invention.

FIG. 4 is a sectional view of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 10 Nonvolatile Semiconductor Memory Device 11 P-Type Silicon Substrate 12 Field Oxide Film 13a, 13b Conductor Layer 15 Groove 16 Tunnel Oxide Film 17 Drain Region 18 Source Region 19 Floating Gate 21 Control Gate Electrode 22 Intermediate Insulating Film 23a, 23b Electrode

Claims (7)

[Claims] 1. A semiconductor substrate of a first conductivity type having a groove on its surface; a pair of first and second conductivity types formed on the surface of the semiconductor substrate so as to contact the sidewall of the groove through the groove. A second region; a first insulating film formed on the surface of the groove; a first conductive layer formed on the surface of the first insulating film in the groove; and a first conductive layer A non-volatile semiconductor memory device comprising: a second insulator layer formed on the surface; and a second conductor layer formed on the surface of the second insulator layer. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first conductive type semiconductor substrate is a P type silicon substrate, and the second conductive type first and second regions are N type impurity diffusion regions. A non-volatile semiconductor memory device characterized by: 3. The non-volatile semiconductor memory device according to claim 2, wherein electrons are injected during data writing and electrons are erased during data erasing via the first insulating layer around the opening end of the groove. And a nonvolatile semiconductor memory device. 4. The non-volatile semiconductor memory device according to claim 1, wherein the first insulator layer and the second insulator layer are silicon oxide film layers, and the first and second conductor layers are polysilicon layers. A non-volatile semiconductor memory device characterized by: 5. The nonvolatile semiconductor memory device according to claim 2, wherein the first insulator layer has a film thickness of 10 to 20 nm. 6. A first-conductivity-type silicon substrate having a groove on its surface; and a second-conductivity-type drain and source regions formed on the surface of the silicon substrate so as to contact the sidewall of the groove through the groove. ; First formed on the sidewall surface of the groove
An insulating film; a first conductor layer formed on the surface of the first insulator film in the groove; a second insulator layer formed on the surface of the first conductor layer; A second non-volatile semiconductor memory device having a second conductor layer formed on the surface of the second insulator layer. 7. The flash non-volatile semiconductor memory device according to claim 6, wherein electrons are injected during a data write operation and emitted during an erase operation through the first insulating layer around the opening end of the groove. A flash type nonvolatile semiconductor memory device characterized by being performed.