JP3141492B2 - Method for manufacturing nonvolatile memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile memory element, and more particularly to a method for improving the memory retention characteristics of a nonvolatile memory element.

[0002]

2. Description of the Related Art FIGS. 3 and 4 are cross-sectional views showing a main part manufacturing process of a nonvolatile memory element according to a conventional method.

In order to manufacture a nonvolatile memory element by a conventional method, first, a channel stopper and a field oxide film (not shown) for element isolation are removed from a P-type silicon substrate (not shown). Next, after removing the thin oxide film in the nonvolatile memory element formation region, an impurity is ion-implanted into a channel region (not shown) for threshold control.

Next, the surface of the P-type silicon substrate is thermally oxidized to form a first gate insulating film (SiO ₂ ) of the nonvolatile memory element.
(Not shown). Next, the entire upper surface of the P-type silicon substrate is formed by a CVD (chemical vapor deposition) method as shown in FIG.
After the polysilicon film 7 is formed as shown in FIG. 7, phosphorus (phosphorus: P) is ion-implanted. Protruding defect asperities 6 occur on the surface of the polysilicon film 7.

Next, photolithography and RIE
When the polysilicon film 7 in the non-volatile memory element formation region is left by the (reactive ion etching) and the polysilicon film 7 in the other region is removed, the floating gate 7 is removed.
a is formed.

Next, as shown in FIG. 3B, the entire surface of the P-type silicon substrate is thermally oxidized to form a first silicon oxide film (SiO ₂ ) 9 having a thickness of 5 nm or more (for example, 12 nm). Thereafter, as shown in FIG. 3C, Si ₃ N ₄ is formed as the insulating film 10 by the CVD method. Next, as shown in FIG. 3D, when the insulating film (Si ₃ N ₄ ) 10 is thermally oxidized,
A second silicon oxide film (SiO ₂ ) 11 is formed on the surface of the nitride film (Si ₃ N ₄ ) 10 to a thickness of about 3 nm.

Next, the polysilicon film is formed by P
(P) after being formed on the entire upper surface of the mold silicon substrate
Is ion-implanted. Next, the polysilicon film, the second silicon oxide film (SiO ₂ ) 11, and the insulating film (S) in the nonvolatile memory element forming region are formed by photolithography and RIE.
i ₃ N ₄₎ 10, leaving the first silicon oxide film (SiO ₂₎ 9, the polysilicon film of the other region, the second silicon oxide film (SiO ₂₎ 11, an insulating film (Si ₃ N ₄₎ 10 Then, when the first silicon oxide film (SiO ₂ ) 9 is removed, as shown in FIG. 4, the control gate 8a and the first silicon oxide film (SiO ₂ ) 9a / insulating film (Si ₃ N ₄ ) 10a /
A second gate insulating film (ONO film) 12 composed of a second silicon oxide film (SiO ₂ ) 11a is formed. Next, arsenic is ion-implanted into the source region and the drain region.

Next, an SOG film (Spin) is used as an interlayer insulating film.
After forming On Glass) (the following process is not shown),
A contact hole is opened in the drain electrode portion, and an aluminum film is formed by an evaporation method. Next, the aluminum film is removed by photolithography and RIE to form a drain electrode. Next, a P-SiN film is formed as a passivation film over the entire surface of the P-type silicon substrate by a plasma CVD method. Through the above steps, a nonvolatile memory element can be manufactured.

[0009]

FIG. 8 is a plan view of a non-volatile memory element. This non-volatile memory element captures electrons in a floating gate 7a and shows a state in which a threshold voltage of a MOS transistor becomes high. The state where the threshold voltage is low in a state where electrons are emitted and electrons are lost in the floating gate 7a corresponds to Low.

In writing electrons into the floating gate 7a, hot electrons generated near the drain region 4 by applying a high voltage to the drain region 4 are injected into the floating gate 7a by applying a positive voltage to the control gate 8a. It is done by doing.

In this nonvolatile memory element, in the step shown in FIG. 3A, a protruding defect asperity 6 occurs on the surface of the floating gate 7a, and furthermore, FIG.
Is oxidized on the surface of the floating gate 7a in the process shown in FIG.

However, this asperity defect 6
Performs the same function as a lightning rod when electrons are captured in the floating gate 7a, and the electrons flow through the second gate insulating film 12 to the control gate 8a.
ler Nordheim Tunnel current or Pool Frenkle
This easily causes a tunnel current to flow, deteriorating the memory retention characteristics of the nonvolatile memory element, which is a problem.

However, the first defect thicker than the second silicon oxide film (SiO ₂ ) is formed on the protrusion defect asperity 6.
In the conventional method of forming the silicon oxide film (SiO ₂ ) 9a, the Fowler
The Nordheim tunnel current acts greatly,
Even if the thickness of the silicon oxide film (SiO ₂ ) 9a is increased,
The effect of preventing the Fowler Nordheim tunnel current is reduced, and the Fowler Nordheim tunnel current flows even at a low voltage.

[0014] As a result, the insulating film (Si ₃ N ₄₎ electrons enters into 10a, into the insulating film (Si ₃ N ₄₎ as Poole Frenkle tunneling current in 10a second silicon oxide film (SiO ₂₎ 11a The electrons pass. However, as the thickness of the first silicon oxide film (SiO ₂ ) 9a is increased, the second silicon oxide film (SiO ₂ ) is equivalently equivalent to that.
The film thickness of 11a is reduced to about 3 nm. Accordingly, the second silicon oxide film (SiO ₂ ) 11a is thinner and thus the second silicon oxide film (SiO ₂ )
₂ ) Electrons easily flow to the control gate after passing through 11a. Therefore, there is a problem that the storage retention characteristics of the nonvolatile storage element deteriorate.

Therefore, the present invention provides a method for forming a second gate insulating film of a nonvolatile nonvolatile memory element into a first silicon oxide film (SiO ₂ ) / insulating film (Si ₃ N ₄ ) / first silicon oxide film having a predetermined thickness . Second silicon oxide film (SiO ₂ ) thicker than
It is another object of the present invention to provide a method of manufacturing a nonvolatile memory element in which the storage gate characteristics are improved by using a polysilicon film into which boron is introduced as a control gate.

[0016]

According to the present invention, there is provided a nonvolatile memory element having a first gate insulating film / floating gate / second gate insulating film / control gate on a P-type silicon substrate. The method is P-type
Forming a first gate insulating film on a silicon substrate;
On this first gate insulating film, a first
After forming a polysilicon film, the first polysilicon film
Floating gate by patterning
Forming and a predetermined process on the floating gate.
Forming a first silicon oxide film having a thickness of
An insulating film is formed on the oxide film, and a first film is formed on the insulating film.
Form a second silicon oxide film thicker than the recon oxide film
By forming the first silicon oxide film /
Forming a second gate insulating film composed of an insulating film / a thick second silicon oxide film, and forming a control gate composed of a second polysilicon film doped with boron on the second gate insulating film; It is solved by the manufacturing method of the nonvolatile memory device characterized by comprising the steps of.

[0017]

[0018]

FIG. 5 is an energy band structure diagram of the nonvolatile memory element according to the present invention in a state where electrons are held in the floating gate. This nonvolatile memory element is composed of a floating gate made of polysilicon into which phosphorus is introduced, a first silicon oxide film (SiO ₂ ) having a predetermined thickness, and Si ₃
Consisting N ₄ dielectric film / thick second silicon oxide film (Si
It is composed of a control gate made of polysilicon into which O ₂ ) / boron is introduced.

According to the present invention, as shown in FIG. 1 ( d ), the first silicon oxide film (SiO ₂ ) 9 is
Since the film thickness is smaller than the film (SiO ₂ ) 11 and is formed on the surface of the floating gate 7 a having the asperity 6, the Fowler Nordheim tunnel current is larger in the first silicon oxide film (SiO ₂ ) 9 than in the prior art. easily flow. Therefore, the first silicon oxide film (SiO
₂ ) 9 has characteristics almost similar to resistance.

As a result, as shown in FIG. 5, the electrons captured by the floating gate are converted into the first silicon oxide film (S
iO ₂₎ 9a through enters the insulating film (Si ₃ N ₄₎ 10a, as in the inside of the insulating film (Si ₃ N ₄₎ 10a shown in FIG. 5, between the trap level ET and the conduction band level EC Flows as a Pool Frenkle tunnel current while repeating the exchange with the second silicon oxide film (SiO ₂ ) 11.
Enter a.

However, the second silicon oxide film (SiO ₂ ) 11a according to the present invention is formed to be thicker than the first silicon oxide film , and the insulating film 10a has a better film quality.
The second silicon oxide film (S
The Fowler Nordheim tunnel current in the iO ₂ ) 11a can be reduced.

As a result, the second silicon oxide film is formed on the floating gate 7a having an asperity 6 and poor film quality.
The _second silicon oxide film (SiO ₂ ) having a larger thickness is formed on the insulating film 10 a having a better film quality than the conventional method of forming the first silicon oxide film (SiO ₂ ) 9 a having a greater thickness than the film (SiO ₂ ) 11 a. ₂ ) The present invention forming 11a can improve the storage retention characteristics of the nonvolatile memory element.

FIG. 6 is an energy band structure diagram of a conventional nonvolatile memory element, and FIG. 6A is an energy band structure diagram in a state where the floating gate does not hold electrons. (B) is an energy band structure diagram in a state where the floating gate holds electrons. This non-volatile memory element has a silicon substrate / a first gate insulating film made of SiO ₂ / a floating gate made of phosphorus-doped polysilicon / SiO 2
_And a control gate made of polysilicon into which boron is introduced.

As shown in FIG. 6B, the potential in the floating gate and at the interface between the floating gate and the first gate insulating film and the second gate insulating film is reduced by the amount of electrons captured and held by the floating gate. Energy increases.

FIG. 7 is an energy band structure diagram of the nonvolatile memory element according to the present invention, and FIG. 7A is an energy band structure in a state where the floating gate does not hold electrons. (B) is an energy band structure diagram in a state where the floating gate holds electrons. The nonvolatile memory element, a floating gate / SiO ₂ composed of polysilicon was introduced first gate insulating film / phosphorus made of a silicon substrate / SiO ₂
And a control gate made of polysilicon doped with boron.

As shown in FIG. 7A, boron is implanted into the polysilicon constituting the control gate to make the control gate P-type, so that the polysilicon is formed from the N-type polysilicon shown in FIG. 6A. Since the potential energy is about 1 eV higher than that of the conventional control gate, the potential energy at the interface between the control gate and the second gate insulating film is about 1 eV higher than that of the conventional control gate.

Therefore, as shown in FIG. 7 (b), the potential energy of the second gate insulating film is increased by about 1 eV at the interface with the control gate compared with the prior art. Of the Fowler-Nordheim tunnel current from the floating gate to the control gate through the second gate insulating film becomes smaller than before. As a result, the storage retention characteristics of the nonvolatile storage element can be improved.

[0028]

An embodiment according to the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show an embodiment according to the present invention, and are cross-sectional views in a main step of manufacturing a nonvolatile memory element.

To manufacture the nonvolatile memory element according to the present invention, first, a channel stopper and a field oxide film (not shown) for element isolation are formed in a P-type silicon substrate (not shown). Then, the thin oxide film in the nonvolatile memory element formation region is removed. Next, an impurity is ion-implanted into a channel region (not shown) for controlling a threshold value.

Next, the surface of the P-type silicon substrate is thermally oxidized to form a first gate insulating film (SiO ₂ ) of the nonvolatile memory element.
To form Next, as shown in FIG. 1A, a polysilicon film 7 is formed on the entire upper surface of the P-type silicon substrate by the CVD method.
Is formed, phosphorus (phosphorus: P) is ion-implanted. Asperities 6 of projection defects are generated on the surface of the polysilicon film 7.

Next, photolithography and RIE
By removing the polysilicon film in the non-volatile memory element formation region and removing the polysilicon film in the other region, the floating gate 7a is formed.

Next, as shown in FIG. 1 (b), and lightly thermally oxidizing the surface of the floating gate 7a, the SiO ₂ 3
A first silicon oxide film (SiO ₂ ) 9 is formed to a thickness of not more than nm (for example, 3 nm). Next, as shown in FIG. 1C, a Si ₃ N ₄ film is formed as an insulating film 10 over the entire surface of the P-type silicon substrate by a CVD method. At this time, the surface of the insulating film (Si ₃ N ₄ ) 10 becomes substantially flat. Next, an SiO ₂ film as a second silicon oxide film (SiO ₂ ) 11 is formed on the surface of the insulating film (Si ₃ N ₄ ) 10 by a low pressure CVD method.
It is formed to a thickness of at least nm (for example, 12 nm). At this time, the first silicon oxide film (SiO ₂ ) 9 has a thickness of 3 nm.
If the second silicon oxide film (SiO ₂ ) 11 was thinner than 5 nm, the effect of the holding characteristics of the nonvolatile memory element was not sufficient.

Next, after a polysilicon film is formed on the entire upper surface of the P-type silicon substrate by a low pressure CVD method, boron ions are implanted into the polysilicon film. Next, by photolithography and RIE, the polysilicon film and the second silicon oxide film (Si
O ₂₎ 11, an insulating film (Si ₃ N ₄₎ 10, leaving the first silicon oxide film (SiO ₂₎ 9, other regions of the polysilicon film, the second silicon oxide film (SiO ₂₎ 11, an insulating film (Si ₃ N ₄ ) 10, first silicon oxide film (SiO ₂ ) 9
Is removed, as shown in FIG. 2, the control gate (polysilicon) 8a and the first silicon oxide film (Si)
O ₂₎ 9a / insulating film (Si ₃ N ₄₎ 10a / second silicon oxide film (SiO ₂₎ a second gate insulating film composed of 9a (ONO film) 12 is formed.

Next, arsenic (As) is ion-implanted into the source region and the drain region (not shown in the following steps).
Next, after forming an SOG (Spin On Glass) film as an interlayer insulating film on the entire upper surface of the P-type silicon substrate, a contact hole is opened in the drain electrode portion. Next, after an aluminum film is formed on the P-type silicon substrate by the CVD method, the aluminum film in the non-volatile memory element formation region is left by using photolithography and RIE, and the aluminum film in the other region is removed. Next, a P-SiN film is formed as a passivation film over the entire surface above the P-type silicon substrate by a plasma CVD method.

FIG. 8 is a plan view (excluding the passivation film and the interlayer insulating film) of the nonvolatile memory element manufactured through the above steps. Floating gate 7a, control gate 8a, drain electrode 16, and aluminum film 14 are formed. FIG. 9 shows YY ′ in FIG.
It is a sectional view in a straight line direction. As shown in FIG. 9, a source region 3, a drain region 4, and a channel region 2 are formed in a P-type silicon substrate 1, respectively. On the channel region 2, a first gate insulating film (SiO ₂ film) 5 / floating gate (polysilicon) 7a / second gate insulating film (ONO film) 12 / control gate (polysilicon) 8a are formed, A drain electrode 16 is formed on the drain region 4, and an interlayer insulating film (SOG film) 13, an aluminum film 14, and a passivation film (P-SiN film) 15 are formed above the P-type silicon substrate. Configure the element.

[0037]

As described above, according to the present invention,
The first silicon predetermined thickness on the floating gate oxide film / insulating film / film thickness thick second silicon oxide film second
A gate insulating film is formed, and a button is formed on the second gate insulating film.
A control made of a second polysilicon film into which Ron has been introduced.
Gate is formed, and the floating gate is
Control gate potential energy
You.

With this structure, the phosphorus-introduced poly
Compared to forming a control gate with a silicon film
In addition, at the interface between the control gate and the second gate insulating film,
Potential energy can be increased by about 1 eV
You. As a result, the current due to Fowler Nordheim tunneling from the floating gate to the control gate can be reduced , and the memory retention characteristics can be further improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first half process of manufacturing a nonvolatile memory element according to an embodiment.

FIG. 2 is a sectional view showing a latter half of a process for manufacturing a nonvolatile memory element according to an embodiment.

FIG. 3 is a sectional view of a first half of a process of manufacturing a nonvolatile memory element according to a conventional example.

FIG. 4 is a sectional view showing a latter half of a process of manufacturing a nonvolatile memory element according to a conventional example.

FIG. 5 is an energy band structure diagram of a second gate insulating film of the nonvolatile memory element according to the present invention.

FIG. 6 is an energy band structure diagram of a conventional nonvolatile memory element.

FIG. 7 is an energy band structure diagram of a nonvolatile memory element according to the present invention.

FIG. 8 is a plan view of a nonvolatile memory element.

FIG. 9 is a sectional view of a nonvolatile memory element.

[Description of Signs] 1 P-type silicon substrate 2 Channel region 3 Source region 4 Drain region 5 First gate insulating film (SiO ₂ ) 6 Asperity 7 Polysilicon film 7a Floating gate (polysilicon) 8a Control gate (polysilicon) 9 , 9a first silicon oxide film (SiO ₂ ) 10, 10a insulating film (Si ₃ N ₄ ) 11, 11a second silicon oxide film (SiO ₂ ) 12 second gate insulating film (ONO film) 13 interlayer insulating film (SOG) Film) 14 aluminum film 15 passivation film (P-SiN) 16 drain electrode EC conduction band level EV valence band level EF Fermi level ET trap level

Continuation of the front page (56) References JP-A-3-71674 (JP, A) JP-A-3-94473 (JP, A) JP-A-2-122570 (JP, A) JP-A-63-179577 (JP) JP-A-62-24673 (JP, A) JP-A-59-149061 (JP, A) JP-A-57-72333 (JP, A) JP-A-50-9387 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] To 1. A P-type silicon substrate, a manufacturing method of a nonvolatile memory element having a first gate insulating film / the floating gate / second gate insulating film / the control gate, the P-type silicon substrate first 1 Form a gate insulating film
A first step of introducing an N-type impurity on the first gate insulating film;
After forming a polysilicon film, the first polysilicon film
Patterning the floating gate.
Forming a first silicon layer having a predetermined thickness on the floating gate.
Forming an oxide film and insulating the first silicon oxide film
Forming a film, and forming the first silicon oxide film on the insulating film;
Forming a second silicon oxide film thicker than
More, the predetermined thickness of the first silicon oxide film / insulating film /
Forming a step of forming the second gate insulating film composed of a thick second silicon oxide film of said thickness, said control gate made of the second polysilicon film obtained by introducing boron on said second gate insulating film method of manufacturing a nonvolatile memory element which comprises a step of.