JP3141520B2 - Method for manufacturing nonvolatile memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory element having a first gate insulating film / floating gate / second gate insulating film / control gate, and more particularly to improving the memory retention characteristics of the nonvolatile memory element. It is about the method of making it.

[0002]

2. Description of the Related Art FIGS. 4 to 6 are cross-sectional views of a conventional method for manufacturing a nonvolatile memory element.

A conventional nonvolatile memory element is first shown in FIG.
As shown in FIG. 1A, a channel stopper 2 and a field oxide film 3 for element isolation are formed on a P-type silicon substrate 1.
After the thin field oxide film 3 on the P-type silicon substrate 1 is removed, an impurity is implanted into the channel region 5 for controlling the threshold as shown in FIG. Next, the entire surface of the P-type silicon substrate 1 is thermally oxidized to form a first gate insulating film (SiO ₂ ) 6.

Next, as shown in FIG. 4C, after a polysilicon film 7 is formed over the entire surface of the P-type silicon substrate 1 by a CVD (chemical vapor deposition) method, a conductive film is formed on the polysilicon film 7. When ions are implanted into the entire surface of the P-type silicon substrate 1 from above so as to have a property, a protruding defect asperity 11 described later occurs. Next, the polysilicon film 7 in the non-volatile memory element formation region is left by photolithography and RIE (reactive ion etching), and the polysilicon film 7 in the other region is removed, as shown in FIG. Gate 7a of nonvolatile memory element
Is formed.

[0005] Next, as shown in FIG. 5 (b), C is formed on the entire upper surface of the P-type silicon substrate 1 to form a second gate insulating film.
The ONO film 8 is formed by the VD method. Next, a polysilicon film is formed on the ONO film 8 by CVD to form a control gate. Next, this polysilicon film 7
(Phosphorus: P) is ion-implanted, and then the ONO film 8 and the polysilicon film 7 in the non-volatile memory element forming region are left using photolithography and RIE, and the polysilicon film 7 and the ONO film in the other region are left. 8 are sequentially removed, the control gate (polysilicon) 7b and the second gate insulating film (ONO) are formed as shown in FIG.
A film 8b is formed. Next, phosphorus (phosphorus: P) is ion-implanted into the source region and the drain region.

Next, as shown in FIG. 6, an SOG film (Spin On Glas) is formed as an interlayer insulating film on the entire upper surface of the P-type silicon substrate 1.
s) After forming 9, a contact hole is opened in the drain electrode portion, and an aluminum film 10 is deposited. Next, the aluminum film 10 is patterned to form a drain electrode.

Next, a non-volatile memory element is formed by forming a P-SiN film 12 on the entire surface of the P-type silicon substrate 1 as a passivation film by a plasma CVD method.

[0008]

In the nonvolatile memory element shown in FIG. 8, the state in which the threshold voltage of the MOS transistor is increased by capturing electrons in the floating gate 7a is indicated by L.
ow, a state in which electrons are not captured or holes are captured and the threshold voltage is low is configured to correspond to High.

Electrons are written into the floating gate 7a by applying a high voltage to the drain region 4b to apply hot voltage to the floating gate 7a by applying a positive voltage to the control gate 7b. This is done by injection.

The non-volatile memory element according to this conventional method has a polysilicon film 7 in the step shown in FIG.
Asperity 11 is generated on the surface of the polysilicon film, and phosphorus (P) is further ion-implanted into the polysilicon film 7.
Projection defect asperity 1 due to minute defects (vacancies, interstitial atoms, etc.) on the surface and inside of polysilicon film 7
1 increases. Thereafter, when the ONO film 8 as the second gate insulating film shown in FIG. 5B is formed, the surface of the floating gate 7a is oxidized. In this oxidation process, an excessive lattice is formed in the floating gate 7a and in the vicinity thereof. Interstitial silicon atoms are generated, so that the interstitial silicon atoms are arranged so as to cover the surface of the protruding defect asperities 11, thereby forming the protruding defect asperities 11.
Will grow even larger.

However, the projection defect asperity 11
Performs the same function as a lightning rod when electrons are captured in the floating gate 7a, and the electrons are emitted as Fowler-Nordheim tunnel current to the control gate 7b through the second gate insulating film (ONO film) 8a. This causes a problem that the storage retention characteristics of the nonvolatile storage element are deteriorated.

Accordingly, the present invention provides a method of manufacturing a nonvolatile memory element in which asperities that cause deterioration of the memory retention characteristics of a nonvolatile memory element are reduced and reduced, and the potential energy of a control gate is increased to improve the memory retention property. The aim is to provide a method.

[0013]

The object, according to an aspect of the according to the present invention, the production of N-channel type nonvolatile memory element in a semiconductor device having a first gate insulating film / the floating gate / second gate insulating film / control gate a method, comprising: forming the first gate insulating film on a semiconductor substrate, the first gate insulating film, the first polysilicon film after forming the first polysilicon film obtained by introducing a phosphorus Forming a floating gate by ion-implanting a predetermined amount of oxygen into the floating gate and patterning; forming the second gate insulating film on the floating gate; and forming boron on the second gate insulating film. and forming the control gate by forming a second polysilicon film introduced, the Groote
And the control gate have different conductivity types.
That is solved by the method of manufacturing a nonvolatile memory element, characterized in that.

Further, according to the present invention, there is provided the above-mentioned first object.
2. The method according to claim 1, wherein the amount of oxygen introduced into the polysilicon film is 2 to 10% by weight.

[0015]

According to the present invention, after the first gate insulating film 6 of the nonvolatile memory element is formed on the semiconductor substrate 1 as shown in FIG. 1B, the first gate insulating film 6 is formed as shown in FIG. When a polysilicon film 7 in which phosphorus is introduced into one gate insulating film 6 is formed,
A protruding defect asperity 11 is formed on the surface. When oxygen is ion-implanted into the first polysilicon film 7, as shown in FIG. 2A and FIG. The protrusion defect asperity 11 can be reduced and reduced. Therefore, as shown in FIG. 2B, even if a second gate insulating film is formed on the first polysilicon film 7, the first polysilicon film 7 has already been formed.
Since the protrusion defect asperities 11 are small and small, the size of the protrusion defect asperities 11 on the surface of the first polysilicon film 7 can be reduced and the number thereof can be kept small. As a result, the floating gate 7a made of the first polysilicon film
ler-Nordheim tunnel current is reduced,
The storage retention characteristics of the nonvolatile storage element can be improved. Further, by setting the amount of oxygen introduced into the first polysilicon film to 2 to 10% by weight, it is possible to preferably improve the storage retention ability of the nonvolatile memory element. Also,
FIG. 9 shows an energy band structure diagram of a conventional nonvolatile memory element. FIG. 9A is an energy band structure diagram when the floating gate does not hold electrons, and FIG. FIG. 3 is an energy band structure diagram in a state where a floating gate holds electrons.
Control gate nonvolatile memory element is formed of polysilicon introducing the second gate insulating film / phosphorus consisting of floating gate / SiO ₂ composed of polysilicon was introduced first gate insulating film / phosphorus made of a silicon substrate / SiO ₂ It is composed of As shown in FIG. 9B, only the floating gate holds electrons,
Compared with the potential energy shown in FIG.
Potential energy at the gate insulating film and the second interface is increased.

Next, FIG. 10 is an energy band structure diagram of the nonvolatile memory element according to the present invention, and FIG. 10A is an energy band structure diagram when the floating gate does not hold electrons. (B) is an energy band structure diagram in a state where the floating gate holds electrons. This nonvolatile memory element includes a silicon substrate / a first gate insulating film made of SiO ₂ / a floating gate made of phosphorus-doped polysilicon /
A second gate insulating film made of SiO ₂ / a control gate made of boron-doped polysilicon.

As shown in FIG. 10A, boron is implanted into the second polysilicon constituting the control gate to make the control gate P-type, so that the conventional control gate made of N-type polysilicon is used. , The potential energy is higher by about 1 eV than at the interface between the control gate and the second gate insulating film.

Therefore, as shown in FIG. 10B, the potential energy of the second gate insulating film is increased by about 1 eV at the interface with the control gate as compared with the prior art, as shown in FIG. As a result, the Fowler-Nordheim tunnel current from the floating gate to the control gate through the second gate insulating film becomes smaller than before. As a result, the storage holding ability of the nonvolatile storage element is improved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

The non-volatile memory element shown in FIG. 7 is a plan view of a non-volatile memory element manufactured through a manufacturing process of a non-volatile memory element according to an embodiment of the present invention which will be described later. Excluding).

FIGS. 1 to 3 show one embodiment of the present invention, and are plan views of the nonvolatile memory element shown in FIG.

In this embodiment, first, as shown in FIG.
A channel stopper 2 and a field oxide film 3 for element isolation are formed on a silicon substrate 1. Next, P
After the thin field oxide film 3 on the type silicon substrate is removed, an impurity is implanted into the channel region 5 for controlling the threshold as shown in FIG. Next, the entire surface of the P-type silicon substrate 1 is thermally oxidized to form a first gate insulating film (SiO ₂ ) 6.

Next, as shown in FIG. 1C, a polysilicon film 7 is formed over the entire surface of the P-type silicon substrate 1 by the CVD method, and then a polysilicon film 7 is formed to have conductivity. Phosphorus (P) is ion-implanted into the entire upper surface of the mold silicon substrate 1. Next, as shown in FIG. 1D, ions are implanted into the entire upper surface of the P-type silicon substrate 1 with an oxygen amount of 2 to 10% by weight. As a result, as shown in FIG. 11B, the surface asperity defect asperity 11 of the polysilicon film 7 generated during the formation of the polysilicon film 7 and the ion implantation of phosphorus is reduced by the oxygen ion implantation. Can be smaller. At this time, the amount of oxygen to be implanted is 2% by weight.
If it is less than this, this effect is not sufficient, and if it is more than 10% by weight, there is a problem in characteristics of the nonvolatile memory element. Next, annealing is performed to activate the polysilicon film 7.

Next, as shown in FIG. 2A, the polysilicon film 7 in the non-volatile memory element forming region is left by photolithography and RIE, and the polysilicon film 7 in the other region is removed. Floating gate 7a is formed.

Next, as shown in FIG. 2B, an ONO film 8 is formed on the entire surface above the P-type silicon substrate 1 by a CVD method so as to form a second gate insulating film. At this time, asperity 1 of the protruding defect on the surface of the floating gate 7a
1 is smaller and smaller than the conventional one (FIG. 5B). Next, a polysilicon film 7 is formed on the ONO film 8 by a CVD method. Next, as shown in FIG. 2C, after boron ions are implanted into the polysilicon film 7, the polysilicon film 7 and the ONO film 8 in the non-volatile memory element formation region are left using photolithography and RIE.
When the polysilicon film 7 and the ONO film 8 in other regions are sequentially removed, as shown in FIG. 3A, the control gate 7b (polysilicon) and the second gate insulating film (O
An NO film 8b is formed. Next, phosphorus is ion-implanted into the source region and the drain region.

Next, as shown in FIG. 3 (b), an SOG film 9 (Spin
After forming On Glass), a contact hole is opened in the drain electrode portion, and an aluminum film 10 is deposited. Next, the aluminum film 10 is patterned to form a drain electrode.

Next, P-Si is formed on the entire surface of the P-type silicon substrate 1 as a passivation film by plasma CVD.
An N film 12 is formed. Through the above steps, a nonvolatile memory element can be manufactured.

FIG. 7 is a plan view (a passivation film and an interlayer insulating film are omitted) of the nonvolatile memory element manufactured through the above-described steps, in which a floating gate 7a, a control gate 7b, and an aluminum film 10 are formed. ing.

FIG. 8 is a sectional view taken along the line YY 'in FIG. As shown in FIG. 8, a source region 4a, a drain region 4b, and a channel region 5 are formed in a P-type silicon substrate 1, and a first gate insulating film 6 / floating gate 7a / second gate insulating film 8a / A control gate 7b is formed, and an interlayer insulating film (SOG
A film 9, an aluminum film 10, and a P-SiN film (passivation film) 12 are respectively formed.

[0030]

As described above, according to the present invention, the emission of electrons from the floating gate can be reduced by reducing and reducing the projection defect asperities generated on the surface of the floating gate of the nonvolatile memory element. As a result, the memory retention ability can be improved.

Furthermore, by the polysilicon control gate of the nonvolatile memory element boron is doped, about than polysilicon doped with phosphorus 1eV
Fowler-No from floating gate to control gate due to high potential energy
Since the current due to the rdheim tunneling can be reduced, the memory retention ability can be further improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first half of a process of manufacturing a nonvolatile memory element showing an example according to the present invention.

FIG. 2 is a cross-sectional view showing a half-step of manufacturing a nonvolatile memory element according to an embodiment of the present invention.

FIG. 3 is a sectional view showing the latter half of the process of manufacturing a nonvolatile memory element, showing an example according to the present invention.

FIG. 4 is a sectional view of the first half of the process of manufacturing a nonvolatile memory element according to a conventional example.

FIG. 5 is a sectional view showing a half-step of manufacturing a nonvolatile memory element according to a conventional example.

FIG. 6 is a sectional view showing a latter half of a process of manufacturing a nonvolatile memory element according to a conventional example.

FIG. 7 is a plan view of a nonvolatile memory element.

FIG. 8 is a sectional view of the nonvolatile memory element taken along the line YY ′ in FIG. 7;

FIG. 9 is an energy band structure diagram of a conventional nonvolatile memory element.

FIG. 10 is an energy band structure diagram of the nonvolatile memory element according to the present invention.

FIG. 11 is a sectional view showing the magnitude of asperity due to oxygen ion implantation.

[Explanation of symbols]

Reference Signs List 1 P type silicon substrate 2 Channel stopper 3 Field oxide film 4 a Source region 4 b Drain region 5 Channel region 6 First gate insulating film (SiO ₂ ) 7 Polysilicon film 7 a Floating gate (polysilicon) 7 b Control gate (polysilicon) 8 ONO film 8b second gate insulating film (ONO film) 9 SOG film (interlayer insulating film) 10 aluminum film 11 asperity 12 passivation film (P-SiN film) E _V valence band level E _C conduction band level E _F Fuerumireberu

Continuation of the front page (56) References JP-A-64-2375 (JP, A) JP-A-3-94473 (JP, A) JP-A-2-122570 (JP, A) JP-A-63-179577 (JP) JP-A-62-24673 (JP, A) JP-A-59-149061 (JP, A) JP-A-57-72333 (JP, A) JP-A-50-9387 (JP, A) 5-243582 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A method of manufacturing an N-channel nonvolatile memory element in a semiconductor device having a first gate insulating film / floating gate / second gate insulating film / control gate , wherein the first gate is provided on a semiconductor substrate. forming an insulating film, the first gate insulating film, on the first polysilicon film after forming the first polysilicon film obtained by introducing the phosphorus oxygen predetermined amount by ion implantation, patterning Forming the floating gate on the floating gate, forming the second gate insulating film on the floating gate, and forming a second polysilicon film doped with boron on the second gate insulating film. Forming a control gate; and
A method for manufacturing a nonvolatile memory element, wherein the control gate has a different conductivity type . 2. The method according to claim 1, wherein the amount of oxygen introduced into the first polysilicon film is 2 to 10% by weight.