GB1595543A

GB1595543A - Memory cell

Info

Publication number: GB1595543A
Application number: GB3022/78A
Authority: GB
Original assignee: Mostek Corp
Current assignee: CTU of Delaware Inc
Priority date: 1977-01-26
Filing date: 1978-01-25
Publication date: 1981-08-12
Also published as: JP2720911B2; DE2802048C2; JPH0918003A; GB1595548A; FR2382767A1; JPH098299A; IT1089299B; GB1595547A; FR2382767B1; JPS5760852A; FR2382769A1; FR2382770A1; JPS62290147A; JPS62290181A; FR2382745B1; JPH0362300B2; FR2382768A1; FR2382768B1; GB1595546A; DE2802048A1

Description

(54) MEMORY CELL (71) We, MOSTEK CORPORATION, a corporation organized and existing under the laws of the State of Delaware, at 1215 West Crosby Road, Carrollton, Dallas County, Texas, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to a memory cell.

According to the present invention there is provided a memory cell comprising: a semiconductor substrate having a surface portion defining a site for the memory cell; a charge storage area disposed in the substrate immediately below the surface within the site; a first insulating layer or insulating layer portion disposed on the surface above the charge storage area; a first conductive layer disposed on the first insulating layer or insulating layer portion in juxtaposition over the charge storage area; a channel area disposed in the substrate immediately below the surface and adjacent to the charge storage area; a second insulating layer or insulating layer portion disposed on the surface above the channel area; a third insulating layer or insulating layer portion adjoining the second insulating layer or insulating layer portion and extending over the first conductive layer; and a second conductive layer, the second conductive layer having a lower portion disposed on the second insulating layer or insulating layer portion in juxtaposition over the channel area, and having an upper portion disposed on the third insulating layer or insulating layer portion partially overlapping the first conductive layer; wherein the thickness of the first insulating layer or insulating layer portion is about 900 Angstroms, the thickness of the second insulating later or insulating layer portion is not less than 1500 Angstroms and not more than 2000 Angstroms,.and the thickness of the third insulating layer or insulating layer portion is not less than 3000 Angstroms.

Preferably the memory cell of the invention further comprises: a data transmission region disposed in the substrate in operative proximity to the channel area, the data transmission region having a conductivity type opposite to that of the channel area; whereby, on the application of a voltage to the first conductive layer for holding a charge in the charge storage area; and on the application of a gate signal to the second conductive layer for inducing a channel in the channel area to bring the charge storage area into electrical communication with the data transmission region, electrical representations of binary information may be stored in the cell.

The first and second conductive layers preferably comprise heavily doped polysilicon, and the third insulating layer or insulating layer portion preferably comprises silicon dioxide grown from the first conductive polysilicon layer.

Preferably the third insulating layer or insulating layer portion is between 3000 and 6000 Angstroms thick.

The memory cell of the invention can be made by a method of making a semiconductor device described and claimed in our co-pending Application No. 7932522 (Serial No. 1595544). Such a method will now be described by way of example with reference to the accompanying drawings in which: Figures 1-20 are schematic sectional views illustrating portions of an integrated circuit device at various stages in a method for making the device; Figure 21 is an enlarged view of a representative portion of Figure 20; Figure 22 is a schematic sectional view illustrating a succeeding step in the method; Figure 23 is an enlarged view of a representative portion of Figure 22; Figures 24 and 25 are schematic sectional views illustrating succeeding steps in the method; Figure 26 is an enlarged view of a representative portion of Figure 25; Figure 27 is a schematic sectional view illustrating a succeeding step in the method; Figure 28 is an enlarged view of a representative portion of Figure 27; Figure 29 is an enlarged view similar to the view of Figure 28 illustrating a succeeding step in the method; and Figure 30 is a schematic sectional view illustrating important features of the device at a final stage in the method.

Referring to Figure 1 there is shown a schematic cross-section of a portion of an integrated circuit device. indicated generally by the reference numeral 10. at an early stage in a manufacturing method. The device 10 comprises a substrate 12 which is typically monocrystalline silicon of a conventional crystal orientation known in the art. Manly features of the present invention are applicable to devices cmploying scmi- conductor materials other than silicon as will be appreciated by those skilled in the art. The substrate 12 may be either P-type or N-type; however, for purposes of this illustrative embodiment. P-type conductivity is employed, a preferred resistivity being about 5 to 25 ohm-cm in the substrate 12.

Thermally grown on top surface 14 of the substrate 12 is a silicon dioxide layer 16, having a preferred thickness of about 600 Angstroms. A silicon nitride layer 18, having a preferred thickness of about 600 Angstroms is deposited on thermal oxide layer 16 in a reactor in a known manner. A top layer 20 of polysilicon having a thickness of about 1000 Angstroms is deposited on nitride layer 18 using known deposition techniques.

The device 10 is then exposed to an oxidizing ambient preferably in steam between 900"C and 1000"C for a sufficient period of time completely to oxidize the polysilicon layer 20 of Figure 1, thereby producing a polyoxide layer 22 as shown in Figure 2. The polyoxide layer 22 is about 2000 Angstroms thick, which is about twice the thickness of the original polysilicon layer 20 due to growth during oxidation.

Referring to Figure 3, representative portions of device 10 are shown after several intermediate steps have been performed.

While two distinct component segments or element sites 24 and 26 are explicitly illustrated in Figure 3, it is to be understood that they are representative of a great many similar sites (not shown) wherein similar elements are simultaneously produced in accordance with the description of the method which follows. At both sites 24 and 26, photoresist patterns 28 and 30 have been deposited on polyoxide layer 22 using standard photomasking techniques, after which the unmasked portions of layer 22 are etched away using an etch ant which selectively attacks oxide thereby leaving polyoxide portions 32 and 34 as shown. Following the etching step, an ion implant step is performed in a known manner as indicated by the arrows, preferably using boron, to produce P+ regions 36, which penetrate to a depth of about 2000 Angstroms in the portions of the substrate 12 not covered by polyoxide (also referred to as the "field area" of the device 10). The energy of the ions is selected so as to penetrate only through the portions of layers 16 and 18 not covered by photoresist and polyoxide. An intensity of about 1.6 x l()|3 boron ions/cm2 is preferably used in accordance with known techniques as, for example, hy means of the techniques described in the U.S. Patent specification No. 3,898,l()5. Whatevcr tcchnique is used, however, it is preferred that P+ regions 36 have a resistivity of about one ohm-cm in the areas of highest impurity concentration in the final device.

Next, the photoresist layers 2X and 30 are removed and the portions of the nitride layer 18 not covered by the polyoxide layer portions 32 and 34 are sclectively etched away using known techniques, thereby leaving nitride portions 38 and 40 as shown in Figure 4.

Now referring to Figure 5, an oxidation is performed in steam for about 6 to X hours at approximately 1000"C, which results in the growth of a relatively thick "isoplanar field oxide" layer 42, preferably of about 14,000 Angstroms in thickness, in the portions of the substrate 12 not covered by silicon nitride. The field oxide 42 penetrates into the substrate 12 to a depth of about 7000 Angstroms, the oxidation process driving the boron implant regions 36 to a greater depth therebelow. The P+ regions 36 permit the use of a thinner field oxide 42 by reducing the resistivity thereunder.

Next, the polyoxide layers 32 and 34 are removed by means of etching with hvdrofluoric acid in a known manner, which also slightly reduces the thickness of the field oxide 42. Then, the nitride layers 38 and 40 and the remaining portions of oxide layer 16 are removed using conventional techniques.

which produces the structure shown in Figure 6.

Various surface "cleaning" steps are ordinarily used at this point in prior art proces- ses to remove surface damage in the active area of the device. By "active area" is meant those portions of the device where no field oxide has been grown. It has been found, however, that merely cleaning by etching some of the substrate 12 along surface 14 is inadequate to remove- silicon nitride contamination which exists along edges 44 of the substrate 12 near the field oxide 42. Small amounts of silicon nitride from layers 38 and 40 are transported to the substrate surface 14 at the edges of the field oxide 42 incident to the chemical process which produces the field oxide 42. Accordingly, an oxidation step is performed, preferably in an ambient atmosphere of hydrogen chloride and oxygen, to produce thermal oxide layers 46 and 48 as shown in Figure 7, thereby gathering the nitride impurities at edges 44 from the substrate 12 into the oxide as it grows. A thickness of about 300 Angstroms is sufficient for oxide layers 46 and 48, with a preferred thickness being between 300 and 1000 Angstroms.

Next, the oxide layers 46 and 48 are etched away to produce the structure of Figure 8. It will be appreciated by those skilled in the art that good surface conditions are important to the operation of field-effect device elements, and particularly in the channel of an enchancement mode FET. In accordance with an important feature, the oxidizing and etching steps of Figures 7 and 8 are effective to remove surface damage (generally occurring in the top 20 to 30 Angstroms of the substrate 12) as well as the silicon nitride contamination, thereby providing the clean, impurity-free surface portions 14 shown in Figure 8.

As a result of the successive etching steps to remove oxide layers 16,32,34,46, and 48 in the steps shown from Figures 5 to 8, the field oxide 42 is somewhat reduced in thickness. At the stage shown in Figure 8, the field oxide has an overall thickness of about 10,000 Angstroms, with about 7000 Angstroms extending to a level below the level of surface 14 and about 3000 Angstroms extending above the level of surface 14.

Next, thermal oxide layers 50 and 52 are grown to a thickness of about 900 Angstroms as shown in Figure 9. A light dose boron ion implantation is then performed using known techniques as indicated by the arrows for purposes of threshold voltage adjustment of the field-effect elements which will be formed subsequently in sites 24 and 26.

Now referring to Figure 10, a polysilicon layer 54 is deposited as shown over the entire device 10 to a thickness of about 6000 Angstroms using known techniques. In order to make layer 54 become highly conductive, it is then heavily doped N-type, preferably using phosphorus diffusion as represented by the stippling of polysilicon layer 54 in Figure 11.

Next a top portion 56 of layer 54 is oxidized to produce the structure shown in Figure 12. Polyoxide layer 56 has a preferred thickness of between 2500 and 5000 Angstroms, the formation of which causes a corresponding reduction in the thickness of polysilicon layer 54 to between 3500 and 4800 Anstroms. It is presently preferred, however, that layers 54 and 56 both be about 4000 Angstroms thick.

Figure 13 illustrates device 10 after masking and etching steps have been performed wherein photoresist patterns 58 and 60 are formed, and the portions of polyoxide layer 56 not covered by photoresist are etched away leaving polyoxide portions 62 and 64.

Optionally, another light dose implant may be performed at this stage for fine adjustment of the threshold of the field-effect element to be formed in site 24.

Now referring to Figure 14, the photoresist has been removed leaving the polyoxide layer portions 62 and 64 as masks for etching away portions of polysilicon layer 54. At similar sites of the device 10 of which sites 24 and 26 are representative, similar polyoxide masks also exist so that etching produces a plurality of separate polysilicon layers in the device 10 of which layers 66 and 68 are representative. The polysilicon layer 66 overlies a portion of thermal oxide layer 50 and extends over an adjacent portion of field oxide layer 42 as shown at element site 24. The polysilicon layer 68 overlies a center portion of thermal oxide layer 52 in the element site 26 as shown in Figure 14.

The use of polyoxide portions 62 and 64 as masks for etching the underlying polysilicon has advantages over prior art deposited oxide masks in that polyoxide growth produces a highly regular layer having a slower, more controllable etch rate. Such properties of polyoxide enable a high degree of mask definition to be carried through from the photoresist mask (layers 58 and 60 in Figure 13) to the polyoxide mask (layers 62 and 64 in Figure 14). The high degree of mask definition is further carried through in the formation of polysilicon layers 66 and 68. By "high definition" is meant "positioned with a higher degree of precision" compared to prior art techniques using deposited oxide masks. The polysilicon layer 68 will be seen layer in the method to serve further as a mask for etching the underlying oxide layer, thereby aligning itself over a channel region of a field-effect transistor. The technique of using a polysilicon layer as a mask for producing a self-aligned gate FET is known, the structure also being referred to in the art as a "silicon-gate" FET. The precision (or tolerance) in positioning layers 66 and 68 has a direct bearing on the degree of element density capable of formation in the integrated circuit device 10.

An oxidation step is now performed on the structure of Figure 14 to cover the exposed edges of polysilicon layers 66 and 68 with polyoxide as shown in Figure 15.

Thermal oxide portions 50 and 52 remain at a thickness of about 900 Angstroms, while uncovered thermal oxide portions 70 and 72 increase in thickness to 1500 to 2000 Angstroms. Polyoxide layers 62 and 64 grow from a minimum of 2500 Angstroms to a thickness of at least about 3000 Angstroms, which again reduces layers 66 and 68 slightly in thickness.

A new polysilicon layer 74 is now deposited over the device 10 as shown in Figure 16 using known deposition techniques in similar fashion to the deposition step of Figure 10. The layer 74 has a preferred thickness of about 4000 Angstroms.

Next a partial oxidation of polysilicon layer 74 is performed to produce a polyoxide layer 76 having a thickness of about 1000 Angstroms as shown in Figure 17. The oxidation reduces polysilicon layer 74 to a thickness of about 3500 Angstroms.

Now referring to Figure 18, the device 10 is shown after a photoresist pattern 78 has been used to mask polyoxide layer 76, which is etched away entirely at site 26 and partially at site 24. The remaining polyoxide 76 overlies both a lower portion 80 and an upper portion 82 of polysilicon layer 74 at site 24.

Referring to Figure 19, the photoresist has been removed and the remaining polyoxide 76 has been used as a mask to etch polysilicon layer 74, thereby removing layer 74 entirely from site 26 and partially from site 24 to produce the structure shown.

It will be seen that the method steps for producing the second polysilicon layer 74 as illustrated in Figures 16-19 are essentially the same (aside from thickness variations) as the method steps for producing the first polysilicon layer 66 as illustrated in Figures 10-14, except that layer 74 remains undoped at the stage of the method shown in Figure 19. For purposes of this specification, the term "undoped" means "essentially free of conductivity affecting impurities" such as phosphorus(N-type), boron (P-type) and their known functional equivalents.

It will also be appreciated that the arrangement of polysilicon layers 66 and 74 enables elements of the type shown in site 24 to be arranged in a dense manner in device 10. In particular, by overlapping the field oxide 42 with layer 66 and likewise overlapping layer 66 with layer 74, interconnections between adjacent cells (not shown) are facilitated, and the formation of contacts in subsequent steps is not a limiting factor in choosing the amount of active surface area 14 allocated to element 24.

Next, an etch is performed which selectively removes a portion of polyoxide layer 70 to expose a portion of surface 14 in the area of site 24 not covered by polysilicon and removes polyoxide layer 72 to expose portions of surface 14 in the area of site 26 not covered by polysilicon. Therefter, an N-type dopant, preferably phosphorus, is diffused using known techniques whereby thermal oxide layers 50,52 and 70 act as diffusion masks in producing N+ regions 86,88, and 90 in the substrate 12, to a depth of about 15,000 Angstroms below surface 14 in accordance with the structure of Figure 20. The phosphorus also diffuses into the top polysilicon layer 74 (as indicated by the stippling), which causes layer 74 to be heavily doped N-type and thus highly conductive. In an alternative embodiment using an N-type substrate, a P-type diffusion, typically using boron, would be performed at this stage to produce the complementary conductivity-type structure of that shown herein.

In order to be sure that no thermal oxide is left on surface 14 where the diffusion is to be performed, it is general practice to over etch somewhat causing a significant amount of lateral etching or undercutting which can be the soure of problems in the areas identified by numeral 84. Precise control of the etch duration will minimize the amount of undercutting, which may result in a small amount of polyoxide layers 62 and 64 being left over polysilicon layers 66 and 68 as shown in Figure 20. In any event, the etched duration must be long enough to remove all oxide from polysilicon layer 74 and from the portions of surface 14 above the diffused regions 86, 88 and 90 to permit the N-type dopants to diffuse therein.

The enlarged view of Figure 21 shows in greater detail, a typical undercut area 84, such as the area under polysilicon layer 68, where thermal oxide layer 52 has been laterally etched to a distance from peripheral edge 92 of polysilicon layer 68, which distance is typically somewhat greater than the thickness of thermal oxide layer 52.

Now referring to Figures 22 and 23, the device 10 is placed in a furnace with dry oxygen or steam at 9000C to 1000"C so that oxide layers of about 2000 Angstroms are grown over the various polysilicon layers as indicated by numerals 94, and over the various N+ regions in the substrate 12 as indicated by numerals 96. The oxidation is effective to fill in the undercut portions 84 as illustrated more clearly in the enlarged view of Figure 23. The position of the peripheral edge of polysilicon layer 68 prior to oxidation is indicated by the dashed line 92'. The growth of polyoxide layer 94 has the effect of moving the peripheral edge 92 of polysili con layer 68 slightly to the left in the view of Figure 23. In addition, growth of thermal oxide layer 96 moves the substrate surface 14 downward from its original position 14'.

Now referring to Figure 24, a layer 98 of "high temperature" undoped oxide is deposited, preferably using SiH4 and CO2 in a known manner, at a temperature between 600"C and 1000"C to a thickness of preferably about 6000 Angstroms. At a corresponding stage, prior art processes typically deposit a "low temperature" oxide in a range of 350"C to 450"C, which has a relatively fast etch rate causing extensive undercutting problems. The present method provides a deposited undoped oxide layer 98 which has an etch rate similar to that of underlying grown oxide layers 94 and 96.

Most preferably, oxide layer 98 is deposited by placing the device 10 in a conventional RF reactor and heating the device to about 900"C or 950"C to cause the reaction: SiH4 + 2CO2 o SiO2 + 2CO + 2H2 In accordance with an additional feature of the present method, it will be appreciated that layer 98 is a redundant oxide layer which covers possible defects such as "pinholes" in the underlying oxide layers 94 or 96.

A photoresist mask 100 is then formed over deposited oxide layer 98. Next, contact windows 102 are opened by etching through the portions of oxide layer 98 not covered by photoresist mask 100, and continuing to etch down through the underlying oxide layers 94 and 96 as shown in Figure 25.

While a certain amount of lateral etching undercuts photoresist layer 100 in the manner typical of Figure 26, the amount of undercut is minimal due to the closely matched etching rates of the "high temperature" undoped oxide layer 98 and the underlying oxide layers 94 and 96. Accordingly, very small contacts may be produced in the present method as will be seen below.

Next, the photoresist layer 100 is removed, and a stabilization step is performed, preferably using a phosphorus diffusion, as indicated by the stippling along the exposed oxide surfaces shown in Figure 27 and the enlarged view of Figure 28. The phosphorus stabilization has the effect of producing very thin oxide layers 104 on exposed silicon surfaces (explicitly shown by way of example in Figure 28) which are approximately 20 to 100 Angstroms thick.

It is convenient to getter the device 10 concurrently with stabilization, which may be achieved by covering all but the backside (i.e., the bottom surface of the substrate 12 with oxide thereon, not shown) with photoresist after opening windows 102, then stripping the backside down to clean silicon.

Stabilization then proceeds as described in the preceding paragraph by removing the photoresist and exposing the device 10 to a phosphorus diffusion, which getters metallic impurities to the backside thereby favorably reducing leakage current.

After the phosphorus stabilization step it is necessary to reopen contact windows 102 through oxide layers 104. A photoresist layer (not shown) is reapplied using the same mask registration which produced layer 100. Then, oxide layers 104 are etched through to the underlying silicon to reopen the contact windows 102, and the photoresist is removed to produce windows 102 typically illustrated by Figure 29. The window opening 102 at surface 14 shown in Figure 29 may be controlled to less than 5 microns in diameter, whereas known prior art processes were previously limited to about 8 microns.

Accordingly, it will be seen that in the present method there is provided a technique for making very small windows so that contacts may be positioned with precision therein. This important feature is achieved by the above sequence of steps in which the windows are etched through undoped oxide layers prior to stabilization. The method described herein has been found to permit a reduction in the surface area allocated to contacts by about 40% over the best known prior art.

Finally, a metallization process is used to form contacts 106, 108, 110, 112,114 and 116 in the windows 102 which yields the device structure 10 shown in Figure 30. The contacts are preferably formed by vacuum deposition of aluminum, photomasking portions of the aluminum, and etching the unmasked portions with etchants which selectively attack the aluminum but not the underlying oxide layer 98.

Those skilled in the art will recognize the utility of the element structures shown in Figure 30, wherein the element in site 24 serves as charge storage cell or memory cell and the element in site 26 serves as a field-effect transistor.

In particular, the element 26 in an Nchannel enhancement mode FET having a self-aligned silicon gate similar to that which is described in U.S. Patent Specification 3898105, wherein contact 114 serves as a gate contact to silicon gate 68 and contacts 112 and 116 serve as source and drain contacts to regions 88 and 90. The present method may also be applied to incorporate N-channel depletion mode FETs as well as both modes of P-channel FETs by modification of the method steps specifically recited herein in accordance with the teachings of that U.S. Patent Specification.

The element 24 is a small area memory cell of the destructive readout type known in the art, having a single transistor and a single capacitor. A complementary memory cell may be produced having conductivity types opposite to those specifically shown in site 24 of Figure 30 as will be appreciated by those skilled in the art.

The operation of a memory cell such as the cell 24 of Figure 30 is known in the art.

Briefly, contact 106 is biased with a voltage sufficient to hold a charge of minority carriers in the substrate 12 in an area 118 along the surface 14 to which conductive polysilicon layer 66 is in close proximity. In circuit analogy, a capacitor is formed by oxide layer 50 serving as a dielectric between the polysilicon layer 66 and the charge storage area 118 in juxtaposition thereunder. The presence or absence of a charge in storage area 118 represents binary information, which may be both sensed and altered through region 86 and contact 110 whenever a gate signal is applied to contact 108. A gate signal applied to contact 108 having a sufficiently high voltage known in the art will be carried by conductive polysilicon layer 74 thereby inducing a channel in substrate 12 along an area 120 near surface 14 immediately under oxide layer 70. Such an induced channel in area 120 permits electrical communication between data transmission region 86 and the charge storage area 118. The area 120 is the circuit equivalent of a channel region in a FET, which in this embodiment is an N-channel enhancement mode FET. Therefore the memory cell 24 may be viewed as comprising a single transistor and a single capacitor in basic function, ignoring as negligible any incidental capacitances and resistances of the structure.

An advantage of the above method steps involves the formation of insulating layers 50,62 and 70 having varying thicknesses which are important to proper device functioning. As discussed above, the present method successfully achieves a relatively thin oxide layer 50 having thickness of about 900 Angstroms, a slightly thicker oxide layer 70 having a thickness of 1500 to 2000 Angstrom';, and a substantially thicker oxide layer 62 having a thickness in excess of 3000 Angstroms. Ideally, layer 62 should be as thick as possible to render negligible any parasitic capacitance existing between polysilicon layers 66 and 74. Since layer 62 is polyoxide grown from the 6000 Angstrom deposit of polysilicon which produced layer 66, the thickness of layer 62 is limited as a practical matter to a maximum of about 8000 Angstroms, which still leaves a sufficient thickness of polysilicon for layer 66. In present commercial embodiments, layer 62 is about 4000 Angstroms, while a thickness of between 3000 and 6000 Angstroms is acceptable.

From the foregoing description, taken with the drawings, it will be apparent that the present invention has broad applicability to commercial semiconductor devices. In particular, the above method has great utility in the manufacture of high density RAMs, and has facilitated the manufacture of a "16K.RAM" i.e., a random-access memory device having 16,384 memory cells in accordance with the invention.

Various subsidiary sequences of method steps of the overall method described above are claimed in co-pending Applications Nos.

7932522, 7932523, 7932524, 7932525 and 8019043. (Serial Nos. 1595544, 1595545, 1595546, 1595547 and 1595548).

WHAT WE CLAIM IS: 1. A memory cell comprising: a semiconductor substrate having a surface portion defining a site for the memory cell; a charge storage area disposed in the substrate immediately below the surface within the site; a first insulating layer or insulating layer portion disposed on the surface above the charge storage area; a first conductive layer disposed on the first insulating layer or insulating layer portion in juxtaposition over the charge storage area; a channel area disposed in the substrate immediately below the surface and adjacent to the charge storage area; a second insulating layer or insulating layer portion disposed on the surface above the channel area; a third insulating layer or insulating layer portion adjoining the second

Claims

**WARNING** start of CLMS field may overlap end of DESC **. cell may be produced having conductivity types opposite to those specifically shown in site 24 of Figure 30 as will be appreciated by those skilled in the art. The operation of a memory cell such as the cell 24 of Figure 30 is known in the art. Briefly, contact 106 is biased with a voltage sufficient to hold a charge of minority carriers in the substrate 12 in an area 118 along the surface 14 to which conductive polysilicon layer 66 is in close proximity. In circuit analogy, a capacitor is formed by oxide layer 50 serving as a dielectric between the polysilicon layer 66 and the charge storage area 118 in juxtaposition thereunder. The presence or absence of a charge in storage area 118 represents binary information, which may be both sensed and altered through region 86 and contact 110 whenever a gate signal is applied to contact 108. A gate signal applied to contact 108 having a sufficiently high voltage known in the art will be carried by conductive polysilicon layer 74 thereby inducing a channel in substrate 12 along an area 120 near surface 14 immediately under oxide layer 70. Such an induced channel in area 120 permits electrical communication between data transmission region 86 and the charge storage area 118. The area 120 is the circuit equivalent of a channel region in a FET, which in this embodiment is an N-channel enhancement mode FET. Therefore the memory cell 24 may be viewed as comprising a single transistor and a single capacitor in basic function, ignoring as negligible any incidental capacitances and resistances of the structure. An advantage of the above method steps involves the formation of insulating layers 50,62 and 70 having varying thicknesses which are important to proper device functioning. As discussed above, the present method successfully achieves a relatively thin oxide layer 50 having thickness of about 900 Angstroms, a slightly thicker oxide layer 70 having a thickness of 1500 to 2000 Angstrom';, and a substantially thicker oxide layer 62 having a thickness in excess of 3000 Angstroms. Ideally, layer 62 should be as thick as possible to render negligible any parasitic capacitance existing between polysilicon layers 66 and 74. Since layer 62 is polyoxide grown from the 6000 Angstrom deposit of polysilicon which produced layer 66, the thickness of layer 62 is limited as a practical matter to a maximum of about 8000 Angstroms, which still leaves a sufficient thickness of polysilicon for layer 66. In present commercial embodiments, layer 62 is about 4000 Angstroms, while a thickness of between 3000 and 6000 Angstroms is acceptable. From the foregoing description, taken with the drawings, it will be apparent that the present invention has broad applicability to commercial semiconductor devices. In particular, the above method has great utility in the manufacture of high density RAMs, and has facilitated the manufacture of a "16K.RAM" i.e., a random-access memory device having 16,384 memory cells in accordance with the invention. Various subsidiary sequences of method steps of the overall method described above are claimed in co-pending Applications Nos. 7932522, 7932523, 7932524, 7932525 and 8019043. (Serial Nos. 1595544, 1595545, 1595546, 1595547 and 1595548). WHAT WE CLAIM IS:

1. A memory cell comprising: a semiconductor substrate having a surface portion defining a site for the memory cell; a charge storage area disposed in the substrate immediately below the surface within the site; a first insulating layer or insulating layer portion disposed on the surface above the charge storage area; a first conductive layer disposed on the first insulating layer or insulating layer portion in juxtaposition over the charge storage area; a channel area disposed in the substrate immediately below the surface and adjacent to the charge storage area; a second insulating layer or insulating layer portion disposed on the surface above the channel area; a third insulating layer or insulating layer portion adjoining the second insulating layer or insulating layer portion and extending over the first conductive layer; and a second conductive layer, the second conductive layer having a lower portion disposed on the second insulating layer or insulating layer portion in juxtaposition over the channel area, and having an upper portion disposed on the third insulating layer or insulating layer portion partially overlapping the first conductive layer; wherein the thickness of the first insulating layer or insulating layer portion is about 900 Angstroms, the thickness of the second insulating later or insulating layer portion is not less than 1500 Angstroms and not more than 2000 Angstrom';, and the thickness of the third insulating layer or insulating layer portion is not less than 3000 Anstroms.

2. A memory cell according to claim 1 further comprising: a data transmission region disposed in the substrate in operative proximity to the channel area, the data transmission region having a conductivity type opposite to that of the channel area; whereby, on the application of a voltage to the first conductive layer for holding a charge in the charge storage area; and

on the application of a gate signal to the second conductive layer for inducing a channel in the channel area to bring the charge storage area into electrical communication with the data transmission region, electrical representation of binary information may be stored in the cell.

3. A memory cell according to claim 1 or claim 2 wherein the first and second conductive layers comprise heavily doped polysilicon, and the third insulating layer or insulating layer portion comprises silicon dioxide grown from the first conductive polysilicon layer.

4. A memory cell according to any one of the preceding claims wherein the thickness of the third insulating layer or insulating layer portion is between 3000 and 6000 Angstrom';.

5. A memory cell according to claim 1 substantially as hereinbefore described with reference to and as illustrated in Figure 30 of the accompanying drawings.

6. An integrated circuit device including a memory cell according to any one of claims 1 to 4.

7. An integrated circuit device according to claim 6 comprising said memory cell and a field-effect transistor.

8. An integrated circuit device according to claim 6 substantially as hereinbefore described with reference to and as illustrated in Figure 30 of the accompanying drawings.