GB1175392A - Method of Treating Protective Coatings for Semiconductor Devices - Google Patents

Method of Treating Protective Coatings for Semiconductor Devices

Info

Publication number
GB1175392A
GB1175392A GB4036067A GB4036067A GB1175392A GB 1175392 A GB1175392 A GB 1175392A GB 4036067 A GB4036067 A GB 4036067A GB 4036067 A GB4036067 A GB 4036067A GB 1175392 A GB1175392 A GB 1175392A
Authority
GB
United Kingdom
Prior art keywords
apertures
etching
mask
layer
etching mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4036067A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1175392A publication Critical patent/GB1175392A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)

Abstract

1,175,392. Semi-conductor devices. HITACHI Ltd. 4 Sept., 1967 [14 Sept., 1966], No. 40360/67. Heading H1K. In order to expose surface regions of a semiconductor body 51a through apertures 55, 56 in two superposed insulating layers, the upper of which 53 is less etchant-resistant than the lower 52, a first etching mask 54 is used to define the apertures in the upper layer 53 and a second etching mask 57 is then applied so as to protect the exposed edges of the layer 53 around the apertures 55, 56 during a second etch which penetrates the lower layer 52. As shown, the body 51a is of N-type Si having a P-type diffused base region 51b and an N-type diffused emitter region 51c to comprise a transistor. The emitter region 51c is formed by phosphorus-diffusion through an oxide mask 52, a phospho-silicate glass layer 53 being formed simultaneously. The two etching masks 54, 57 are of photoresist materials, the second of which, 57, is applied to the entire surface and subsequently washed free of the bottoms of the apertures 55, 56. The exposed edges of the easily etched glass layer 53 remain protected by the second mask 57 during the second etching stage. After exposure of the semi-conductor surface through the apertures 55, 56, the photoresist layers 54, 57 are removed and electrodes, e.g. of Al, are applied. In an alternative embodiment, the first etching mask may be completely removed from the surface between the first etching stage and the application of the second etching mask.
GB4036067A 1966-09-14 1967-09-04 Method of Treating Protective Coatings for Semiconductor Devices Expired GB1175392A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6035766 1966-09-14

Publications (1)

Publication Number Publication Date
GB1175392A true GB1175392A (en) 1969-12-23

Family

ID=13139806

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4036067A Expired GB1175392A (en) 1966-09-14 1967-09-04 Method of Treating Protective Coatings for Semiconductor Devices

Country Status (2)

Country Link
DE (1) DE1621468B2 (en)
GB (1) GB1175392A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089299B (en) * 1977-01-26 1985-06-18 Mostek Corp PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE

Also Published As

Publication number Publication date
DE1621468B2 (en) 1971-01-07
DE1621468A1 (en) 1971-01-07

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees