JPS5713772A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5713772A
JPS5713772A JP8786780A JP8786780A JPS5713772A JP S5713772 A JPS5713772 A JP S5713772A JP 8786780 A JP8786780 A JP 8786780A JP 8786780 A JP8786780 A JP 8786780A JP S5713772 A JPS5713772 A JP S5713772A
Authority
JP
Japan
Prior art keywords
gate
eprom
directly under
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8786780A
Other languages
Japanese (ja)
Inventor
Jun Sugiura
Kazuhiro Komori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8786780A priority Critical patent/JPS5713772A/en
Priority to DE19813124283 priority patent/DE3124283A1/en
Priority to GB8119691A priority patent/GB2080024A/en
Publication of JPS5713772A publication Critical patent/JPS5713772A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: To enhance the writing efficiency of an EPROM and to increase the integration of the EPROM by partly extending the same conductive type high density layer as a semiconductor substrate formed directly under a field insulating film to the semiconductor region directly under the gate insulating film.
CONSTITUTION: A field oxidized film 2 is formed at the periphery of a p- type Si substrate 1, and in an EPROM having a p+ type channel stopper 10, a gate oxidized film 3, a floating a gate 4, an interlayer insulating film 5 and a control gate 6, a part 10a of the stopper 10 extends directly under the film 3. Since a hot electron generation efficiency becomes good in this manner, the writing speed can be accelerated, and the integration can also be enhanced.
COPYRIGHT: (C)1982,JPO&Japio
JP8786780A 1980-06-30 1980-06-30 Semiconductor device and manufacture thereof Pending JPS5713772A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8786780A JPS5713772A (en) 1980-06-30 1980-06-30 Semiconductor device and manufacture thereof
DE19813124283 DE3124283A1 (en) 1980-06-30 1981-06-19 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
GB8119691A GB2080024A (en) 1980-06-30 1981-06-25 Semiconductor Device and Method for Fabricating the Same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8786780A JPS5713772A (en) 1980-06-30 1980-06-30 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5713772A true JPS5713772A (en) 1982-01-23

Family

ID=13926819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8786780A Pending JPS5713772A (en) 1980-06-30 1980-06-30 Semiconductor device and manufacture thereof

Country Status (3)

Country Link
JP (1) JPS5713772A (en)
DE (1) DE3124283A1 (en)
GB (1) GB2080024A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594170A (en) * 1982-06-30 1984-01-10 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS60223945A (en) * 1984-04-21 1985-11-08 Shinryo Air Conditioning Co Ltd Blow-off port structure for clean room
US4780424A (en) * 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US5330938A (en) * 1989-12-22 1994-07-19 Sgs-Thomson Microelectronics S.R.L. Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192067A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Erasable and programmable read only memory unit
US4516313A (en) * 1983-05-27 1985-05-14 Ncr Corporation Unified CMOS/SNOS semiconductor fabrication process
DE3575813D1 (en) * 1984-05-07 1990-03-08 Toshiba Kawasaki Kk METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH A GATE ELECTRODE STACK STRUCTURE.
US4754320A (en) * 1985-02-25 1988-06-28 Kabushiki Kaisha Toshiba EEPROM with sidewall control gate
FR2583920B1 (en) * 1985-06-21 1987-07-31 Commissariat Energie Atomique METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT, ESPECIALLY AN EPROM MEMORY COMPRISING TWO DISTINCT ELECTRICALLY ISOLATED COMPONENTS
IT1191558B (en) * 1986-04-21 1988-03-23 Sgs Microelettronica Spa MOS TYPE INTEGRATED SEMICONDUCTOR DEVICE WITH NON-UNIFORM DOOR OXIDE THICKNESS AND ITS MANUFACTURING PROCEDURE
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JPH0766946B2 (en) * 1989-03-31 1995-07-19 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2509697B2 (en) * 1989-04-28 1996-06-26 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2573432B2 (en) * 1991-02-18 1997-01-22 株式会社東芝 Method for manufacturing semiconductor integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51104276A (en) * 1975-03-12 1976-09-14 Hitachi Ltd HANDOTAISH USEKAIRO
JPS54137982A (en) * 1978-04-19 1979-10-26 Hitachi Ltd Semiconductor device and its manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2129181A (en) * 1934-04-11 1938-09-06 Carrie E Morse Liquid purification plant
IT1089299B (en) * 1977-01-26 1985-06-18 Mostek Corp PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
JPS5530846A (en) * 1978-08-28 1980-03-04 Hitachi Ltd Method for manufacturing fixed memory
DE3015615A1 (en) * 1979-04-27 1980-11-06 Maruman Integrated Circuits In Read only memory has two types of MOS elements - producing different information states with different threshold voltage values
JPS56108259A (en) * 1980-02-01 1981-08-27 Hitachi Ltd Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51104276A (en) * 1975-03-12 1976-09-14 Hitachi Ltd HANDOTAISH USEKAIRO
JPS54137982A (en) * 1978-04-19 1979-10-26 Hitachi Ltd Semiconductor device and its manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594170A (en) * 1982-06-30 1984-01-10 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS636155B2 (en) * 1982-06-30 1988-02-08 Mitsubishi Electric Corp
JPS60223945A (en) * 1984-04-21 1985-11-08 Shinryo Air Conditioning Co Ltd Blow-off port structure for clean room
JPS6238617B2 (en) * 1984-04-21 1987-08-19 Shinryo Air Cond
US4780424A (en) * 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US5330938A (en) * 1989-12-22 1994-07-19 Sgs-Thomson Microelectronics S.R.L. Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation

Also Published As

Publication number Publication date
GB2080024A (en) 1982-01-27
DE3124283A1 (en) 1982-06-16

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