CA1164107A

CA1164107A - Method for making a semiconductor device

Info

Publication number: CA1164107A
Application number: CA000368125A
Authority: CA
Inventors: Tsiu C. Chan; Charles B. Johnson; Ian A. Young
Original assignee: Mostek Corp
Current assignee: CTU of Delaware Inc
Priority date: 1980-01-11
Filing date: 1981-01-08
Publication date: 1984-03-20
Also published as: EP0043372A1; WO1981002074A1

Abstract

Abstract:
A method for forming a semiconductor device includes the steps of forming an element site on a surface of a semiconductor substrate. A dopant is introduced into the semiconductor substrate at the element site to form a region. An oxide layer is formed over the element site.
A layer of polysilicon is formed over a portion of the element site. An oxide layer is formed over the poly-silicon layer and the doped portion of the substrate exposed at the element site.

Description

B12689 ' . ~ .

~641~7 METHOD FOR MAKING A SEMICONDUCTOR DEVICE

TECHNICAL FIELD
This invention relates to a method for fabricating a semiconductor device, and more particularly to a capacitor and method for fabricating a capacitor having a high capacitance per unit area to increase packing densities on a semiconductor chip.

~l6aR~V7 , BACKGROUND ART
It is frequently necessary to fabricate capacitor type devices for use in integrated circuits. One such application is a switched~capacitor filter for simulating capacitor and inductor elements in passive ladder filters for use in voice-band systems re~uiring prec~s'ion high-order filters. Such capacitors must be fabricated to approximate the operating characteristics of true metal double plate capacitors having low voltage coefficients. Additionally, due to the size constraints of integrated circuits, the size of capacitors fabricated in semiconductor devices is a critical element in the design considerations. Therefore, capacitors must have high capacitance per unit area to reduce the area necessary to fabricate such capacitors.
Previously developed fabrication techniques for fabricating capacitors have included an N-channel meta]
gate and CMOS processes in which a diffusion layer for~ed one plate of the capacitor, a metal layer formed 2J the other plate and silicon dioxide (oxide) formed the dielectric. Another previously developed capacitor fabrication technique using a silicon gate process utilized two levels of polysilicon sandwiched around an oxide layer such that the layers of polysilicon formed the plates of the capacitor and the oxide layer formed the dielectric. The silicon gate process utilizing two levels of polysilicon suffers from the inability to form oxide grown on polysilicon that is low in defect density. The configuration where polysilicon overlaps polysilicon creates poor yields in the fabrication of such capacitors and additionally, the process is more difficult to control. Minimization of defects in the oxide lay~r sandwiched between the two levels of polysilicon requires the use of a thicker oxide layer which decreases the capacitance per unit area and which in turn means that larger die siæes are necessary with this type of fabrication.

.. ~

7 `'-A need has thus arisen for a process for the fabrication of a low voltage coefficient capacitor in a semiconductor device in which the capacitance per unit area is high to per~it small die size in the fabrication process. A need has further arisen for a fahrication process in which control of for~ation of an oxide layer forming the dielectric of a capacitor is possible to increase the capacitance per unit area while producing higher yields in the fabrication process. A
need'has further arisen for a fabrication process for forming a capacitor in a seniconductor device together with other semiconductor elements in an efficient process.

` 11641~7 DISCLOSURE OF THE INV~NTION
In accordance with the present invention, a capacitor and fabrication process is provided for fabrication of a capacitor in a semiconductor substrate which su~stantially eliminates the problems heretofore associated with the fabrication of capacitors including low capacitance per unit area and excessive size requirements.
In accordance with the present invention, a method for fabricating a semiconductor device comprises the steps of forming an element site on a surface of a sericonductor substrate. The method further includes intro~ucin~ a do~ant in field areas adjacent the element site. A field oxide is grown a~ove the field areas. A donant is diffused into the semiconductor substrate at the element site. An oxide layer is formed over the element site.
A layer of polysilicon is then formed to cover a portion of the element site. A laver of oxide is for~ed over the polysilicon layer and the doped portions of the substrate exposed at the element site.
In accordance with another aspect of the ~resent invention, a capacitor is provided. The ca~acitor is formed on a semiconductor substrate havina a surface defining a site for the capacitor. A dopant area is disposed in the substrate immediatelv below the surface of the site. An insulatinq layer is disposed on the surface of the substrate above the dopant area. The capacitor of the present invention further includes a layer of polvsilicon disposed on the insulating layer.
In accordance with yet another aspect of the present invention, a method for forminq a semiconductor device comprises the steps of formin~ first and second element sites on a surface of a semiconductor substrate. A
dopant is implanted in field areas adjacent the element sites. Field oxide is grown above the field areas. A
layer of polysilicon is for~ed to cover a portion of ~164~7 the first element site. A dopant is introduced into the substrate at selected portions of the first element site not covered by the layer of polysilicon and into the entire second element site. An oxide layer is formed over the layer of polvsilicon at the first element site and over the entire second element site. A layer of polvsilicon is formed to cover a portion of the second element site. An oxide layer is formed over the poly-silicon layers and the doped portions of the substrate ln exposed at the element sites. Contact windows are opened to expose a selected area of the doped areas of the substrate at the element sites and the lavers of poly-silicon at the element sites. Contacts are then formed in the windows. The element formed at the first element site comprises a field-effect transistor and the element formed at the second element site comprises a capacitor.

~16~ 7 BRIEF DESCRIPTION OF DRA~INGS
For a more complete understandinq of the present invention and for further objects and advantaqes thereof, reference will now be made to the following Detailed Description ta~.en in conjunction with the accompanyinq Drawings in which:
FIGURÆS 1-24 are schematic sectional views illustrating portions of an integrated circuit device of the present invention at various stages in a process for ma~ing the device;
FIGURE 25 is an enlarged view of a representative portion of FIGURE 24;
FIGURE 26 is an enlarged view similar to the view of FIGURE 25 illustrating a succeedinq step in the process; and FIGURE 27 is a schematic sectional view illustratin~
the device of the present invention at a final stage in the process.

~ ' ~1641~7 DETAILED DESCRIPTIOM
Referring to FIGURE 1, there is shown a schematic cross-section of a portion of an integrated circuit device of the present invention, generally identified by the numeral 10, at an early stage in a man~facturing process. The device 10 comprises a substrate~2 which is typically monocrystalline silicon of a conventional crystal orientation known in the art. Many features of the present invention are applicable to devices employing semiconductor materials other than silicon as will be appreciated by those skilled in the art. The substrate 12 may be either P-type or N-type; however, for purposes of this illustrative embodiment, P-type conductivity is employed, a preferred resistivity being about 5 to 25 ohm-cm in the substrate 12. Thermally grown on top surface 14 of the substrate 12 is a thermal oxide layer 16, having a preferred thickness of about 600 Angstroms. A silicon nitride layer 18, having a preferred thickness of about 600 Angstroms, is deposited on thermal oxide layer 16 in a reactor in a known manner.
A polysilicon top layer 20 of polysilicon having a thickness of about 1000 Angstroms is deposited on silicon nitride layer 18 using known deposition techniques.
The device 10 is then exposed to an oxidizing ambient preferably in steam between about 900C to 1000C for a sufficient period of time to completely oxidize the polysilicon top layer 20 of FIGURE 1, thereby producing a polyoxide layer 22 as shown in FIGURE 2.
The polyoxide layer 22 is about 2000 Angstroms thick, which is about twice the thickness of the original polysilicon top layer 20 due to growth during oxidation.
Referring to FIGURE 3, representative portions of device 10 are shown after several intermediate steps have been performed. While two distinct component segments or element sites 24 and 26 are explicitly 1~6~7 illustrated in FIGURE 3, it is to ~e understoo~ that they are representative of a great many similar sites (not shown) wherein similar elements are simultaneously produced in accordance with the description of the 5 inventive process which follows. At element site 24, a capacitor is fabricated while at ele~ent site 26, a transistor device is fabricated. At both element sites 24 and 26, photoresist patterns 28 and 30 have been deposited on polyoxide layer 22 using standard photomasking techni~ues, after which the un~asked portions of polyoxide layer 22 are etched away usin~ an etchant which selectively attacks oxide thereby leaving polyoxide portions 32 and 34 as shown.
Following the etchin~ step, an ion implant step is performed in a known manner as indicated by the arrows, preferably using boron, to produce P+ re~ions 3fi, which penetrate to a depth of about 2nnn Anastroms in the portions of the substrate 12 not covered bv polyoxi~e portions 32 and 34, also referred to as the "field area"
of the device 10. The ener~y of the ions is selected so as to penetrate onlv through the portions of thermal oxide layer 16 and silicon nitride layer 18 not covered bv photoresist patterns 28 and 30 and ~olyoxide portions 32 and 34. An intensity of about 4.0 x 1013 boron ions/cm2 is preferably used in accordance with known techniaues as, for example, by means of the techniaues described in U.S.
Patent No. 3,898,105, hereinafter cited as r~ai et al~
It is preferred that P+ reqions 36 have a resistivity of about one ohm-cm in the areas of hiahest impurity concen-tration in the final device.
Next, as illustrated in FIGURE 4, the photoresistpatterns 28 and 30 are removed and the portions of the silicon nitride layer 18 not covered by the polyoxide portions 32 and 34 are selectively etched awaY using known techniques, thereby leavina nitride portions 38 and 40.

'; 116~1~7 Referring to FIGURE ~, an oxidation is performed in steam for about 6 to 8 hours at approximately lOOO~C, which results in the growth oE a relatively thick "isoplanar field oxide" layer 42, preferably of about 14,000 Angstroms in thickness, in the portions of the substrate 12 not covered by nitride portions 3~ and 40.
The isoplanar field oxide layer 42 penetrates into the substrate 12 to a depth of about 7000 Angstroms, the oxidation process driving the boron implant regions 36 to a greater depth therebelow. The P+ regions 36 permit the use of a thinner isoplanar field oxide layer 42 by reducing the resistivity thereunder.
Next, as illustrated in FIGURE 6, the polyoxide portions 32 and 34 are removed by etching using hydrofluoric acid in a known manner, which also slightly reduces the thickness of the isoplanar field oxide layer 42. Then, the nitride portions 38 and 40 and the remaining portions of thermal oxide layer 16 are renioved using conventional techniques.
Various surface "cleaning" steps are ordinarily used at this point to remove surface damage in the active area of the device. "Active area" means those portions of the device where no field oxide has been grown. It has been found, however, that merely cleaning by etching some of the substrate 12 along top surface 14 is inadequate to remove silicon nitride contamination which exists along edges 44 of the substrate 12 near the isoplanar field oxide layer 42. Small amounts of silicon nitride from nitride portions 38 and ~0 are transported to the top surface 14 at the edges of the isoplanar field oxide layer 42 incident to the chemical process which produces the isoplanar field oxide layer 42. Accordingly, an oxidation step is performed, preferably in an ambient atmosphere of hydrogen chloride and oxygen, to produce oxide layers 46 and 48 as shown in FIGURE 7, thereby 1~L64~)7 gathering the nitride impurities at edges 44 from the substrate 12 into the oxide as it grows. A thickness of about 300 Angstroms is sufficient for oxide layers 46 and 48, with a preferred thickness being between 300 and lO00 Angstroms.
Next, the oxide layers 46 and 48 are etched away to produce the structure of FIGURE 8. It will be appreciated by those skilled in the art that good surface conditions are important to the operation of field-effect device elements, and particularly in the channel of an enhancement mode FET. The oxidizing and etching steps of FIGURES 7 and 8 are effective to remove surface damage (generally occurring in the top 20 to 30 Angstroms of the substrate 12) as well as the silicon nitride contamination, thereby providing the clean, impurity-free top surface 14 shown in FIGURE 8.
As a result of the successive etching s~ps to remove thermal oxide layer 16, polyoxide portions 32 and 34, and oxide layers 46 and 48 in the steps shown from FIGURE 5 through FIGURE 8, the isoplanar field oxide layer 42 is somewhat reduced in thickness. At the process stage shown in FIGURE 8, the field oxide has an overall thickness of about 10,000 Angstroms, with about 7000 Angstroms extending to a level below the level of top surface 14 and about 3000 Angstroms extending above the level of top surface 14.
Next, thermal oxide layers 50 and 52 are grown to a thickness of about 900 Angstroms as shown in FIGURE
9. A light dose boron ion implantation is then performed using known techniques as indicated by the arrows for purposes of threshold voltage adjustment of the field-effect elements which will be formed subsequently in element sites 24 and 26.

~164~07 Now referrina to ~IGUR~ 10, in accordance with the present invention, a first deposition of polysilicon is deposited to subsequently form the gate of a transistor to be subsequentlv described fabricated at element site 26. Polysilicon layer 54 is deposited as shown over the entire device 10 to a thickness of about 500n`Angstroms using known techniques.
Next, a top portion of polvsilicon laver 54 is oxidized to produce polyoxide layer 56 sho~n in ~IGUR~ 11.
Polydxide layer 56 has a preferred thickness of about 1000 Angstroms, the formation of which causes a correspondin~ reduction in the thickness of polysilicon layer 54 to about 45nn Angstroms.
FIGURE 12 illustrates device ln after maskinq and etching steps have been performed wherein photoresist pattern 60 is formed, and the portions of polvoxide layer 56 not covered hv photoresist pattern fin are etched away leaving polyoxide portion 64.
Referring to FIGURE 13, the photoresist pattern 60 has been removed leaving the polvoxide portion fi4 as a mask for etching away portions of polysilicon layer 54.
At similar sites of the device 10 of which element site 26 is representative, a similar ~olvoxide mask also exists so that etching produces a plurality of separate polv-silicon layers in the device ln of which polysilicon layer68 is representative. Polysilicon laver 6~ overlies a center portion of thermal oxide layer 52 in the element site 26 as shown in FIGURE 13.
The use of polyoxide ~ortion 64 as a ~ask for etching the un~erlyinq polysilicon laver 54 produces a highlv regular layer having a slower, more controllable etch rate. Such properties of polyoxi~e ena~le a high degree of mas~ definition to be carried throuah from the photo-resist pattern (layer 60 in FIGURE 12~ to the polyoxide portion (la~er 64 in FIGURE 13). The high dearee of mask definition is further carried through in the formation of ~L641~)7 POlysilicon layer 68. The polysilicon layer 68 will be seen later in the process to further serve as a mask for etching the underlying thermal oxide layer 52, thereby aligning itself over a channel region of a field-effect transistor.
Referring to FIGURE 14, an etch is performed to remove polyoxide portion 64, thermal oxide layer 50 and selective portions of thermal oxide layer 5~. Polysilicon layer 68 serves as a mask for etching thermal oxide layer 52, leaving a portion 52a of thermal oxide layer 52.
Thereafter, an N-type dopant, preferably phosphorus, is diffused using known techniques whereby thermal oxide layer portion 52a acts as a diffusion mask in producing N+ regions C, S and D in substrate 12, to a depth of about 15,000 Angstroms below top surface 14.
Alternatively, an ion implantation technique can be utilized to introduce the dopant into substrate 12 at element site 24 to produce region C. The N-type dopant also dopes polysilicon layer 68 to become highly conductive. The C region forms a first capacitor plate of the present capacitor fabricated at element site 24.
The D region forms the drain and the S region forms the source of the transistor device fabricated at element site 26. In an alternate embodiment using an N-type substrate, a P-type diffusion, typically using boron, would be performed at this stage to produce the complementary conductivity-type structure of that shown herein.
An oxidation step is now performed on the structure of FIGURE 14 to cover the exposed edges and top of polysilicon layer 68 and top surface 14 with thermally grown oxide as shown in FIGURE 15. Thermal oxide layer portion 52a remains at a thickness of about 900 Angstroms, while uncovered thermal oxide portions 70 and 72 increase in thickness to about 200 to 500 Angstroms. Thermal oxide portion 70 forms the capacitor dielectric for the capacitor fabricated in accordance with the present invention at element site 24. Thermal oxide portion 70, 1~6~7 since it is fahricated directly on substrate 12 can be made thinner and be of a high ~uality. Beinq thinner, thermal oxide portion 70 forms a dielectric that has a hiqh capacitance per unit area to permit the present capacitor to be fabricated in a smaller area resultinq in greater packing densities.
A new polysilicon layer 74 constitutinq a second deposition of polysilicon is now deposited over the device 10 as sho~n in FIGURF 16 using known deposition techniques in similar fashion to the deposition step of FIGURE 10. The polysilicon layer 74 has a preferred thickness of about 4noo Anqstroms.
Next, an oxidation of polysilicon laver 74 is performed to produce ~ ~olyoxide layer 76 having a thickness of about 1000 Angstroms as sho~n in FI~URE
17. The oxidation reduces polvsilicon layer 74 to a thickness of about 350n ~nqstroms.
Now referring to FI~,URE lR, the device 10 is shown after a photoresist pattern 78 has been used to mask polyoxide layer 76, which is etched away entirely at element site 26 and partially at element site 24. The remaining polyoxide layer 76 overlies both a lower portion 80 and an upper portion 82 of polvsilicon layer 74 at element site 24.
Referring to FI~URF 19, the photoresist pattern 7~
has been removed and the remaining polyoxide laver 76 has been used as a mask to etch polysilicon layer 74, thereby removing polysilicon la~er 74 entirely fro~ element site 26 and partially from element site 24 to produce the structure sho~Jn such that the remaining ~ortion of polysilicon layer 74 forms the second plate of the capacitor fabricated using the present process.
It will be seen that the process steps for producin~
the second pol~silicon layer 74 as illustrated in FIGURES
17-19 are essentially the same, aside from thickness variations, as the process steps for producing the first polysilicon layer fi~ as illustrated in FI~UR~S 10-13, "

~ 4~)7 except that polysilicon layer 74 remains undoped at the stage of the process shown in FICURE 19. For purposes of this specification, the term "undoped" means "essentiallv free of conductivity affecting impurities" such as phosphorus (N-type~, boron (P type) and their known functional e~uivalents.
It will also be appreciated that the arrangement of polysilicon laver 74 enables capacitive elements of the type sho~n in element si~e 24 to be arranged in a densé manner in device 10. In particular, by overlapping the isoplanar field oxide layer 42 with polysilicon laver 74 r interconnections between adjacent cells (not shown) are facilitated, and the formation of contacts in subsequent steps is not a li~iting factor in choosing the amount of active top surface area 14 allocated to ele~ent site 24.
Referring to FIGUR~ 20, an etch is performed which selectively removes a portion of thermal oxide portion 70 to ex~ose a portion of top surface 14 in the area of element site 2~ not covered by polysilicon layer 74 and removes thermal oxide portion 72 to expose portions of top surface 14 in the area of element s.ite 26 not covered by polysilicon layer 68. Thereafter, phosphorus is diffused into the top of polysilicon layer 74, as indicated by the stippling, which causes polysilicon layer 74 to be heavilv doped N-type and thus highly conductive. In an alterna-tive embodiment using an N-tvpe substrate, a P-type diffusion, typically using boron, would be performed at this stage to produce the complementary conductivity-type structure of that shown herein.
Referring to FIGURE 21, the device 10 is placed in a furnace with dry oxygen or steam at about gn~c to 1000C so that oxide layers of about 2000 Angstro~s are grown over the various polysilicon layers 68 and 74 as indicated by numerals 94, and over the various ~+ regions, C, S and D in the substrate 12 as indicated by numerals 96.
, .

; ~641~ ' Referring to FIGURE 22, an oxide layer 98 of "high temperature" undoped oxide is deposited, preferablv usinq SiH4 and CO2 in a known manner, at a tem~erature between 600C and 1000C to a thickness of preferably about 6000 Angstroms.
Referring to FIG~RE 23, a photoresist mask lOn is then formed over deposited oxide layer 98. Next, contact windows 102 are opened by etching through the portions of oxide layer 98 not covered by photoresist mask l~n, and continuing to etch down through the underlying polyoxide layer 94 and thermal oxide layer 96.
Next, as illustrated in FIGUR~ 24, the photoresist mask 100 is removed, and a stabilization step is performed, preferably using a phosphorus diffusion, as indicated by the stippling along the exposed oxide surfaces. As shown in FIGURE 25, the phosphorus stabilization has the effect of ~roducing very thin oxide layers 104 on exposed silicon surfaces (explicitlv shown by way of example in FIC.~RE 25) which are approximately 20 to 100 Angstroms thick.
It is convenient to getter the device 10 concurrently with stabilization, which may be achieved by covering all but the backside, the botto~ surface of the substrate 12 with oxide thereon tnot shown), with photoresist after opening contact windows 102, then stripping the bac~.side down to clean silicon. Sta~ilization then proceeds as described in the preceding paraqraph by removing the photoresist and exposing the device 10 to a phosphorus diffusion, which getters metallic impurities to the 3n backside, thereby favorably reducing leakage current.
After the phosphorus stabilization step, it is necessary to reopen contact windows 102 through oxide layers 104. A photoresist layer (not shown) is reapplied~
using the same mask registration which produced photo-resist mask lnO. Then, oxide layers 104 are etchedthrough to the underlying silicon to reopen the contact windows 102, and the photoresist is removed to produce ~16411~7 contact windows 102, typically illustrated by FIGURE 26.
The contact window opening 1~2 at top surface 14, shown in FIGURE 26, may be controlled to less than 5 microns in diameter.
Finally, a metalliæation process is used to form contacts 106, 108, lln, 112 and 114 in the contact windows 102 which yields the device structure 10 shown in FIGURE
27. The contacts are preferablv formed by vacuum deposition of aluminum, photomasking portions of the aluminum, and etching the unmasked portions with etchants which selectivelv attac}; the aluminum but not the under-lying oxide layer 98.
Those skilled in the art will reco~nize the utility of the element structures shown in FIGUR~ 27, wherein element site 24 serves as a capacitor and the element site 26 serves as a field-effect transistor. In particular, element site 26 is an N-channel enhancement mode EFT
having a self-aligned silicon gate similar to that which is described in Mai et al., cited ahove, ~herein contact 20 112 serves as a aate, contacting polysilicon layer 68 and contacts 110 and 114 contact reqions S and D forrin~
the source and drain of the FET. The present invention may also be applied to make N-channel depletion mode FETs as well as both modes of P-channel FE~s by modification of the process steps specifically recited herein in accordance with the teachings of Mai et al.
Element site 24 is a capacitor wherein contact lOfi serves as a top plate contact to polysilicon laver 74 and contact 108 serves as a bottom plate contact to diffused region C. ~he operation of a capacitor such as the capacitor fabricated at ele~ent site 24 of FIGURE
28 is known in the art. In circuit analogv, a capacitor is formed by thermal oxide portion 70 servina as a dielectric between the polysilicon layer 74 and N~ reaion C.
It therefore can be seen that the present process of manufacturing a low volta~e coefficient capacitor in ~6~07 . .

a semiconductor suhstrate provides for a capacitor having a high capacitance per unit area ~hile simultaneously requiring a small area for fabrication. The method of the present invention involves a process of minimal complexitv to result in high vields in fabrication of the capacitor of the present invention. Since th'e dielectric element of the capacitor is fabricated directly on the semiconductor substrate and not on a layer of polysilicon, the dielectric la,ver is of good auality and uniform in struCture, such that a thinner dielectric layer can be utilized than with previously developed capacitor fabrication techniques to thereby achieve a ca~acitor having increased capacitance per unit area fahricated using the present invention.
Whereas the ~resent invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims

CLAIMS:

1. A method for forming a semiconductor device comprising the steps of:
forming an element site on a surface of a semi-conductor substrate;
implanting a dopant in field areas adjacent the element site;
growing a field oxide above the field areas;
introducing a dopant into the semiconductor substrate at the element site;
forming an oxide layer over the element site;
forming a layer of polysilicon to cover a portion of the element site; and forming an oxide layer over the polysilicon layer and the doped portions of the semiconductor exposed at the element site.

2. The method of Claim 1 wherein the step of introducing a dopant into the semiconductor substrate at the element site forms a plate of a capacitor at the element site.

3. The method of Claim 1 wherein the step of introducing a dopant into the semiconductor substrate comprises diffusing the dopant.

4. The method of Claim 1 wherein the step of introducing a dopant into the semiconductor substrate comprises implanting the dopant.

5. The method of Claim 1 wherein the step of forming an oxide layer over the element site forms a dielectric of a capacitor at the element site.

6. The method of Claim 1 wherein the step of forming a layer of polysilicon to cover a portion of the element site forms a plate of a capacitor at the element site.

7. A method for forming a semiconductor device comprising the steps of:
forming first and second element sites on a surface of a semiconductor substrate;
implanting a dopant in field areas adjacent the element sites;
growing field oxide above the field areas;
forming a layer of polysilicon to cover a portion of the first element site;
introducing a dopant into the substrate at selected portions of the first element site not covered by the layer of polysilicon and into the entire second element site;
forming an oxide layer over the layer of poly-silicon at the first element site and over the entire second element site;
forming a layer of polysilicon to cover a portion of the second element site;
forming an oxide layer over the polysilicon layers and the doped portions of the substrate exposed at the element sites;
opening contact windows to expose a selected area of the doped portion of the substrate at the element sites and the layers of polysilicon at the element sites; and forming contacts in the windows.

8. The method of forming a semiconductor device of Claim 7 wherein the step of introducing a dopant into the semiconductor substrate at the second element site forms a plate of a capacitor at the second element site.

9. The method for forming a semiconductor device of Claim 7 wherein the step of forming an oxide layer over the second element site forms a dielectric of a capacitor at the second element site.

10. The method for forming a semiconductor device of Claim 7 wherein the step of forming a layer of polysilicon to cover a portion of the second element site forms a plate of a capacitor at the second element site.

11. The method for forming a semiconductor device of Claim 7 wherein the step of introducing a dopant into selective portions of the first element site forms a drain and a source of a field-effect integrated circuit element.

12. The method for forming a semiconductor device of Claim 7 wherein the step of forming a layer of polysilicon to cover a portion of the first element site forms a gate of a field-effect integrated circuit element.

13. A method for forming a semiconductor device comprising the steps of:
forming a thin oxide layer on a silicon semi-conductor substrate;
forming a silicon nitride layer on the thin oxide layer;
depositing a layer of polysilicon on the silicon nitride layer over portions of the substrate to define first and second element sites;
implanting a dopant in field areas adjacent the element sites;
growing field oxide areas above the field areas;
exposing the silicon substrate surface at the element sites;
forming an oxide layer over the element sites;
depositing a first layer of polysilicon on the oxide layer and the field oxide;
oxidizing a top portion of the first layer of polysilicon producing a polyoxide layer;
etching selected portions of the first polysilicon layer thereby forming a first area of polysilicon at the first element site and completely etching the polysilicon layer covering the second element site;
etching the remaining portion of the polyoxide layer;
introducing a dopant into the substrate at selected portions of the first element site not covered by the area of polysilicon and into the entire second element site;
forming an oxide layer around the area of poly-silicon at the first element site and over the entire second element site;
depositing a second layer of polysilicon over the entire surface of the semiconductor device;
oxidizing a top portion of the second layer of polysilicon to produce a polyoxide layer;
etching selective portions of the second poly-silicon layer thereby forming an area of polysilicon at the second element site and completely etching the second poly-silicon layer covering the first element site;
forming an oxide layer over the areas of poly-silicon and the doped portions of the substrate at the element sites;
opening contact windows to expose selective areas of the doped portions of the substrate and the areas of poly-silicon at the element sites; and forming contacts in the windows.