JPH0450754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device. In particular, the present invention relates to a method of manufacturing a 1-transistor type nonvolatile semiconductor memory device that is electrically rewritable and has a nondestructive readout method.

(2) Background of the technology Current non-volatile semiconductor memory devices are composed of two transistors: a selection transistor and a memory transistor, and the area of the memory cell section is required to be at least the size of two transistors. This was a major obstacle to progress. Therefore, a one-transistor nonvolatile semiconductor memory device has been proposed, and a floating gate structure shown in FIG. 1 has been proposed as one method for realizing this system.

In the figure, 1 is a semiconductor substrate, 2 and 3 are sources and drains, 4 is an insulating layer,
5 is a floating gate made of metal;
6 is a gate electrode. In this structure, writing is performed by applying a relatively high voltage to the gate electrode 6 to accumulate charge in the floating gate 5 and raising the threshold voltage, and reading is performed between the source 2 and drain 3. This is done by applying a predetermined voltage and identifying the element whose threshold voltage has increased. On the other hand, in the case of erasing, an operation completely opposite to that of writing is performed to restore the threshold voltage. The voltage applied between the source and drain for the above reading may be about 3 to 5 [V], but the voltage used for writing and erasing is, for example, 20V.
It is relatively high at about [V] or more. but,
It is desirable that this value be as small as possible.

What is essential for stable operation of such a 1-transistor type nonvolatile semiconductor memory device is the change in threshold voltage (hereinafter referred to as △
It is called Vth margin. ) is large. The read voltage must be set between the threshold voltage in the state where information is written and the threshold voltage in the state where information is erased, so △
This is because the larger the Vth margin, the lower the possibility of malfunction.

(3) Conventional technology and problems It has the above floating gate structure.
Non-volatile semiconductor memory devices using MOS transistors can increase the △Vth margin to some extent, but in order to avoid pinholes etc., a tunnel oxide film interposed between the substrate and the floating gate is required. It has the disadvantage that it cannot be thinned beyond a certain limit.

In addition, as another non-volatile semiconductor memory device, MIS
2. Description of the Related Art Some transistors have a structure in which an insulating layer is interposed between a gate electrode made of metal and a semiconductor substrate. This insulating layer is classified into various types depending on the material that makes up it, and currently it is classified into MNOS.
(metal nitride oxide semiconductor) structure has become mainstream. Figure 2 shows this
An example of the basic structure of an MNOS transistor is shown.
In the figure, 11 is a silicon (Si) substrate,
12 and 13 are sources and drains, 14 is an insulating layer made of silicon dioxide (SiO ₂ ),
17 is an insulating layer made of silicon nitride (Si ₃ N ₄ ), and 16 is a gate electrode made of metal.
The operating method is similar to the above-mentioned nonvolatile semiconductor memory device using a MOS transistor with a floating gate, in which charge is accumulated in a silicon nitride (Si ₃ N ₄ ) layer 17 having a trap instead of a floating gate. Ru. However, in the MNOS structure, it is not easy to reduce the write voltage to about 10 [V] or less, so recently, the MNOS
There is an example of a structure in which the upper part (gate electrode side) of a thin silicon nitride (Si ₃ N ₄ ) layer is oxidized to form SiO ₂ , that is, a MONOS structure, which aims to reduce the write voltage by about 8 [V]. A write voltage of
Since the voltage is as small as about 2.5 [V], when applied to a 1-transistor, there is a possibility of malfunction during reading. In addition, process disadvantages such as difficulty in forming a thin film of silicon nitride (Si ₃ N ₄ ) and control of its surface oxidation are also unavoidable disadvantages.

(4) Purpose of the Invention The purpose of the present invention is to eliminate these drawbacks. An object of the present invention is to provide a method for manufacturing a 1-transistor type nonvolatile semiconductor memory device that is a read method.

(5) Structure of the Invention According to the present invention, (a) forming an insulating layer 29 made of an oxide of a substance belonging to group A or group VA of the periodic table of elements on a semiconductor substrate 21; (c) patterning the insulator layer 29 and the conductor layer 26 into a desired shape; and (d) in a humidified oxygen atmosphere. A third insulating layer 31' is formed at the interface between the conductive layer 26 and the insulating layer 29 and at the interface between the insulating layer 29 and the channel layer 21 by performing oxidation treatment. first insulator layer 3
0', and (e) the step of forming the insulating layer 29
A method of manufacturing a non-volatile semiconductor memory device is provided, which includes the step of converting the insulating layer 29'' into a second insulating layer 29'' containing many traps by reducing the insulating layer 29''.

In order to achieve the above objectives and realize a gate structure with a low write voltage and a large △Vth margin, the material forming the gate insulating film must be a dielectric with a high dielectric constant. All you have to do is choose a material that will easily form a trap inside.

That is, in the layered structure of the gate insulating film, an oxide layer containing a large number of traps and having a high dielectric constant is used as the second insulating layer, and the upper and lower layers of this layer have a larger band gap to stabilize the accumulated charge. It is most effective when the structure is held between the first and third insulating layers having a small dielectric constant, and the manufacturing method for realizing such a structure is as follows. On a semiconductor substrate, for example,
After forming a second insulating layer made of an oxide of a substance from group A or group VA of the periodic table of elements,
A layer made of a conductor such as polycrystalline silicon (polySi) is formed, and the oxide layer of the above-mentioned A and VA group materials can serve as an introduction route for oxidized species in a wetO ₂ atmosphere. The body layer is oxidized to form third and first insulator layers made of oxide, and the second insulator layer is further oxidized with hydrogen (H ₂ ).
It is advantageous to generate a large number of traps by reduction in an atmosphere containing

In the above structure, the third insulating layer is for preventing charges tunneled through the first insulating layer from the channel layer from being discharged to the conductive layer during a write operation, that is, during charge injection. Both the first and third insulating layers have a charge retention function. The second insulating layer is related to the gist of the present invention and is realized, for example, by reducing tantalum oxide (Ta ₂ O ₅ ) with hydrogen (H ₂ ) to generate a large number of traps consisting of oxygen (O) vacancies. It is a dielectric layer that has a charge storage function. Although this dielectric layer cannot store as much charge as the floating gate described above, it can store much more charge than the MNOS structure, and this layer itself is a dielectric. This structure does not allow the movement of charges, so unlike floating gates, there is less possibility of leakage current occurring, and there is an advantage that the retention time is sufficiently long even if the first insulating layer is made thin. On the other hand, since the first insulating layer can be made sufficiently thin, it is possible to reduce the write voltage. That is, this gate structure has both the advantages of the floating gate structure and the MNOS structure.

Furthermore, we will discuss the properties that the insulator layer should have. FIG. 7 shows a band structure of a nonvolatile semiconductor memory device according to the present invention. In order to lower the write voltage, the first, second, and third insulating layers 73, 72, and 71 must be made as thin as possible, and in particular, the first and second insulating layers 71, 73 are dominated by Feurer-Nordheim tunnel current. It is formed so thin that it becomes visible.
Further, since the electric field is high in the third and second insulating layers 71 and 72, the Schottky effect must also be taken into consideration. Therefore, in order to achieve the object of the present invention, the relationships among the permittivity, electric field, band gap, and film thickness that affect the tunneling probability and the Schottky effect must be determined as follows:
The insulating layer must be considered. FIG. 7a shows a state in which no voltage is applied to the gate, and FIG. 7b shows a state in which a positive voltage is applied to the gate and electrons are injected from the semiconductor substrate 74 into the second insulating layer 72. Generally, the electric flux density D in a dielectric is D=ε・E
It is expressed by the formula (permittivity x electric field strength), and considering that when dielectrics are stacked and the electric flux density is constant, the electric field strength of each dielectric is inversely proportional to the dielectric constant. Electrons are injected into the insulating layer 73 and the third
The condition that can be stopped by the third insulating layer 7 is that the third insulating layer 7
The band gap of the first insulating layer 73 is larger than that of the first insulating layer 73, and furthermore, in order to hold the electrons injected into the second insulating layer 72, the band gap of the second insulating layer 72 is larger than that of the first insulating layer 73. is large (F ₁ ≧F ₃ >F ₂ ), and the dielectric constant of the third insulating layer 71 is made larger than that of the first insulating layer 73.
Increasing the electric field of the insulating layer 73 (ε ₁ ≧ε ₃ ),
At least one of making the thickness of the third insulating layer 71 thicker than that of the first insulating layer 73 (l ₁ ≧l ₃ )
is to be fulfilled. Furthermore, since it is better to lower the voltage applied to the second insulating layer 72 in order to lower the electron injection voltage, the dielectric constant of the second insulating layer 72 is made larger than the other two insulating layers to reduce the electric field (ε ₁ , ε ₃ <ε ₂ ), or by reducing the band gap of the first insulating layer 73 on the substrate side, ie, using a so-called glazed band gap, the write voltage can be lowered.

(6) Embodiments of the Invention A method for manufacturing a 1-transistor type nonvolatile semiconductor memory device according to an embodiment of the present invention will be explained below with reference to the drawings, and the structure and unique effects of the present invention will be clarified. do.

As an example, on a silicon (Si) substrate, a polycrystalline silicon (polySi) gate electrode, a first insulating layer made of silicon dioxide (SiO ₂ ), a second insulating layer made of tantalum oxide (TaxOy), Next, a manufacturing process for a structure having a third insulating layer made of silicon dioxide (SiO ₂ ) will be described. However, in Figures 3 to 6, A in Figure 8
-A cross section is shown.

Refer to FIG. 3. A layer (not shown) of silicon nitride (Si ₃ N ₄ ) is formed on a p-type silicon (pSi) substrate 21,
After patterning, a field insulating layer 28 made of silicon dioxide (SiO ₂ ) is formed in a desired region using a thermal oxidation method. Subsequently, after removing the silicon nitride (Si ₃ N ₄ ) layer by etching, tantalum (Ta) is etched using a sputtering method.
A tantalum oxide (Ta 2 O 5 ) layer 29 is formed to a thickness of about 440 Å by forming a tantalum oxide (Ta ₂ O ₅ ) layer 29 to a thickness of about 200 Å and oxidizing it by a thermal oxidation method at a temperature of 500 [°C] or less. to form.

See Figure 4 After forming a polycrystalline silicon (polySi) layer to a thickness of about 5000 Å on the tantalum oxide (Ta ₂ O ₅ ) layer 29 using chemical vapor deposition, the gate The tantalum oxide (Ta ₂ O ₅ ) 29 and the polycrystalline silicon (polySi) layer are selectively removed from the region excluding the region where the gate electrode 26 and the second gate electrode made of polycrystalline silicon (polySi) are formed.
Tantalum oxide (Ta ₂ O ₅ ) layer 2 becomes the insulating layer of
9'. Then, using these as a mask, ion implantation is performed to introduce arsenic (As) as an n-type impurity into the substrate 21 to form the source/drain, that is, the ground line diffusion layer 22 and the bit line diffusion layer 23. do.

See Figure 5. Next, oxidation is carried out for about 10 minutes in a wet O ₂ atmosphere at about 800 [°C]. Through this interfacial oxidation step, the exposed portion 30 of the substrate 21, the gate electrode 26,
31 is oxidized and the silicon region in contact with the tantalum oxide also becomes the tantalum oxide (Ta ₂ O ₅ ) layer 2.
9' serves as an introduction path for oxidizing species, and oxidation takes place.
A first insulating layer 30' and a third insulating layer 31' made of silicon dioxide (SiO ₂ ) are formed.

See Figure 6. Next, annealing is performed for about 20 minutes in a mixed gas of nitrogen gas (N ₂ ) containing 5% hydrogen gas (H ₂ ) by volume at a temperature of about 1000 [°C]. (Ta ₂ O ₅ ) layer 29' is reduced.
Many traps due to oxygen (O) vacancies are generated in the reduced tantalum oxide (TaxOy) layer 29''.The traps have the function of accumulating electric charge.

Note that in this step, the silicon (Si) of the gate electrode 26 and the substrate 21 is oxidized to some extent. This is thought to be due to a reaction between some of the oxygen (O) in tantalum oxide (Ta ₂ O ₅ ) and silicon (Si), but this phenomenon can be used to bond the conductive layer and the substrate. If oxidation is performed, the above temperature at 800 [℃]
The oxidation step in wetO ₂ can be omitted.
At the same time, the implanted arsenic (As) is diffused, but if this diffusion is to be increased, the time for the above-mentioned wetO ₂ oxidation may be shortened and the annealing time may be extended.

Subsequently, a silicon dioxide (SiO ₂ ) layer 28' is formed using a chemical vapor deposition method (CVD method), and a contact hole is formed on the gate electrode 26 using a known method. Al)
The word line 32 is formed by selectively forming the following layers.

FIG. 8 shows a plan view of a substrate of a one-transistor type nonvolatile semiconductor memory device manufactured by the above steps. In the figure, 28 is a field insulating layer, 26 is a gate electrode made of polycrystalline silicon (polySi), and 26' is a contact hole formed on the gate electrode 26. In addition, the area 23 surrounded by the dashed line B constitutes the bit line n.
A region 22, which is a type region and is surrounded by broken lines c, is an n-type region constituting a ground line. However, in this figure, the interlayer insulating layer 28' and aluminum (Al)
The word line 32 consisting of the above is omitted.

Furthermore, an equivalent circuit of the nonvolatile semiconductor memory device shown in FIG. 8 is shown in FIG. The operating principle of a one-transistor type nonvolatile semiconductor memory device according to an embodiment of the present invention will be described below with reference to this figure. In the figure, B ₁ , B ₂ , C ₁ , and C ₂ are bit lines and ground lines, respectively, and are connected to the sources and drains of transistors constituting each memory cell 41 to 46. Furthermore, D ₁ , D ₂ , and D ₃ are word lines connected to the gates of each transistor. Taking as an example a memory cell that can be operated with a bit line B ₁ , a ground line C ₁ , and a word line D ₁ , that is, the cell 41, first, when writing only to the cell 41, the word line line D ₁
Set to 10V and ground bit wire _B1 . By this operation, a write voltage of 10 [V] is applied to the gate of the cell 41, and electrons are transferred from the n-type region constituting the bit line to the second insulator made of tantalum oxide (TaxOy) in the gate part. It is injected into the material layer and accumulated. Note that in order to prohibit writing in the cell 43 connected to the same word line as the cell 41, the bit line _B2 of the cell 43 is kept at an open potential.
Further, in order to prevent electron injection from the ground lines in the cells 41 and 43, both the ground lines C ₁ and C ₂ are set to an open potential. Next, when reading the cell 41,
Set the word line _D1 to +3V and the bit line _B1 to +5 [V], and detect ON/OFF of the cell. That is, if electrons are accumulated in the gate, no current will flow between the source and drain, and if no electrons are accumulated, current will flow. According to the present invention, the △Vth margin is about 5 to 10 [V], which is much larger than the value of about 2.5 [V] achieved in the conventional technology, so the degree of freedom in setting the read voltage is increased. Larger, less chance of malfunction. Furthermore, cell 4
When erasing 1, the operation is completely opposite to that for writing. That is, the word line _D1 is grounded and the bit line _B1 is set to 10 [V]. As a result, the electrons accumulated in the gate are erased by tunneling to the n-type region constituting the bit line. At this time, other cells connected to bit line _B1 , namely cells 42, 44 and 4,
5, if information is written in these cells, if the word lines D ₂ and D ₃ are set to +5V to prevent erasure in these cells, the effective electron emission voltage will be 5V.
[V], and no tunnel will occur. Further, the ground lines C ₁ and C ₂ on both sides of the bit line B ₁ are kept at an open potential to prevent current from flowing to other cells.

The structure is realized through the above steps 1
- Transistor type non-volatile semiconductor RAM has a write voltage as low as 10 [V], and
The Vth margin is as large as about 5 to 10 [V], and the operation is stable and it effectively contributes to high integration.

The gist of the present invention is that the structure of the gate part is a conductive layer/first insulating layer/second insulating layer including a large number of traps/third insulating layer/semiconductor layer. In the above embodiment, the materials forming the gate part are polycrystalline silicon (polySi)/silicon dioxide (SiO ₂ )/tantalum oxide (TaxOy)/silicon dioxide (SiO ₂ )/
Although silicon (Si) was selected and the gate structure was made using silicon, it is not limited to this material.

(7) Effects of the Invention As explained above, according to the present invention, the write voltage is low, the △Vth margin is large, the operation is stable, electrical rewriting is possible, and the read method is non-destructive. 1-A transistor type nonvolatile semiconductor memory device can be manufactured.

[Brief explanation of the drawing]

FIG. 1 shows a floating gate that constitutes a conventional nonvolatile semiconductor memory device.
FIG. 2 is a cross-sectional view showing an example of the basic structure of a MOS transistor, FIG. FIG. 7 is a sectional view of the substrate after completion of the main steps in the method for manufacturing a 1-transistor type non-volatile semiconductor memory device according to an embodiment of the present invention.
A diagram showing the band structure of a non-volatile semiconductor memory device manufactured by carrying out the method for manufacturing a transistor-type non-volatile semiconductor memory device, FIG. 8 is a plan view of the substrate of the completed 1-transistor type non-volatile memory, and FIG. It is a circuit diagram showing the equivalent circuit. 1, 11, 21...Si substrate, 2, 12, 22...
...source/ground line diffusion layer, 3, 13,
23...Drain, that is, bit line diffusion layer,
4, 14... SiO ₂ insulator layer, 5... floating gate (metal), 6, 16... gate electrode,
17... Si ₃ N ₄ layers, 28, 28', 30, 31...
... ₂ layers of SiO, 29... ₅ layers of Ta ₂ O, 29'... ₅ layers of Ta ₂ O which will become the second insulator layer, 32... gate wiring,
That is, word line (Al), 26... gate electrode (polySi), 26'... contact hole formed in the gate electrode, 31'... third insulating layer (SiO ₂ ), 29''... 2 insulator layer (TaxOy),
30′...first insulator layer (SiO ₂ ), 41 to 46
...Memory cell.

Claims (1)

[Claims] 1. A step of forming an insulating layer 29 made of an oxide of a substance belonging to group A or group VA of the periodic table on a semiconductor substrate 21, and forming a conductive layer 26 on the insulating layer 29. a step of patterning the insulator layer 29 and the conductor layer 26 into a desired shape; and a step of forming the conductor layer 26 and the insulator layer 29 by performing oxidation treatment in a humidified oxygen atmosphere. A third insulating layer 31' and a first insulating layer 3 are provided at the interface and the interface between the insulating layer 29 and the channel layer 21, respectively.
0'; and a step of converting the insulating layer 29 into a second insulating layer 29'' containing many traps by reducing the insulating layer 29. Method of manufacturing the device.