JPS59124768A - Nonvolatile semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain the nondestructive type reading system 1-transistor type nonvolatile semiconductor memory device, writing voltage thereof is low, a DELTAVth margin thereof is large, operation thereof is stable and which can be rewritten electrically. CONSTITUTION:A layer consisting of silicon nitride (Si3N4) is formed on a P type silicon (psi) substrate 21, and removed through etching, and a tantalum oxide (Ta2O5) layer 29 is formed. A polycrystalline silicon layer is formed on said tantalum oxide (Ta2O5) 29 by using a chemical vapor deposition growth method, and removed selectively, and a gate electrode 26 consisting of polycrystalline silicon and a tantalum oxide layer 29' as a second insulator layer are formed. Ions are implanted, and a ground wire diffusion layer 22 and a bit wire diffusion layer 23 are formed. The tantalum oxide (Ta2O5) layer 29' also functions as an introducing path for oxidation seeds in a silicon region being in contact with tantalum oxide to cause oxidation, and a third insulator layer 30' and a first insulator layer 31' consisting of silicon dioxide (SiO2) are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same. In particular, electrical data can be transferred, the reading method is non-destructive, 1-transistor type non-instrument #L, conductive memory device and its manufacturing method, and 0. (2) Background of technology Current non-volatile A semiconductor memory device is composed of two transistors, a selection transistor and a memory transistor (1), and the area of the memory cell section is required to be at least the size of two transistors.
This was a major obstacle. Therefore, a one-transistor volatile semiconductor memory device has been proposed, and a floating gate structure shown in FIG. 1 has been proposed as one method for realizing this system.

In the figure, 1 is a semiconductor substrate (A1), 2.3 is a source/drain), 4 is an insulator layer, and 5 is a metal gate (A1), 6-digit gate. This is the gate electrode. In this structure, writing is performed by applying a relatively high voltage to the gate electrode 6, accumulating charge in the floating gate 5, and raising the threshold value t'.
For reading, a predetermined voltage F is applied between the source 2 and drain 3.
On the other hand, in the case of erasing, the operation is actually the exact opposite of the erase operation, and the threshold voltage is increased. For the above reading, Ex. 1. Source:
The voltage applied between 2247 and 2247 may be about 3 to 5 [■], but the voltage I+ used in the furnace for writing and erasing is good! 1 shoot, 20 (V) culm dust or more 〒 Relatively high. Only?
7. It is desirable that this value be as small as possible.

What is essential for stable tr operation in such a 1-transistor type nonvolatile semiconductor memory device is that the threshold voltage variation (hereinafter referred to as Δvth margin) accompanying write erasure is large. . Read.

The output voltage must be set between the threshold voltage in the state where information is desired and the long-term value voltage in the state where the information is erased; the larger the △vth margin, the more likely it will malfunction. There is a 〒 because there is little possibility of tr.

(3) Conventional technology and problems A non-volatile semiconductor memory device using an MO8 type transistor with a floating gate structure of
It is possible to increase the th margin to some extent, but in order to avoid the occurrence of pinholes etc., it is necessary to connect the board to the floating board7)? There is a disadvantage in that the tunnel oxide film interposed between the two layers cannot be made thinner than a certain limit.

In addition, as a non-volatile semiconductor memory device for IlIJ,
Some transistors have a structure in which an insulating layer is interposed between a gate electrode made of metal and a semiconductor substrate. This insulator layer is classified into various types depending on the material that makes up it, and currently the material used is MNOS (met-alnitri
This MNO is in the 0@2 diagram, where those with a
An example of the basic structure of an 8-type transistor is shown. In the figure, 11 is a silicon (Sl) substrate, 12.13 is a source/drain.
10 □) and I) are the insulator layers, 17 is silicon nitride (Si3N4'), and 1116 is the metal, and the gate electrode is 0.The operation method is the floating type as described above. It is similar to a nonvolatile semiconductor memory device using an MO8 type transistor with a gate.
Charges are stored in the silicon nitride (813N4) layer 7 with traps instead of floating gates. However, since it is not easy to lower the dent voltage of the MNO8 structure to about 10 [V] below IW, recently this MN
The soil part of the thin silicon nitride (Si3N4) layer with O8 structure (
This is an example of a structure in which the gate type rod side) is oxidized to create FliO□, that is, a MONO8 structure with a low t-included voltage. Although one drawback of the 2-transistor type non-volatile memory has been improved, the △vth margin is as small as Z5 [V], so when applied to a 1-transistor, there is a possibility of malfunction during output. have 9. Silicon (S)
Process disadvantages such as difficulty in forming a thin film of i3N4) and control of surface oxidation are also unavoidable.

(4) Purpose of the Invention The purpose of the present invention is to eliminate this drawback.
A 1-transistor type nonvolatile conductor memory device with low input voltage, large △vth margin, stable operation↑A), electrically rewritable, and non-destructive read/out method. It is about providing.

(5) Structure of the Invention According to the present invention, a semiconductor substrate, a first insulating layer disposed on the semiconductor substrate, and 1. a second insulating layer made of an oxide of a substance belonging to Group 1 VA or Group VA of the Periodic Table of Elements; a third insulating layer disposed on the second insulating layer; A non-volatile semiconductor memory device comprising: a third insulating layer, a gate electrode disposed on the third insulating layer; Oxides of substances belonging to I
) a step of forming an insulator layer on the insulator layer, a step of patterning the insulator layer and the conductor layer into a desired shape, and an oxidation treatment in a humid oxygen atmosphere. The interface between the conductor layer and the insulator layer and the interface between the aforementioned 1J insulator and the channel layer i? There is provided a method for manufacturing a non-volatile semiconductor memory device, comprising the steps of forming an oxide layer on the insulator 1-, and then reducing the insulator 1- of the above-described 1.

Achieving the above objectives, low backfilling voltage, and △v
In order to realize a gate structure with a large th margin,
The material forming the gate insulating film may be a dielectric having a high dielectric constant, and the dielectric may be a material that does not easily form traps inside.

That is, in the layered structure of the gate insulating film, an oxide R~ containing many traps and having a high dielectric constant is used as the second insulating layer, and the upper and lower layers of this layer have a large mant gap and are It is most effective when the first and third insulating layers, which have a small dielectric constant and which hold the electric charge stably, are sandwiched between them. As a manufacturing method, a second insulating layer made of, for example, an oxide of a substance of the TVA group or VA group of the Periodic Table of the Elements is formed on a semiconductor substrate, and then polycrystalline silicon (I) is formed. pol, ySi), etc., conductors IIf
The substrate and conductor layer are oxidized by forming a layer containing the above-mentioned TVA and VA group substances, and by utilizing the phenomenon that the oxide layer of the above-mentioned TVA and VA group substances can serve as an introduction path for oxidizing species in a Wθt○2 atmosphere. Advantageously, the third and first insulator layers are formed, and the second insulator layer is further reduced in an atmosphere containing hydrogen (N2) to generate a large number of traps.

In the above structure, the harmful insulating layer is separated from the channel layer in the injection operation, that is, during charge injection.
This is to prevent charges tunneled through the insulating layer from being discharged to the conductive layer, and both the first and third insulating layers have a charge retention function. The second insulating layer is inverted, tantalum oxide (Ta205).
) by hydrogen (N2) and oxygen (0)
(by generating a large number of traps consisting of vacant positions)
This is a dielectric layer that has a realized charge storage function. This dielectric layer cannot store as much charge as the floating gate described above, but in the MNO8 structure I),
It is possible to accumulate a much larger amount of charge), and since this waste itself is a dielectric, it does not allow charge Ffh, so it is not possible to generate leakage current like a floating gate. On the other hand, C has the advantage that the retention time is small even if the P edge layer is made thinner, and the insulating layer, which is harmful, can be made sufficiently wide, so it is possible to reduce the built-in voltage. In other words, such a gate structure is a structure that combines the advantages of the floating gate structure and the MNO8 structure described above.

Furthermore, the property γt of the P14 body layer will be described.

FIG. 7 shows a nonvolatile semiconductor memory device according to the present invention. In order to lower the write voltage, it is formed so thin that the Fowler-No-P-Heim tunnel N Mt becomes dominant. Also, the second harm, the second insulation Jv! 71.72
Since the electric field becomes high, the Schottky effect must also be taken into consideration. Therefore, in order to achieve the purpose of the present invention, it is necessary to consider the dielectric constant, electric field, non-p-gap, and N1 coefficient of the barrier, which affect the tunneling probability and the Schottky effect, for the 1.2.3 insulating layer. fret “I. @Figure 7 (a)
Figure 7(b) with no voltage applied to the gate.
is a state in which electrons are injected from the semiconductor substrate 74 into the second insulating layer 72 by applying a positive voltage to the gate. Generally, electric flux density in dielectric material D=ε・E (permittivity x electric field strength)
Equation 1 shows that when dielectrics are laminated, the electric flux density is constant), and considering that the electric field strength of each dielectric is inversely proportional to the dielectric constant, in the first insulating layer 73, The number of electrons injected and stopped by the harmful insulating layer is large at the top of the IC 73, and the second insulating layer 72 is further injected to hold the electrons injected into the second insulating layer 72. 8 seconds of insulating layer 73 is large (F1
≧F3〉'F2), ■ Dielectric constant of the second harmful insulating layer 73 I) Increase that of the second harmful insulating layer 71 to strengthen the electric field of the insulation layer 73 that attracts customers (ε, ≧83) , ■
The thickness of the second insulating layer 71 is set to 1 more than that of the third insulating layer 73.
At least one of the following conditions (/1≧/3) is satisfied. Also? 11; Since it is better to have a lower voltage applied to the second insulating layer 72 in order to lower the injection voltage, the R ratio of the second insulating layer 72 is set to 1. to reduce the electric field (ε1・ε3〈ε
2) Nonon P on the substrate side of the first P line layer 73
By using a so-called glaze P, F gap that reduces the gap, the voltage can be lowered.

(6) Embodiment of the Invention With reference to the drawings, an embodiment of the present invention will be described below. The structure and unique effects of the present invention will be explained below.

As an example, in 7, a polycrystalline silicon (PO17SI) gate electrode, a silicon dioxide (S
The first insulating layer consists of tantalum oxide (T
A manufacturing process for a structure having a second insulating layer made of silicon dioxide (S10□) and a third insulating layer made of silicon dioxide (S10□) will be described. However, FIGS. 3 to 6 show the A-A cross section of FIG.

Refer to FIG. 3. A layer (not shown) of sealed silicon (Si3N4) is formed on a p-type silicon (psi) substrate 21, and after chisel turning is performed, desired regions are formed using a thermal oxidation method. Silicon dioxide (S10□) l) Nullfield I
A β edge layer 28 is formed. Subsequently, the silicon 9ide (8
13N4) layer is removed by etching, and then sputtering is used to form tantalum (Ta) to a thickness of about 1200X, which is oxidized by a thermal oxidation method maintained at a temperature of 500C or less. /l/ (T a
205) J? ” 29 to a thickness of about 440 (s).

Figure 4. Teruichi says polycrystalline silicon (poly6) is grown on the tantalum oxide (Ta20.
1) After forming the layer to a thickness of about 5,000 (X), the above-mentioned tantalum oxide (Ta205) 29 and polycrystalline silicon (polySl) are added from the region excluding the gate region.
#11- is selectively removed to form a gate electrode WI26 made of polycrystalline silicon (1) and a tantalum oxide (T a 205 ) layer 29' which becomes a second P edge layer. After that, ion implantation is performed using the stiffener as a mask to introduce AS as an n-type impurity into the substrate 21, and form the source/drain, that is, the original line diffusion layer 2.
2 and the bit line diffusion layer 23. Refer to FIG. 5. Next, oxidation is performed for about 10 minutes in a wet 02 atmosphere of about 800 ('n). This process oxidizes I), the substrate 21, and the gate electrode. The exposed portions 30.31 of vjL26 are oxidized, and the silicon region in contact with the tantalum oxide is also oxidized because the tantalum oxide (Ta2 ("14.) layer 29' serves as an introduction path for the oxidized glaze, and silicon dioxide ( Si
A third insulating layer 30' and a first insulating layer 31' made of C2) are formed.

Next, FJ annealing is performed for 20 minutes in a mixed gas of nitrogen gas (N2) containing 5% hydrogen gas (N2) by volume percentage at a temperature of about 1,000 ('O).
12- Reduce tantalum oxide ('ra2o5)829'. A large number of traps are generated in the reduced tantalum oxide (TaxOy) layer 2 due to vacancies of acid salts (0). The trap has the function of accumulating charge.

t "Oh, in this process, the gate electrode 26 and the substrate 21
silicon (Sl) is oxidized to some extent. This is thought to be due to the reaction between some of the oxygen (0) in tantalum oxide (T a 20 y, ) and silicon (Sl). If the oxidation with the substrate is performed, the acid process in weto□ at 800[° C.] mentioned above can be omitted. Also, this and N
At 1:00, the ion-implanted arsenic (As) is diffused, but if this diffusion is to be increased, the above-mentioned wet02 oxidation time may be shortened and the annealing time may be extended.

Next, a silicon dioxide (S1O2) layer 28' is formed using a chemical vapor deposition method (OVD method), and a contact hole is formed on the gate electrode 26 using a known method. 1) Word lines 32 are formed by selectively forming layers such as A/).

FIG. 8 shows the plane of the substrate of the transilous non-volatile conductor measurement device manufactured by the above process. In the diagram? 8 field isolation @ layer 〒A number), 26 is polycrystalline silicon (I) gate voltage fi
There is a contact hole 26' formed on the gate electrode 26. Further, the region 23 surrounded by the dashed dotted line B is an n@ region constituting a bit line, and the region 22 surrounded by the broken lines C is an n type region constituting a ground line. (
I-1, l, In this figure, the interlayer insulating layer 28' and the word line 32 made of aluminum (AI) are omitted.

Furthermore, an equivalent circuit of the nonvolatile semiconductor memory device shown in FIG. 8 is shown in FIG. The operating principle of a one-transistor type nonvolatile semiconductor memory device according to an embodiment of the present invention will be explained below with reference to this figure. In the figure, B1
, B2 r 01 + 02 are the bit line and ground line, respectively.
A11. Each of the memory cells 41 to 46 is connected to the source and drain of the transistor. Also, T)
, , B2. B3 key P@〒A number) is connected to the gate of each transistor.

Now, the et line B1, the ground line C1, and the word % D,
Taking as an example a memory cell that can be operated, that is, cell 41, first, when writing only to cell 41, the word F' line is set to 10 V and the bit line B1 is grounded. By this operation, a write voltage of 10 (V) is applied to the gate of the cell 41, and fr+1, an n-type region where electrons form a bit line. The second
is injected into the insulator layer and accumulated. Note that in order to prohibit writing to cell 43 connected to the same word line as cell 41, bit MB2 of cell 43 is kept at an open potential, and electron injection from the ground line in cell 41. In order to prevent this, both the grounding lines C1 and C2 are set to an open potential. Next, when reading the cell 41, the word line D1
Set the bit line B1 to +3V and the bit line B1 to +5 (V), and detect whether the cell is ON or OFF. That is, if electrons are accumulated in the gate, no current will flow between the source and drain, and if no electrons are accumulated, current will flow. According to the present invention, the △vtb margin l is approximately 5 to 10 (V), which is a value of 25 [■
] Since it is much larger than the current level, there is a greater degree of freedom in setting the output voltage, and there is less possibility of malfunction. Furthermore, when erasing the cell 41, the operation is completely opposite to that of the insertion. That is, the voltage YlaD1 is grounded and the bit NBL is set to 10 [V]. As a result, the electrons accumulated in the gate pass through the n-type region that makes up the bit line (due to tunnel development) and are erased. At this time, if the cell 42, 44 and 45 were connected to the ♂tMBI (cell 117, 484
% are written, to prevent erasure of these cells, set the word gB2*B3 to +5. If the effective electron emission voltage is 5 [V], the tunnel will be It won't happen. Furthermore, ground @c1 on both sides of bit line B1
C2 is held at an open potential to prevent current from flowing through the cell.

The structure is realized through the process of making the upper wiring.1-Transistor type non-volatile semiconductor RAM
The Δvth margin is as large as about 5 to 10 (V), and the operation is stable and contributes effectively to high integration.

Note that the gist of the present invention is that the P structure of the gate portion is formed by a conductor W/a first insulator layer/a second insulator layer containing a large number of traps/
Regarding the third insulating layer/semiconductor layer, in the above embodiment, polycrystalline silicon (p 01 y S :l)/silicon dioxide (S10 □)/Tantalum oxide (Taxoy)
/silicon dioxide (SiO2)/silicon (Sl) was selected to form the gate structure according to I et al., but it is not limited to these materials.

(7) The effects of the invention can be explained in detail.According to the present invention, the write voltage is low, the △vth margin is large, the 111 operation is stable, and electrical recombination is possible. ), it is possible to provide a 1-transistor type nonvolatile semiconductor memory device that uses a non-destructive readout method.

[Brief explanation of the drawing]

FIG. 1 is a 1 mm cross section showing an example of the basic structure of an MO8 type transistor having a 70-ring gate constituting a non-volatile semiconductor storage device in the prior art, and FIG. The MNs that make up
3 to 6 are cross-sectional views showing an example of the basic structure of an O8 type transistor, after completion of the main steps in a method for manufacturing a 1-transistor type non-volatile organic storage device according to an embodiment of the present invention. Figure 8 is a cross-sectional view of the substrate, and Figure f87 is a diagram showing the structure of the non-volatile external conductor storage device according to the present invention.
FIG. 1 is a plan view of a substrate of a completed one-transistor type nonvolatile memory, and FIG. 9 is a circuit diagram showing its equivalent circuit. 1.11.21...S1 board, 2.12.22...
Source i.e. ground line diffusion layer, 3.13.23...
-Drain, that is, bit line diffusion layer, 4.14...
・5i02 insulator layer, 5... floating gate (
Metal), 6.16...Gate type rod, 17...813
N, layer, 28.28', 3(), 31...SiO□ layer, 29...Ta205 layer, 29'...Ta206 layer serving as second insulator layer, 32...gate wiring , that is, the wire P line (A/), 26... gate type rod (pol
ysi), 26... contact hole formed in the gate electrode, 31'... first insulator layer (S10°),
29'...Second insulator layer (TaXO7), 3(1
'=-@3's isolation layer (61102), 41-46
...Memory cell 0 C > D1319

Claims (1)

[Claims] (1) A semiconductor substrate, a first P-edge layer disposed on the semiconductor substrate, and an element having a ring on the first VA pole or VA group A of the periodic table of elements disposed on the first P-edge layer. Is an insulating layer of 2% of the acid content of the substance disposed on the second insulating layer? 1. A non-volatile semiconductor memory device comprising an insulating layer at t3 and a gate electrode disposed on the third insulating layer. f21 #! - Insulation on the conductive substrate from IVA dust or acid substances belonging to the VA group of the periodic table! ! Yuk.6.l'A. On the insulator layer (-step of forming a conductor layer, step of patterning the insulator layer and conductor layer into a desired shape, force ρ groove oxygen A step of forming an oxide layer at the interface between the conductive layer and the insulating layer and at the interface between the insulating layer and the channel layer by performing an oxidation treatment in the atmosphere. 1- A method for manufacturing a non-volatile semiconductor memory device, comprising the step of reducing the kasuri oxide layer of ['.