JP2817500B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory such as an ultraviolet erasable programmable ROM (hereinafter referred to as an EPROM) and an electrically erasable programmable ROM (hereinafter referred to as an EEPROM). It relates to a storage device.

[0002]

2. Description of the Related Art FIGS. 5A and 5B are cross-sectional views of a conventional nonvolatile semiconductor memory device of this type in the channel length direction and channel width direction, respectively. In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2c and 2d denote a drain region and a source region each formed of an n-type impurity diffusion layer, and 3 denotes a gate insulating film between a channel region and a floating gate electrode (hereinafter C-FG).
4 is a floating gate, 5 is a gate insulating film between a floating gate electrode and a control gate electrode (hereinafter referred to as FG).
−CG gate insulating film), 6 is a control gate electrode,
7, an interlayer insulating film; and 8, a field insulating film. Although not shown, a high-concentration impurity diffusion layer serving as a channel stopper is formed below the field insulating film 8.

In this memory transistor, a threshold value changes according to the electric charge stored in the floating gate electrode. The storage is performed using the electric charges, and the reading of the stored contents is performed by converting a change in the threshold value into a channel current.

Writing, ie, programming, is mainly performed by hot electron injection from a channel region, C-
This is performed by the FN tunneling phenomenon through the gate insulating film between the FGs and hot hole injection by avalanche breakdown.

FIG. 6 shows an EPROM or a batch erase type EEPROM.
OM [hereinafter referred to as FEPROM (= Flash EPRO
M)] is an equivalent circuit diagram of a general memory array used in [1]. Here, Q ^M _{i, j} (i = 1, 2, j = 1,
2) The memory transistors, X _1, word lines X ₂ is connected to the control gate electrode 6 of FIG. 5 in the row direction, Y _1,
Y ₂ is a bit line connecting the drain region 2c in the column direction, S is a source line that connects the source region 2d in common. Hereinafter, the operation of this conventional example will be described.

Read: Bias the selected word line to a high voltage of, for example, 5V and the other word lines to a low voltage of, for example, 0V. Also, the selected bit line is set to, for example, 1V.
The other bit lines are set to the open state. The selected bit line is connected to a sense amplifier. As a result, a current corresponding to the threshold value of the memory transistor at the intersection of the selected word line and the selected bit line flows through the selected bit line.
That is, if the threshold value of the memory transistor is 5 V or less, a channel current flows, and if the threshold value is 5 V or more, no current flows. The sense amplifier detects a potential change at a node caused by the presence or absence of the current and reads information.

Write: bias the selected word line to a high voltage of, for example, 13V and the other word lines to a low voltage of, for example, 0V. Further, the selected bit line is set to a voltage of, for example, 7 V, and the other bit lines are set to an open state. As a result, a channel current flows only in the memory transistor at the intersection of the selected word line and the selected bit line, hot electrons are generated, and electrons are injected into the floating gate electrode. A similar operation is performed by sequentially selecting memory transistors to be written.

[0008] Erase: In the case of an EPROM, the entire surface is irradiated with ultraviolet rays. In the case of a FEPROM, all word lines are set to a low voltage of, for example, 0 V, all bit lines are opened, and a high voltage of, for example, 12 V is applied to a source line. As a result, the electric field between the source and the floating gate electrode is increased, and electrons are emitted from the floating gate electrode to the source electrode to perform erasing.

[0009]

The above-mentioned conventional structure has the following structural features, and therefore has the following problems. Structural features Source / drain regions are formed in the surface region of the semiconductor substrate. Structural features The surface of the semiconductor substrate is a channel region. Structural features Element isolation is performed by a thick insulating film formed on the substrate surface and an impurity diffusion layer below the insulating film.

Problem: Although the substrate is fixed at a constant potential, a depletion layer is formed between the drain electrode and the substrate due to the characteristic, and a diffusion layer capacitance is generated. This capacitance depends on the total area of the drain region and the impurity concentration of the substrate. Substrate concentration: 7 ×
Under the conditions of 10 ¹⁶ cm ^-3 and V _D = 1 V, the capacitance becomes about 1 × 10 ^-3 pF per 1 μm ² . In an actual product, a large number of memory transistors are connected to a bit line, so that the bit line capacitance is several pF. However, the charge up of the drain voltage is delayed in proportion to the time constant of the product of the bias transistor resistance and this capacitance, and the discharge is delayed in proportion to the time constant of the product of the cell transistor resistance and this capacitance. Is a problem.

Problem: Since the drain region is formed on the substrate (characteristic), if there is a defect in the drain depletion layer, a junction leak occurs. If the leak current is so large as to be not negligible compared to the cell read current, reading of the write cell becomes impossible. In particular, in this structure, a crystal defect is likely to occur in a region adjacent to the insulating film having a large element isolation, and a decrease in yield due to this phenomenon becomes a problem.

Problems: Since the source region is formed on the substrate (characteristic), when erasing is performed by applying a high voltage to the source electrode, an avalanche breakdown current and a leakage current in addition to the FN tunnel current. An electric current is generated and flows out to the substrate. For this reason, when the source voltage is applied by, for example, a charge pump power supply that boosts the voltage from a low power supply voltage, a voltage drop occurs due to insufficient current supply capability, and the voltage required for erasure cannot be maintained.

Problems: Due to the characteristics, the threshold value _{VTM of the} memory transistor changes according to the substrate potential _VSUB according to the following equation. _{V TM = V TM0 + √ (} 4ε Si ε 0 qN A φ f) / C OX + √ {2ε Si ε 0 qN A (| V SUB | + 2φ f)} / C OX where, V _TM0 is, V _SUB V _{TM at} = 0 V, ε _Si is the dielectric constant of Si, ε ₀ is the dielectric constant of vacuum, q is the charge of electrons, N _A is the substrate impurity concentration, φ _f is the Fermi level, C
_OX is the gate oxide capacitance.

Therefore, when a substrate potential is applied, _VTM of the memory transistor increases. On the other hand, when the substrate potential is applied, the capacitance of the diffusion layer decreases, which is advantageous for high-speed operation of the peripheral transistor. For this reason, a substrate bias method is generally used in a dynamic random access memory (DRAM) or the like. However, EPROM, FEPR
In the OM, there is a problem that since the impurity concentration in the channel portion is high and the _VTM rise due to the substrate bias is large, there is a large trade-off for speeding up the peripheral circuit portion and the substrate bias method cannot be used.

PROBLEM: A thick insulating film has a low LO
It is generally formed by a selective oxidation method called a COS method. However, according to this method, erosion of the isolation insulating film into a channel region called “bars beak” occurs, and intrusion of impurities under the insulating film into the channel region also occurs. Therefore, the narrow channel effect becomes remarkable, and there arises a problem that the effective channel width becomes smaller than the initial patterning channel width.

[0016]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a control gate electrode on an insulating film; a first gate insulating film covering the control gate electrode; A floating gate electrode in contact with and having at least an overlap with the control gate electrode;
A gate insulating film, a channel region made of a first conductivity type semiconductor thin film in contact with the second gate insulating film and at least overlapping the floating gate electrode, and the floating gate electrode and the control gate sandwiching the channel region. And a plurality of thin film memory transistors each having a source / drain region made of a semiconductor thin film of the second conductivity type insulated from the electrode.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B show an n-channel type memory transistor according to a first embodiment of the present invention. FIG. 1A shows a channel length direction, and FIG. 1B shows a channel width direction. It is sectional drawing. Here, 1 is a p-type semiconductor substrate having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ , 9 is a SiO ₂ film having a thickness of 5000 °, 6 is 1 × 10 ²¹ P (phosphorus).
A control gate electrode made of polycrystalline silicon (hereinafter, referred to as polySi) having a thickness of 3000 ° doped at a concentration of cm ^-3 , and a SiO ₂ film formed by a 50 ° vapor phase growth method
0 ° Si ₃ N ₄ film and 50 ° SiO by vapor phase epitaxy
FG-CG gate insulating film having a three-layer structure of _two films, 4
Is P doped at a concentration of 5 × 10 ²⁰ cm ^-3 , and has a thickness of 15
A floating gate electrode made of polySi of Å, 3 is made of SiO ₂ film by vapor deposition with a thickness of 250 Å C-
This is an inter-FG gate insulating film.

Further, reference numeral 11 denotes that B (boron) has a concentration of 5 × 1.
The channel regions 10a and 10b made of an amorphous silicon (hereinafter referred to as a-Si) film having a thickness of 400 ° and doped to 0 ¹⁶ cm ^-3 are formed by adding an A-Si film having a thickness of 400 ° to A
The drain region and the source region are formed by doping s to a concentration of 1 × 10 ²¹ cm ⁻³ . The drain / source regions 10a and 10b are insulated from each gate electrode by the control gate / floating gate electrode side wall oxide film 12 and are formed on the Si substrate.
The substrate is insulated from the substrate by the O ₂ film 9. 7 is 700 thick
This is an interlayer insulating film made of 0 ° BPSG.

The feature of this embodiment is that the source / drain / channel region is formed in a semiconductor thin film on a relatively thick SiO ₂ film 9 on the substrate. Therefore, the substrate potential in the channel region is in a floating state. However, our experimental results show that if the thickness of the semiconductor thin film in the channel region is 700 ° or less, the potential of the thin film in the channel region can be controlled by the gate electric field. Therefore, the thin film memory transistor having the structure of the present embodiment performs the same operation as the conventional memory transistor shown in FIG. Therefore, the array layout can be configured in the same manner as in the conventional example, and the equivalent circuit diagram when the memory transistor of the present embodiment is laid out in that way is the same as FIG. Hereinafter, advantages of the thin film memory transistor according to the present embodiment will be described.

Advantages: The capacitance between the drain electrode and the substrate is
Since the capacitance is between the thick SiO ₂ film 9 and the semiconductor region, the capacitance can be reduced. Specifically, the SiO ₂ film 9
Is 5000Å, the capacity is about 1 × 1 per μm ²
0 ^-4 pF, which can be reduced to about 1/10 of the capacity of the conventional diffusion layer on the substrate. For this reason, the bit line capacity is remarkably reduced, and high-speed operation becomes possible.

Advantages: Since both the drain region and the source region are separated by the insulating film, no junction leakage occurs except for leakage to the channel region. Therefore, the device can be manufactured with a high yield.

Advantages: Since there is no substrate electrode, even if avalanche breakdown or channel leakage occurs during an erasing operation in which a high voltage is applied to the source side, there is no leakage current destination other than the bit line. Therefore, if the bit line is set to the open state, the outflow current can be limited to only the FN current. For this reason, erasing can be performed by an internal boosting power supply such as a charge pump.

Advantages: The electric field due to the substrate potential of the substrate 1 is shielded by the control gate electrode 6 and the floating gate electrode 4 and does not affect the channel region of the thin film transistor. Even if the substrate is biased to a negative potential, the threshold value of the thin-film memory transistor does not increase and the on-current does not decrease.

Advantages: Since the active element is a thin film semiconductor on an insulating film, it is not necessary to perform element isolation by a channel stopper having a high impurity concentration or a thick field oxide film, and the narrow channel effect which has been a problem in the conventional example occurs. Will not be. Therefore, the effective size of the element is determined only by the patterning width of the thin film semiconductor, and the limitation accompanying the reduction of the element width does not occur.

FIG. 2A shows n of the second embodiment of the present invention.
Plan view of the channel memory transistor, FIG.
(C) is a sectional view taken along line BB and line CC, respectively. Here, 1 is B-doped and the surface impurity concentration is 3
A semiconductor substrate made to 10 ¹⁶ cm ^-3 , 1a is a first channel region on the substrate surface, 2a and 2b are first drain regions formed by doping As with a concentration of 5 × 10 ²¹ cm ^-3. And a first source region, 8 is a 8000 ° thick SiO 2
_{2 is} a field insulating film for isolating an active region, and 3a is a first insulating film made of thermally oxidized SiO ₂ having a thickness of 250 °.
Of the gate insulating film between C and FG, 4a has a P concentration of 5 × 10
1500 cm thick polySi doped to ²⁰ cm ^-3
The first floating gate electrode 5a made of
First FG-CG of a three-layered structure of SiO ₂ film by the Si ₃ N ₄ film and the vapor deposition thickness 60Å by SiO ₂ film and the vapor deposition thickness 70Å by 0Å vapor deposition during gate insulating film, 6 is polySi the thickness of the thickness 1500Å doped with P on the impurity concentration 1 × 10 ²⁰ cm ^-3 1500
制 御 is a control gate electrode having a two-layer structure of WSi.

A substrate memory transistor composed of the control gate electrode 6, the first floating gate electrode 4a, the first channel region 1a, and the first drain / source regions 2a, 2b is a first memory transistor. It becomes a transistor.

5b is a SiO ₂ film of a thickness of 60 ° from a lower layer formed by a vapor phase growth method, and a Si film of a thickness of 70 ° formed by a vapor phase growth method.
_A second FG-CG gate insulating film having a three-layer structure of a ₃ N ₄ film and a SiO ₂ film having a thickness of 40 ° formed by a vapor phase growth method;
b is pol obtained by doping P to an impurity concentration of 5 × 10 ²⁰ cm ⁻³
A second floating gate electrode made of ySi, 3b is a second C-FG gate insulating film made of 350 ° SiO ₂ formed by a vapor phase growth method, and 11a is an impurity concentration of 1 × 10 ¹⁶ cm ^-3 .
Channel regions 10c and 10d made of a-Si and doped with a thickness of 500 ° are doped with an impurity concentration of 1 × 10 ²⁰ cm.
The second drain / source region 14 made of a-Si with a thickness of 500 ° doped with As- ³ is formed of TiSi formed on the surface thereof to reduce the resistance of the drain / source region.
₂ film, 12a are formed from the floating gate electrodes 4a, 4b and the control gate electrode 6 to the drain / source regions 10a, 10b.
Control gate / floating gate electrode side wall oxide film for insulating the substrate.

The TiSi ₂ film is formed on the second channel region 11a and the drain / source region 1 near the second channel region 11a.
After covering 0a and 10b with SiO ₂ , Ti is sputtered, sintered at 650 ° C. to silicide, and then NH ₄
It can be formed by immersing in OH and H ₂ O ₂ solution to remove unreacted Ti. The thin-film memory transistor including the control gate electrode 6, the second floating gate electrode 4b, the second channel region 11a, and the second drain / source regions 10c and 10d is the second memory transistor.

As shown in FIG. 2C, the second drain region 10c is connected to the first drain region 2a. On the other hand, the second source region 10d is insulated from the first source region 2b.

Reference numeral 7 denotes an interlayer insulating film whose lower layer is a 2,000-mm-thick SiO ₂ film formed by vapor deposition and the upper layer is a 7000-thick BPSG film. Reference numeral 15 denotes a connection with the first and second drain regions. Hole 16 for impurity concentration 1
Silicon plug P in × 10 ²¹ cm ^-3 is made of polySi doped, 13a is a metal wire.

FIGS. 3 (a) to 3 (d) all show the source
It is sectional drawing of a contact part. In the figure, 13b
Is a metal wiring connected to the first source region 2b;
Reference numeral 13c denotes a metal wiring connected to the second source region 10d.

Next, the electrical connection relationship of the device of the present embodiment will be described with reference to FIGS. 2A to 2C, 3A to 3D, and FIG. 4 which is an equivalent circuit diagram of the present embodiment. This will be described with reference to FIG. The control gate electrode 6 is connected in the row direction so that the word line X
1, X2, the first and second drain regions are connected in the column direction by metal wires 13a forming the bit lines Y1, Y2, and the first source region 2b is formed in the impurity diffusion layer in the row direction. After the connection, they are commonly connected by a metal wiring 13b serving as a first source line S1, and the second source region 10d is connected in the row direction by an a-Si film and a silicide film, and then connected to a second line. They are commonly connected by a metal wiring 13c which is a source line.

In FIG. 4, Q ^MD _{i, j} (i = 1, 2, j
= 1, 2) a first memory transistor of FIG. 2, Q ^MU
_{i, j} (i = 1, 2, j = 1, 2) indicates the second memory transistor.

Next, the operation of the apparatus of this embodiment will be described. Read: Bias the selected word line to a high voltage of, for example, 5V and the other word lines to a low voltage of, for example, 0V. Further, the selected bit line is set to a voltage of 1 V, and the other bit lines are set to the open state. The source line to which the memory transistor selected from the first and second source lines is connected is set to a low voltage of, for example, 0 V, and the other is opened. As a result, only the memory transistors whose source lines are biased to a low voltage among the pair of memory transistors connected to the selected word line can enter a state where a channel current can flow. Here, a channel current flows when the threshold value of the memory transistor is 5 V or less, and no current flows when the threshold value is 5 V or more. The change in the potential of the node due to the presence or absence of the current is compared with a reference voltage in the sense amplifier to obtain a sense amplifier output.

Write: Bias the selected word line to a high voltage of, for example, 13V and the other word lines to a low voltage of, for example, 0V. Further, the selected bit line is set to an intermediate voltage of, for example, 7 V, and the other bit lines are set to the open state. Further, the first of the first and second source lines to which the memory transistor to be written is connected is set to a low voltage of 0 V, and the other is set to the open state. No channel current flows on the memory transistor side where the source line is open, so that no hot electrons are generated and writing is not performed. Channel current flows on the memory transistor side on the side where the source line is set to 0 V, hot electrons are generated, and electrons are injected into the floating electrode.

Erasure: In the case of an EPROM, ultraviolet light is applied to the entire surface. In the case of a FEPROM, a word line is set to a low voltage of, for example, 0 V, all bit lines are set to an open state, and a high voltage of, for example, 12 V is applied to first and second source lines. As a result, the electric field between the source and the floating gate electrode is increased, and electrons are emitted from the floating gate electrode to the source electrode, thereby performing erasing. In another method, the same erase operation is performed even when all the bit lines are opened and a negative voltage of, for example, -7 V is applied to the word lines, and a positive voltage of, for example, 5 V is applied to the first and second source lines. Can be realized.

The advantage of the second embodiment is that the degree of integration is greatly improved by stacking the thin film memory transistors on the conventional substrate memory transistor while sharing the control gate electrode. By modifying the second embodiment, the memory transistor in the lower layer can also be a thin film transistor. This change enables higher integration.

[0038]

As described above, since the nonvolatile semiconductor memory device of the present invention includes a plurality of thin film memory transistors having a floating gate electrode, the following effects can be obtained.

Since the capacity of the impurity diffusion layer can be reduced, it is possible to provide a semiconductor memory device capable of reducing bit line capacity and operating at high speed.

Since the leakage of the junction leak current to the substrate electrode is eliminated, a stable read operation can be performed, and the yield can be improved.

Since the breakdown current and the channel leak current due to the application of the high voltage do not flow to the substrate electrode and the load on the power supply circuit at the time of erasing is reduced, the voltage drop of the internal power supply is suppressed, and the stable erasing operation is performed. Becomes possible.

Even if a bias is applied to the substrate, the variation in the threshold value of the memory transistor is small. Therefore, high-speed peripheral circuits can be achieved while avoiding occurrence of erroneous reading.

Since element isolation can be easily achieved without using a channel stopper or a field oxide film, the narrow channel effect is suppressed, and the effective size of the element can be made close to the design value.

Since the memory transistors can be stacked and formed, high integration can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a plan view and a sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a source contact portion according to a second embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a second embodiment of the present invention.

FIG. 5 is a sectional view of a conventional example.

FIG. 6 is an equivalent circuit diagram of a conventional example.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 1a first channel region 2a first drain region 2b first source region 2c drain region 2d source region 3 gate insulating film between channel region and floating gate electrode (C
-FG gate insulating film) 3a First channel region-floating gate electrode gate insulating film (first C-FG gate insulating film) 3b 2nd channel region-floating gate electrode gate insulating film (second 4 floating gate electrode 4a first floating gate electrode 4b second floating gate electrode 5 floating gate electrode-control gate electrode gate insulating film (FG-CG gate insulating film) 5a No. 1 floating gate electrode-control gate electrode gate insulating film (first FG-CG gate insulating film) 5b Second floating gate electrode-control gate electrode gate insulating film (second FG-CG gate insulating film) film) 6 control gate electrode 7 interlayer insulating film 8 field insulating film 9 SiO ₂ film 10a drain region 10b source region 10c second drain region 10d second source region 1 The channel region 11a second channel region 12,12a control gate a floating gate electrode side wall oxide films 13a~13c metal wiring 14 TiSi ₂ film 15 contact hole 16 silicon plug

Claims (5)

(57) [Claims] A control gate electrode formed on the insulating film of the semiconductor substrate; a first gate insulating film covering the control gate electrode; a floating gate electrode formed on the first gate insulating film; A second gate insulating film provided on the floating gate electrode, a channel region provided on the second gate insulating film, the first conductive type semiconductor thin film, and the channel region interposed therebetween. A nonvolatile semiconductor memory device comprising a plurality of thin film memory transistors each having a source / drain region formed of a second conductive type semiconductor thin film. 2. The thin film memory transistors are arranged in rows and columns, the drain regions of the thin film memory transistors are connected in the column direction by bit lines, and the control gate electrodes of the thin film memory transistors are connected in the row direction by word lines. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the source regions of said thin film memory transistors are connected in common. 3. A first channel region provided in a surface region of a semiconductor substrate of a first conductivity type, and a second conductive region provided in a surface region of the semiconductor substrate and sandwiching the first channel region. A first source / drain region of a mold, a first gate insulating film covering the first channel region, a first floating gate electrode provided on the first gate insulating film, A second gate insulating film covering the floating gate electrode, a control gate electrode provided on the second gate insulating film,
A third gate insulating film covering the control gate electrode;
A second floating gate electrode provided on the second gate insulating film, a fourth gate insulating film covering over the second floating gate electrode, and the second floating gate electrode via the fourth gate insulating film. A second channel region provided on the gate electrode and formed of a semiconductor thin film of the first conductivity type; and a second channel region formed of the semiconductor thin film of the second conductivity type and sandwiched between the second channel region
And a source / drain region, and a plurality of stacked memory transistors. 4. A first channel region formed of a semiconductor thin film of a first conductivity type formed on a semiconductor substrate via an insulating film, and a second channel of a second conductivity type formed across the first channel region. A source / drain region composed of a semiconductor thin film, a first gate insulating film covering the first channel region, a first floating gate electrode provided on the first gate insulating film, A second gate insulating film covering the floating gate electrode, a control gate electrode provided on the second gate insulating film, a third gate insulating film covering the control gate electrode,
A second floating gate electrode provided on the third gate insulating film, a fourth gate insulating film covering the second floating gate electrode, and the fourth gate insulating film with the fourth gate insulating film interposed therebetween. A second channel region provided on the second floating gate electrode and formed of a first conductive type semiconductor thin film, and a second channel region formed of the second conductive type semiconductor thin film and sandwiching the second channel region. A nonvolatile semiconductor memory device comprising a plurality of stacked memory transistors each having two source / drain regions. 5. The stacked memory transistor is arranged in a matrix, first and second drain regions of the stacked memory transistor are connected in a column direction by a bit line, and a control gate electrode of the stacked memory transistor is a word line. 5. The non-volatile semiconductor memory device according to claim 3, wherein the first source regions and the second source regions of the stacked memory transistor are connected in common in the column direction.