JPS62265768A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the occupation area of cells as well as to accomplish high integration by a method wherein the semiconductor layer, with which the control gate of a memory transistor is constituted, is formed on the gate region of a selective transistor, and a p-n junction region is formed on the semiconductor layer located on the gate region. CONSTITUTION:A memory transistor is composed of a semiconductor substrate 20, the n<+> type impurity diffusion regions 21 and 22, which will be turned to a source and a drain, a floating gate 1, and a control gate 10. A selective transistor is composed of the semiconductor substrate, the impurity diffusion region 22 to be turned to a source, the impurity diffusion region 23 to be turned to a drain, and the conductive layer 3 to be turned to a gate. A control transistor consists of the conductive layer 3 to be turned to a gate, the semiconductor layer 10 to be turned to a source, the semiconductor layer 10a to be turned to a drain, and the p-type region 11 to be used for formation of a channel between the source and the drain. As the selective transistor and the control transistor are laminated using a word wire 3 as a common gate electrode as above-mentioned, the occupation area of the memory cell can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in the structure of a memory cell of an electrically programmable/erasable nonvolatile semiconductor memory device (EEPROM).

[Prior Art] FIG. 3 is a diagram showing a planar arrangement of memory cells of a conventional electrically programmable/erasable nonvolatile semiconductor memory device. In FIG. 3, a memory cell of a conventional electrically programmable/erasable nonvolatile semiconductor memory device (hereinafter referred to as EEPROM) is provided via a memory transistor 8 for storing information and a word line 3. It is turned on and off in response to a word line selection signal, and is turned on and off in response to a selection transistor 6 for connecting the memory transistor 8 to the bit line 4 and a word line selection signal applied via the word line 3. , the signal applied via the control gate line 5 is transmitted to the control gate 2 of the memory transistor 8, and the information of the memory transistor 8: c! and a control transistor 7 for controlling storage and read operations.

The selection transistor 5 has its drain 6a connected to the bit line 4 via the contact hole 15, and its source 6b
is shared with the drain of memory transistor 8. Its gate is formed by the word line 3 and constitutes an MO5 type transistor.

The memory transistor 8 includes a floating gate 1 formed of a polysilicon layer formed on a semiconductor substrate with an insulating film interposed therebetween to store charge, and a floating gate 1 formed on the floating gate 1 with an insulating film interposed therebetween. A control gate 2 for controlling the charge accumulation operation of 1, a floating gate 1 and a thin oxide film region 9
It is composed of a drain 6b (shared with the source of the selection transistor 6) and a source region 8a, which charges and discharges charges by a tunnel current via the drain. The thin oxide film region 9 formed to charge and discharge charges between the floating gate 1 and the drain 6b is usually called a tunnel oxide film.

The control transistor 7 has a drain 7a connected to the control gate line 5 through the contact hole 16, and a source 7b connected to the contact hole 17 and the wiring layer 1.
9. It is connected to the control gate 2 of the memory transistor 8 through the contact hole 18, and the gate is formed by the word line 3.

That is, in the planar arrangement of FIG. 3, the upper right region in the drawing is allocated to the selection transistor 6, the lower region in the drawing is allocated to the memory transistor 8, and the upper left region in the drawing is allocated to the control transistor 7.

Word lines 3 for transmitting row selection signals are arranged horizontally in the drawing, control gate lines 5 for applying voltage to control gates 2 of memory transistors 8, and data buses (not shown) for transmitting information of the memory transistors 8. ) are arranged in the vertical direction of the drawing.

FIG. 4 is a diagram showing an equivalent circuit of the EEPROM memory cell shown in FIG. 3.

As seen from FIG. 4, both the control transistor 7 and the selection transistor 6 are turned on and off by receiving a signal applied through the word line 3 at their gates.
The electrical connection between the control gate line 5 and the control gate of the memory transistor 8 and the electrical connection between the drain 6b of the memory transistor 8 and the bit line 4 are controlled, respectively.

Next, the operation will be explained. To erase information in a memory cell (write information "1"), a high voltage Vp of, for example, about 21 V is applied to the control gate line 5, a high voltage Vp is also applied to the word line 3, and the bit line 4 is set to the ground potential. Ru. At this time, a high voltage Vp is applied to the control gate 2 of the memory transistor 8 via the control transistor 7, while the drain 6b of the memory transistor 8 is connected to the bit line 4 via the selection transistor 6 and becomes a ground potential. . As a result, a high voltage is applied between the drain 6b of the memory transistor 8 and the floating gate 1 via the tunnel oxide film 9, and the drain 6b
Electrons are injected into the floating gate 1 as a tunnel current.

As a result, the threshold value of the memory transistor 8 is shifted to a higher side, and information "1" is written into the write memory.

To program the memory cell (write information “O”), apply a high voltage Vp to the bit line 4, and apply the high voltage Vp to the control gate line 5.
This is done by setting the voltage to the ground potential and applying a high voltage Vp to the word line 3. In this case, the high voltage Vp is applied to the drain 6b of the memory transistor 8 via the selection transistor 6, while the control gate 2 is brought to the ground potential via the control transistor 7. As a result, a tunnel current discharges from the floating gate 1 to the drain 6b through the tunnel oxide film 9, and the threshold value of the memory transistor 8 shifts to a lower side, becoming a depletion type transistor, and information "0" is written. be included.

To read information from memory cells, set word line 3 to “H”
This is achieved by applying a signal at a level (normal power supply potential level), a signal at a ground potential level to control gate line 5, and connecting bit line 4 to a data bus (not shown).

If the memory transistor 8 has information "1" (erased state), the memory transistor 8 is of an enhancement type and is therefore in an off state, and no current flows on the bit line 4. On the other hand, when the memory transistor 8 has the information "0", the memory transistor 8 is a depletion type, and at this time the memory transistor 8 is in the on state, so the bit line 4 is connected to the memory transistor 8.
Current flows through. By detecting whether or not current flows on this bit line 4, it is determined whether the information held by the memory transistor 8 is "1" or "O".

[Problem to be Solved by the Invention 1] As described above, the conventional nonvolatile semiconductor memory device has a control transistor 7 for electrically connecting the control gate line 5 and the control gate 2 of the memory transistor 8, and a memory Drain 6b of transistor 8
Since the selection transistor 6 for electrically connecting the EEFROM to the bit line 4 is provided in a different area, the area occupied by the memory cell becomes large, which is a major obstacle to increasing the integration density of EEFROM. was there.

Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that solves the above-mentioned problems and can be highly integrated by reducing the area occupied by cells.

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention includes forming a semiconductor layer constituting a control gate of a memory transistor over a gate region of a selection transistor, and forming a semiconductor layer over a gate region of a selection transistor. pn in the semiconductor layer located in
A bonding area is formed.

[Function] The pn region formed in the semiconductor layer serving as the control gate forms a MOS transistor together with the gate of the selection transistor, and functions as a control transistor to transmit the signal potential of the control gate line to the control gate of the memory transistor. .

[Embodiment of the Invention] FIG. 1 is a diagram schematically showing a cross-sectional structure of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention.

In FIG. 1, an EEPROM memory cell according to the present invention includes a semiconductor substrate 2 of a first conductivity type (p-type in the figure).
0, impurity diffusion regions 21, 22, and 23 formed in predetermined regions of the semiconductor substrate 20, and a first semiconductor layer formed on the surface of the semiconductor substrate 2 and the impurity diffusion region 22 via an insulating film. a conductive layer 3 formed on the semiconductor substrate 20 between the first semiconductor layer 1 and the impurity diffusion regions 22 and 23 with an insulating film interposed therebetween; and a conductive layer 3 formed on the first semiconductor layer 1 and the conductive layer 3 with an insulating film interposed therebetween. For example, a second layer consisting of a polysilicon layer
and a second semiconductor layer 10 of conductivity type (p-type in the figure).

A first conductivity type region 11 is formed in a region of the second semiconductor layer 10 overlapping with the conductive layer 3 by using, for example, an ion implantation method. A region 9 with a thin insulating film is formed between the first semiconductor layer 1 and the impurity diffusion layer 22, and serves as a tunnel region. Furthermore, the n-type region 10 of the second semiconductor layer 10
a is connected to the wiring layer 5 through the contact hole 12.

The memory transistor includes a semiconductor substrate 20, an n+ type impurity diffusion region 21 serving as a source, an n+ type impurity diffusion region 22 serving as a drain, a first semiconductor layer 1 serving as a floating gate for accumulating charges, and a floating gate. A second semiconductor layer 10 serves as a control gate for controlling the charge storage operation of the gate 1.

Selection transistor is semiconductor based! 220, an impurity diffusion region 22 serving as a source, an impurity diffusion region 23 serving as a drain, and a conductive layer 3 serving as its gate.

The control transistor includes a conductive layer 3 serving as its gate, a second semiconductor layer 10 serving as its source, a second semiconductor layer 10a serving as its drain, and a p-type head for forming a channel between the source and drain. It consists of area 11.

The conductive layer 3 has the function of the word line 3, and the wiring layer 5 has the function of the control gate line.

In the above structure, the selection transistor and the control transistor are formed by stacking the word line 3 as a common gate electrode, thereby reducing the area occupied by the memory cell.

The equivalent circuit of the memory cell shown in FIG. 1 is exactly the same as the equivalent circuit of the conventional memory cell shown in FIG.

FIG. 2 is a diagram showing an example of a planar arrangement of memory cells of the nonvolatile semiconductor memory device shown in FIG. 1. In FIG. 2, a memory transistor having a floating gate 1 and a control gate 10 is formed in the lower half region of the drawing, and a control transistor and a selection transistor having a word line 3 as a common gate electrode are formed in the upper region of the drawing. It is formed. The drain of the control transistor is connected to the control gate line 5 through the contact hole 12, and the drain of the selection transistor is connected to the bit line 4 through the contact hole 30.

As is clear from comparing FIGS. 2 and 3, in the nonvolatile semiconductor memory device according to the present invention, the control transistor and the selection transistor are stacked, so the area occupied by the memory cell is large. The width has been reduced.

In the above embodiment, a p-type semiconductor substrate was used as the semiconductor substrate, but the conductivity type is not limited to this, and even if a p-type semiconductor substrate is used, the same effect as in the above embodiment can be obtained. is obtained.

Furthermore, although a case has been described in which the control gate 10 is formed of a polysilicon layer, the same effects as in the above embodiment can be obtained even if the control gate 10 is formed using a single crystal semiconductor layer.

[Effects of the Invention] As described above, according to the present invention, a pn junction region is provided in a region overlapping with a word line of a semiconductor layer forming a control gate of a memory transistor, and a MOS transistor with the word line as its gate electrode is manufactured. Since the selection transistor for connecting the memory transistor to the bit line and the control transistor for electrically connecting the control gate of the memory transistor to the control gate line are stacked, the memory cell occupancy is reduced. The area can be reduced, and the nonvolatile semiconductor memory device can be highly integrated efficiently.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic cross-sectional structure of a memory cell of a nonvolatile semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a planar arrangement of a nonvolatile semiconductor device according to an embodiment of the present invention. FIG. 3 is a diagram showing an example of a planar arrangement of a conventional nonvolatile semiconductor memory device. FIG. 4 is a diagram showing an equivalent circuit of a memory cell of a nonvolatile semiconductor memory device. In the figure, 1 is a floating gate (first semiconductor layer), 2 is a control gate (second semiconductor layer), and 3 is a floating gate (first semiconductor layer).
is a word line, 4 is a bit line, 5 is a control gate line, 6 is a selection transistor, 7 is a control transistor, 8 is a memory transistor, 9 is a tunnel region, 11
is the channel region of the control transistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix of rows and columns, each of which stores electrically writable and erasable information in a nonvolatile manner, the memory Each of the cells includes: a semiconductor substrate of a first conductivity type; a first insulating film formed in a predetermined region on the semiconductor substrate via a first insulating film, and for accumulating charges corresponding to the information; a semiconductor layer; and a second semiconductor layer formed over the first semiconductor layer via a second insulating film for controlling charge storage operation of the first semiconductor layer, Second
A nonvolatile semiconductor characterized in that a second conductivity type region, the first conductivity type region, and the second conductivity type region are formed adjacent to each other in this order in a predetermined region of the semiconductor layer. Storage device. (2) the memory cell includes the first semiconductor layer and the second semiconductor layer;
A memory transistor that stores information, and a control electrode that receives a row selection signal from the outside to turn on and off.
a selection transistor for connecting the memory transistor to a corresponding column, and a control electrode of the selection transistor is formed in a predetermined region on the semiconductor substrate via a third insulating film. 3 semiconductor layers, and the first conductivity type region formed in the second semiconductor layer is formed on the third semiconductor layer so as to overlap with a fourth insulating film interposed therebetween. The nonvolatile semiconductor memory device according to item 1. (3) Regions of different conductivity types formed in a predetermined region of the second semiconductor layer form a MOS transistor together with the third semiconductor layer, and the regions that are formed in a predetermined region of the second semiconductor layer form a MOS type transistor. Claim 1 or 2 transmitting a signal for controlling the electric storage operation of the semiconductor layer.
The non-volatile semiconductor memory device described in 2. (4) the second semiconductor layer is a polycrystalline silicon layer;
A nonvolatile semiconductor memory device according to any one of claims 1 to 3.