KR0130548B1 - Non-vocatle semiconductor memory device with voltage stabilizing electrode - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory with Potential Locking Electrode

1 is a plan view showing main parts of a NAND type EEPROM according to an embodiment of the present invention.

2 is a cross-sectional view of the EEPROM along line II-II of FIG.

3 is a cross-sectional view of the EEPROM along line III-III of FIG.

4 is a cross-sectional view of the EEPROM along line IV-IV of FIG.

5 is a cross-sectional view of the EEPROM along the line VV of FIG.

6 is a sectional view of the EEPROM along the VI-VI line of FIG.

7 is a cross-sectional view of an EEPROM according to another embodiment of the present invention.

8 is another cross-sectional view of the illustrated EEPROM of FIG.

9 is a cross-sectional view of an EPROM according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: EEPROM 12: Semiconductor Substrate (Silicon Substrate)

14, 14i: NAND cell unit 16: conductive layer (bit line)

18: floating gate layer 20: control gate layer (word line)

30: isolation layer for device isolation 32: isolation layer (channel stopper layer)

34: first gate insulating layer 36: insulating layer (CVD insulating layer)

39: second gate insulating layer

40, 44: first polysilicon layer (floating gate layer)

42, 46: second polysilicon layer (control gate layer)

64 contact hole 70 conductive layer (contact layer)

72 conductive layer 74 contact hole

76: p + type diffusion layer 78: p type separation layer

90: n-type silicon substrate 92: p-type semiconductor layer (well region).

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a NAND type memory cell unit that is programmable and electrically erasable.

[Traditional Technology and Problems]

As the demand for high performance and high reliability for digital computer systems increases, highly integrated semiconductor memory cells are becoming indispensable. In other words, there is a strong demand for solid-state memory with enhanced data storage capability. Such solid-state memory can be used to provide an external data storage device (for example, a magnetic floppy disk drive unit or a fixed disk unit) for an existing digital computer system. It can be replaced.

Currently available EEPROM (Electrcally Erasable Programmable Read Only Memory) has technical advantages such as higher reliability and faster data programming than magnetic data storage. However, the total memory capacity of the EEPROM is not yet large enough to replace the magnetic data storage device. That is, in the conventional EEPROM, since each memory cell is typically composed of two transistors, there is a problem that the degree of integration cannot be increased as necessary to have a memory capacity that can replace the magnetic data storage device. .

Recently, a NAND type EEPROM has been developed as a nonvolatile semiconductor memory with increased storage capacity. According to this type of memory, memocells are divided into a predetermined number of memory cell block sections. Here, since each memory cell is typically composed of a NAND cell unit composed of a single transistor of floating gate type, only one contact portion is required between each array of memory cells and the corresponding bit line. Therefore, the area occupied by all the memory cells on the substrate is reduced compared to the conventional EEPROM, so that the degree of integration of the EEPROM is improved and the total capacity of the memory is increased.

According to the NAND type EEPROM, the carrier is moved by the tunneling phenomenon between the floating gate of the transistor and the substrate on which the insulating thin film is interposed so that data is written or read out to a predetermined memory cell. In this respect, a NAND memory cell is also called a FET-MOS memory cell. More specifically, when the memory cell is an N-channel transistor, by applying a high voltage of 20V to the control gate of the cell transistor and setting the drain layer to 0V, electrons are transferred from the drain region to the floating gate by the tunneling effect. Is injected. As a result, the threshold value of the cell transistor is level shifted in the positive direction. In order to emit electrons stored in the floating gate to the substrate, a high voltage of, for example, 20V is applied to the drain region of the cell transistor, and the control gate electrode is set to 0V. The threshold of the cell transistor is then level shifted in the negative direction. By applying these two different voltages, the data writing operation and the data erasing operation are performed in the cell transistor. In order to read the data stored in the cell transistor, a read voltage having a predetermined potential level is applied to the control gate of the cell transistor. Accordingly, the logic value of the stored data, namely logic 0 or 1, is determined by whether or not the channel current flows in the cell transistor under such voltage application. However, the highly integrated NAND type EEPROM suffers from a number of problems due to undesirable breakdown as described below. That is, when a high voltage is applied to the drain region of the memory cell transistor in the data write and erase mode, breakdown occurs in the PN junction (e.g., the junction between the drain region and the channel-stopper layer formed adjacent to the drain region in the substrate). do. The breakdown also occurs on the surface portion of the drain region, and such a breakdown is known as a surface breakdown.

Since the breakdown phenomenon greatly degrades the performance of the data write / erase operation, it is a very serious problem for the EEPROM. Even if the breakdown is not perfect, that is, even when a partial breakdown occurs, the current flowing through the substrate is abnormally increased, making it difficult or impossible to successfully remove the electrons stored in the floating gate. When the stored electrons become difficult to remove in this way, the operation reliability of the EEPROM is degraded, and in the worst case, malfunction occurs. The same is true of an EEPROM or an ultraviolet erasing type EEPROM called a FLOTOX type memory cell.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a non-volatile semiconductor memory device having high integration and greatly improved operation reliability.

[Configuration of Invention]

To achieve the above object, the present invention provides a nonvolatile semiconductor memory device including a semiconductor substrate, a memory cell portion including a parallel data transfer line formed on the semiconductor substrate and a memory cell connected to a bit line of the data transfer line. . The memory cell includes a predetermined number of data storage transistors having a control gate layer and a NAND cell unit having a series circuit of switching transistors. In order to receive the preselected constant voltage applied to the substrate in at least the selected period during which the NAND cell unit enters the data writing or erasing operation, the potential fixing is provided adjacent to a certain data transmission line with a conductive layer. Means are insulated in the substrate. The predetermined voltage may be a substrate voltage, or may be a well potential when the NAND cell unit is formed in a semiconductor well region in the substrate.

EXAMPLE

Hereinafter, each embodiment of the present invention will be described in detail with reference to the accompanying drawings. First, referring to FIG. 1, an electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention is denoted by reference numeral 10. The EEPROM 10 includes a semiconductor substrate 12 of a specific conductivity type, and the semiconductor substrate 12 may use a p-type (p-type) silicon substrate doped with a small amount of impurities. Here, for the sake of better understanding, the illustration of all the insulating layers is omitted in FIG. 1, but these insulating layers are shown in the cross-sectional views of FIGS. 2 and 3, 4, 5, and 6. It should be noted.

A plurality of NAND cell units 14 are formed on the silicon substrate 12. In FIG. 1, for simplicity, only one NAND cell unit is referred to by reference numeral 14i (where i is an appropriately selected integer). Each of these NAND cell units 14 is actually configured in the same manner, and the following description of the NAND cell unit 14i also applies to the remaining NAND cells of the EEPROM 10. do. As shown in FIG. 1, the NAND cell unit 14i is provided with error numbers of a predetermined number of data storage transistors M connected in series with each other, and each NAND cell unit is abbreviated as a memory cell transistor or a transistor. Two select transistors QS1 and QS2 are provided at both ends of the serial array of the data storage transistor M. In this embodiment, eight cell transistors (M1, M2, ..., M8) RK are provided in the NAND cell unit 14i. The number of the cell transistors can be changed to 16 or 32 as necessary.

The NAND cell unit 14 is coupled to a corresponding bit line BLi as the conductive layer 16 formed of, for example, aluminum, and is provided at one end of a series array of cell transistors M in the NAND cell unit 14i. 1 selector QS1 is provided. The first selection transistor QS1 is selectively conductive, for example, when the first selection transistor QS1 is turned on, the first NAND cell unit 14i is in the conductive state at the drain of the cell transistor M1. The select transistor QS1 is connected to the corresponding bit line BLi. In addition, a second selection transistor QS2 is provided at the other end of the series array of cell transistors M in the NAND cell unit 14i, and the second selection transistor QS2 is also selectively conducted. When the two-select transistor QS2 is turned on, the NAND cell unit 14i is connected to the common source region of the EEPROM 10 at the source of the cell transistor M8. The memory cell transistors M1 to M8 in the NAND cell unit 14i are floating gate layers 18-i (I = 1, 2, ..., 8) and control gate layers 20-i; i = 1 as described later. Are metal oxide semiconductor field effect transistors (MOSFETs) having (2, ..., 8), whereas the first and second selection transistors (QS1, QS2) are switching MOSFETs each having only a control gate layer, and the cell transistor (M). Control gate layer 20 serves as a word line of the EEPROM 10. Hereinafter, the structure of the NAND cell unit 14i will be described in detail with reference to FIGS. 2 to 6. An 800 nm-thick insulating layer 30 is formed in the field region of the p-type silicon substrate 12, and the isolation layer 32 is an element formation surface region on which the memory cell is formed. The p-type device isolation layer 32 is formed under the device isolation insulating layer 30 as a channel stopper layer. As shown in FIG. 2 or FIG. 3, a first gate insulating layer 34 of a thin film is formed in the element-shaped sanctuary on the silicon substrate 12, and the first gate insulating layer 34 is a tunneling current. Has a specific thickness so that it can flow through the first gate insulating layer 34. In addition, a first polysilicon layer acting as a floating gate layer 18-i for carrier storage of each NAND cell transistor Mi (I = 1, 2, ..., in this embodiment) is formed in each NAND cell transistor region. It is formed insulated on the one gate insulating layer 34. As shown in FIG. 2, the floating gate layer 18 is formed by patterning such that both ends thereof extend to terminate the device isolation insulating layer 30 located at both ends of the NAND cell unit on the silicon substrate 12. As shown in FIG. The second polysilicon layer serving as the control gate 20 is formed on the first polycrystalline silicon layer, that is, the floating gate layer 18, in each of the NAND cell transistor regions, and the control gate layer 20-i is Insulated by the second gate insulating layer 39 interposed between the floating gate layer 18 and the control gate layer 20, the control gate layer (20-1, 20-2, ... 20-8) is NAND It can be used as a word line for the memory cell transistors M1, M2, ..., M8 in the cell unit 14.

Each control gate layer 20-i is then covered with an insulating layer 36, as is apparent in FIGS. 2, 3, or 4, which are subjected to the CVD process. Since it can form, it is called a CVD insulating layer. In addition, a conductive layer 16 serving as a bit line is formed on the CVD insulating layer 36 to have a linear planar shape as shown in FIG. 1, in which case the conductive layer 16 is formed of aluminum. Can be. The bit lines BL are arranged side by side at predetermined intervals along the extension direction of the control gate layer 20 of the cell transistor M in the word line, that is, the NAND cell unit 14. The two selection transistors QS1 and QS2 are provided across the series circuits of the NAND cell transistors M1 to M8, of which the first selection transistor QS1 is the NAND cell unit 14i as shown in FIG. Is connected between the first cell transistor M1 of < RTI ID = 0.0 >) < / RTI > and the bit line BLi coupled to this NAND cell unit 14i, and the second selection transistor QS2 is an eighth cell transistor of the NAND cell unit 14i. It is connected between M8) and the silicon substrate 12 having the engine voltage Vss set to the ground voltage potential in some cases while being referred to as a source voltage or a common source voltage. As clearly shown in FIG. 5, each of the first and second selection transistors QS1 and QS2 has a gate electrode formed of a polysilicon layer having a two-layer structure, as shown in FIG. The two-layer structured gate electrode of the first selection transistor QS1 is connected to the selection gate control line SG1, while the two-layer structure gate electrode of the second selection transistor QS2 is connected to the selection gate control line SG2. Connected. In more detail, the first selection transistor QS1 may include a first polycrystalline silicon layer 40 and a second polysilicon layer 42 that is insulated on the first polycrystalline silicon layer 40. Wherein the first polysilicon layer 40 is formed by patterning the same layer provided to form the floating gate layer 18 of the NAND cell transistor M, while the second polysilicon layer 42 is formed by patterning the same layer provided to form the control gate layer 20 of the NAND cell transistor. In addition, the above-described configuration is also applied to the other second selection transistor QS2, and the second selection transistor QS2 is formed on the first polycrystalline silicon layer 44 and the first polycrystalline silicon layer 44. A second polysilicon layer 46 disposed insulated on the substrate, wherein the first polysilicon layer 44, which is a substructure, is formed by patterning the same layer provided to form the floating gate layer 18; The second polysilicon layer 46 is formed by patterning the same layer provided to form the control gate layer 20 of the NAND cell transistor M. Meanwhile, the silicon substrate 12 has n-type (n +) semiconductor layers 48, 50, 52, 54, 56, 58, 60, and 62 doped with a large amount of impurities, of which n + layer 48 , 50, 52, 54, 56 and 58 are two adjacent floating gate layers 40 and 18-1 and a floating gate layer [(18-i, 18- (i + 1)] or floating gate layer respectively. Located on a specific substrate surface portion defined between (18-8, 44), and the n + type layers are fabricated with gate layers 18, 20, 40, 42, 44, 46 during the manufacturing process of EEPROM 10. After and before the bit line layer 16 is formed by impurity doping, the n + type layer 48 acts as a source and drain region of the corresponding NAND cell transistor Mi. ) Are connected in series so that any one of the n + type layers 48, 50, 53, 54, 56, 58, and 60 is used as a source region of a specific cell transistor Mi and adjacent cell transistors [M]. (i + 1)] For example, the n + layer 50 is used as a source of the NAND cell transistor (.M1) as shown in Fig. 5, and the NAND cell transistor (M2) adjacent to the cell transistor (M1) can be used. The n + layer 42 is larger than the remaining n + layer so that the n + layer 42 can also be used as a contact portion with the bit line 16, in which case the bit line 16 is a NAND cell. A contact hole 64 is formed in the CVD saving layer 36 so as to be in contact with the n + layer 62 serving as the drain of the transistor M.

As the first selection transistor QS1 is turned on, the NAND cell unit 14i is connected to the corresponding bit line BL1 coupled thereto. More specifically, the first selection transistor QS1 is connected to the NAND cell unit 14i. When turned on, the drain of the NAND cell transistor QS1 is electrically connected to the corresponding bit line BLi, while the NAND cell unit 14i is connected to the NAND cell unit 14 when the second selection transistor QS2 is conducted. The source of the eighth cell transistor M8 in 14i) is connected to the common source voltage.

Here, a very important point is that the two-layer gate structure of the first selection transistor QS1, that is, the first and second polysilicon layers 40 and 42 are in direct contact with each other at a plurality of contact portions. In FIG. 1 or FIG. 6 only one contact layer is visually shown as indicated by reference numeral 70. A conductive layer, which refers to the third polysilicon layer formed by the patterning process so as to have the planar shape shown in FIG. 1, can be used as the contact layer for connecting the gate layers 40 and 42 to each other. In this case, these contact layers 70 are provided at predetermined intervals along the direction parallel to the word line WL, and the intervals of these contact layers 70 do not necessarily have to be fixed to a fixed interval value, but a pair of The distance between the selected NAND cell unit, for example, the NAND cell unit 14i and the NAND cell unit 14 (i + 8) or 14 (i + 6) can be set. In this case, the lower floating gate layer 40 is continuously formed, while the upper control gate layer 42 is connected to each other by a plurality of layer portions, that is, the contact layer 70, and the lower floating gate layer 40 ( Connected to 40) and divided into two adjacent layers. A contact structure similar to the above can also be used for the two-layer structure gate electrode of the second select transistor QS2 composed of other gate layers 44 and 46.

In addition to the NAND cell structure, another conductive linear enhancement layer 72 is provided between two adjacent bit lines BLi and bit lines BL (i + 1) not shown in FIG. The additional linear layer 72 is formed on the CVD insulating layer 36 so as to extend in parallel with the bit line BL, while the linear layer 72 is provided in the defined device isolation region. In addition, the linear layer 72 can be formed between all two adjacent bit lines BLi and BL (i + 1).

On the other hand, as shown in FIG. 6, the linear layer 72 is a p-type separation layer formed in the silicon substrate 12 as a so-called channel stopper layer via a contact hole 74 formed in the CVD insulating layer 36 ( The silicon substrate 12 is connected to the silicon substrate 12 in a form of being connected to the p + type diffusion layer 76 formed at 78, and the channel stopper layer 78 extends in parallel with the bit line BL. The linear layer 72 is formed under the isolation insulating layer 30, and the linear layer 72 is formed on the p + type diffusion layer 76 to minimize contact resistance between the silicon substrate 12 and the linear layer 72. It connects with the p-type silicon substrate 12 by this. According to this structure, the linear conductive layer 72 is fixedly set to the substrate potential Vss. In this sense, the conductive layer 72 is described as the substrate potential fixed electrode.

On the other hand, the data writing in the memory cell transistors M1 to M8 in the selected NAND cell unit 14i is performed in a sequential manner as will be described later. When the EEPROM 10 is set to the data writing mode, the selected data is selected. The eighth cell transistor M8 of the NAND cell unit 14i is first subjected to data recording, and the seventh cell transistor (.M7) is then subjected to data recording, and then M6,... , Data recording is performed in the order of M3, M2, M1. Here, to summarize the features of such sequential data writing, when the NAND cell unit 14i is designated as the selected NAND cell unit, the memory cell transistor M included in the selected NAND cell unit is the NAND cell unit 14i. ) Is the first cell transistor M8 located farthest from the first selection transistor QS1 for connecting the corresponding bit line BLi to the corresponding bit line BLi, and the cell transistors M7, ..., M3, M2 adjacent thereto are first selected. Are sequentially selected, and the data write operation is performed in a specific order in which the first cell transistor M1 positioned adjacent to the first select transistor QS1 is finally selected.

According to the sequential data write mode described above, in order to first write data into the memory cell transistor M1, for example, a high level voltage of 20 V is supplied to the bit line BLi coupled with the selected NAND cell unit 14i, At this time, the word lines WL1 to WL7 connected to the gate electrodes of the remaining NAND cell transistors M1 to M7 have a positive value that is lower than the high level voltage and high enough to conduct the cell transistors M1 to M7. The voltage is supplied, which is set at about 10V. Under this condition, the data voltage appearing on the bit line BLi coupled with the selected NAND cell unit 14i is equal to the selection gate control signal transmitted by the selection gate control line SG1. In response to the conduction state, it is transmitted to the selected transistor M8 through the remaining transistors M1 to M7. At this time, as the second selection transistor QS2 is also turned on, the second selection transistor QS2 is transferred to the transistor M8. At this time, as the second select transistor QS2 is also turned on, the drain of the transistor M8 is connected to the substrate voltage Vss, and the word line WL8 is set to, for example, the substrate total Vss, that is, 0V. Carrier, in this case, electrons are injected into the floating gate 18-1 by tunneling from the drain 58 of the transistor M8, and the electron accumulation in the floating gate 18-8 is a cell transistor ( This means that data is recorded in M8). The remaining cell transistors M7, ..., M2, M1 are subjected to the data write operation in a similar manner to the above.

On the other hand, the erasing of data is performed by emitting electrons accumulated in the floating gate of the NAND cell transistor in a selective manner or in a batch manner. In this data erasing mode, for example, the selected NAND cell including the selected cell transistor M2. While the 0V voltage is supplied to the bit line BLi coupled to the unit 14i, the high level voltage of about 20V is applied to the word line WL2 connected to the control gate voltage 18-2 of the selected cell transistor M2. This is supplied in unison. As the voltage is supplied, electrons accumulated in the floating gate 18-2 are emitted to the silicon substrate, which is a selective data erasing mode. On the other hand, if a high level voltage is applied to all the word lines WL1 to WL8, the above-mentioned full discharge is simultaneously performed in all the cell transistors M1 to M8 included in the selected NAND cell unit 14i. This batch data erasing mode. In addition, if the selective data erasing operation is performed sequentially with respect to the NAND cell transistor M, this method is called a sequential data erasing mode.

In the data recording / erasing mode, the substrate potential fixing electrode 72 is constantly fixed to a specific voltage having a preset voltage at a ground potential (0 V) or a low potential of negative polarity. According to this voltage setting, only the substrate Even though the voltage Vss changes due to the flow of tunneling current, for example, due to the transfer of electrons by the turret between the floating gate 18 and the silicon substrate 12 of the selected NAND cell transistor 14, the substrate potential fixed electrode ( 72 can be set to be effective and stable at a predetermined constant voltage. Even if there is a variation in the substrate voltage Vss, in principle, it is effectively absorbed by the substrate potential fixing electrode 72 and assisted by the channel stopper region 78 connected to the substrate potential fixing electrode 72. Is absorbed. As a result, an unnecessary increase in the substrate voltage Vss can be suppressed or excluded, thereby maximizing the expansion of the operation margin of the EEPROM 10. Here, various methods may be employed for the application of the constant voltage to the substrate potential fixing electrode 72. Meanwhile, the substrate potential fixing electrode 72 may be fixed to the substrate potential fixing electrode 72, for example, through the data access mode of the EEPROM 10. A voltage, that is, a substrate voltage Vss is continuously supplied, and on the other hand, a specific voltage Vss is selectively supplied to the substrate potential fixed electrode 72 at a constant interval or at a variable interval specified in the data recording / erasing mode. Note that it can be supplied. According to the embodiment of the “substrate potential fixed” feature, since the substrate voltage Vss remains stable at a constant voltage, the potential variation of the silicon substrate 12 which is increased in the highly integrated EEPROM is effectively eliminated in the data erasing and recording mode. This eliminates voltage breakdown, including “surface breakdown”. Therefore, the operation margin of the ERROM can be maximized, so that a good data recording / erasing operation with high reliability can be provided. In the above embodiment, the substrate potential fixing electrode 72 has two adjacent NAND cell units 14i and 14 (i + 1) on the silicon substrate 12 as a separate layer for stabilizing the substrate voltage Vss. In addition, the contact hole 74 is located in the field region defined between the upper control gate layer 42 and the lower floating gate layer 40 of the two-layer select gate electrode serving as the select gate control line SG1. It is important to be formed adjacent to the contact layer 70 for interconnecting them. In other words, the configuration of a separate layer for stabilizing the substrate voltage is formed in a "dead space" which is not originally used to form any layer, which is the addition of the substrate potential fixed electrode 72. This means that a separate surface space is essentially not necessary on the silicon substrate 12 of limited size. Meanwhile, the embodiment can be changed as shown in FIGS. 7 and 8, and is used for the p-type semiconductor layer 92 in which the n-type silicon substrate 90 is formed of a region commonly referred to as a "well region". do. As shown in FIG. 7, the NAND cell unit 14 having the same configuration as the above-described embodiment actually includes the memory cell transistors M1 to M8, the first select transistor QS1 and the first transistors formed in the well region 92. FIG. It is formed to have a series circuit of two-selection transistor QS2. In addition, as shown in FIG. 8, the substrate potential fixing electrode 72 has a tunnel current due to the data writing or erasing operation of the NAND cell unit 14 via the p + layer 76 and the channel stopper layer 78. FIG. The well potential (Vw; w means " well ") is connected to the well region 92 in which the well potential changes. The variation or instability of the well potential is completely reduced by designing and using the substrate potential fixing electrode 72. Can compensate. In this case, the substrate potential fixed electrode layer has a function of fixing the potential Vw of the well region 92 so as to be set to a predetermined voltage which may be equal to the well potential Vw or a negative low voltage. In an embodiment, the substrate potential fixed electrode layer may be referred to as a “well potential fixed electrode”. In addition, the two-layer select gate layer structure of one or both of the first and second select transistors QS1 and QS2 may be changed as shown in FIG. The polysilicon gate layers 42 and 40 are in direct contact with each other without the use of any contact layer, such as the contact layer 70 clearly shown in FIG. According to this configuration, the upper surface configuration of the EEPROM can be made under flattening so that the bit line layer 16 and the substrate potential fixing electrode 72 can be positioned at substantially the same height as shown in FIG. In addition, although this invention was illustrated and demonstrated especially about some preferable embodiment, various changes and a deformation | transformation are possible within the range which does not deviate from the technical summary and range of this invention. For example, the contact hole 64 for each bit line BLi may be slightly moved along the extension direction of the word line to secure the increased space with respect to the substrate potential fixing electrode 72. Obviously, the present invention can be applied not only to the NAND cell type EEPROM described above, but also to other types of nonvolatile semiconductor memory devices such as a NOR type EEPROM, an EEPROM having a FLOTOX type memory cell structure, and an ultraviolet erasing type PROM. . On the other hand, the reference numerals corresponding to the drawings in parallel with each component of the claims of the present application are for the purpose of facilitating the understanding of the present invention, and the intention to limit the technical scope of the present invention to the embodiments shown in the drawings. It is not one.

Claims (18)

Programmable memory cells coupled to the semiconductor support layers 12 and 92, parallel data transfer lines BL formed on the semiconductor support layers 12 and 92, and arbitrary bit lines 16 and BLi of the data transfer lines BL. A nonvolatile semiconductor memory device having a memory cell portion including an array of (M1, M2, ..., M8), said semiconductor support layer (10) in at least a selected period during which said NAMD cell unit enters a data write / erase operation. In order to accept a predetermined constant voltage applied to the 12,92, a potential fixing means 72 positioned adjacent to the arbitrary data transfer line 16, BLi is provided on the semiconductor support layers 12,92. Nonvolatile semiconductor memory device, characterized in that installed insulated. 2. The memory cell of claim 1, wherein the memory cell comprises a NAND cell unit 14i having a series circuit of a predetermined number of data storage transistors M1 to M8 and a switching transistor QS1 having a control gate. Nonvolatile semiconductor memory device. The semiconductor support layer (12,92) according to claim 1, wherein the potential holding means (72) is electrically connected to the semiconductor support layers (12,92) and positioned adjacent to the arbitrary data transfer lines (16, BLi). Nonvolatile semiconductor memory device, characterized in that consisting of a conductive layer provided on the insulating layer. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said conductive layer is fixedly connected to said semiconductor support layer (12,92) and is set to said predetermined constant voltage in a data recording mode or a data erasing mode. 4. The nonvolatile semiconductor as claimed in claim 3, wherein the semiconductor support layer having a stacked region in which the conductive layer 72 is formed comprises a semiconductor substrate 12 having a surface portion on which a NAND cell unit is formed. Memory. 4. The semiconductor support layer according to claim 3, wherein the semiconductor support layer having a stacked region in which the conductive layer 72 is formed includes a first conductive semiconductor substrate 12 and a surface portion on which the NAND cell unit is formed. And a semiconductor well region (92) formed on said semiconductor substrate (12). The semiconductor device of claim 5, wherein the semiconductor substrate 12 has the same conductivity type as the substrate 12 and is formed in the semiconductor substrate 12 in the stacked region, and functions as a channel stopper layer for the NAND cell unit 14. And a conductive layer (70) connected to the semiconductor layer (78). 8. The semiconductor device of claim 7, further comprising a semiconductor layer 76 formed on the semiconductor layer 78 and heavily doped with the same conductivity type as the semiconductor substrate 12. A nonvolatile semiconductor memory device, characterized in that it is in contact with a heavily doped semiconductor layer (78). 7. A nonvolatile semiconductor memory device according to claim 5 or 6, wherein the conductive layer (72) is formed between two adjacent data transfer lines (BL). 7. The nonvolatile semiconductor memory device according to claim 5 or 6, wherein the conductive layer (72) is formed between two adjacent data transfer lines (BL). 7. The data storage transistor (M) according to claim 5 or 6, wherein each data storage transistor (M) has a carrier storage layer (41) provided on the substrate (12) insulated. And a data link between the serial circuit of the data storage transistor (M) and a corresponding data transfer line. The method of claim 11, wherein the switching transistor QS1 is disposed on the first substrate 40 and the first conductive layer 40 insulated from the semiconductor substrate 12. And a two-layered gate electrode having a second conductive layer (42) at least partly connected thereto. The method of claim 12, further comprising a contact means (70) provided at predetermined intervals along the two-layer gate electrode to electrically connect the first layer (40) with the second layer (40). Nonvolatile semiconductor memory device. 15. The nonvolatile semiconductor as claimed in claim 13, wherein the first layer (40) and the carrier storage layer (18) are formed in a first polycrystalline semiconductor layer insulatedly disposed on the semiconductor substrate (12). Memory. 15. The nonvolatile semiconductor memory according to claim 14, wherein said second layer (42) and said control gate layer (20) are formed in a second polycrystalline layer insulatedly disposed on said first polycrystalline semiconductor layer. Device. 16. The nonvolatile semiconductor memory device according to claim 15, wherein said contact means comprises a contact layer (70) formed in a third polycrystalline semiconductor layer located on said second polycrystalline semiconductor layer. 17. The nonvolatile semiconductor memory device according to claim 16, wherein the conductive layer (72) is at least partially overlapped with the contact layer (70). 18. The nonvolatile semiconductor memory device according to claim 17, wherein the conductive layer (72) is made of a metal layer having an insulating layer disposed on the contact layer (70).

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