KR950004865B1 - Non-volatile semiconductor memory device with nand cell structure - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory with NAND Cell Structure

1 is a diagram schematically showing the overall circuit configuration of an EEPROM according to a first embodiment of the present invention.

2 is a plan view of a NAND cell block including a selection transistor and a memory transistor connected in series for the construction of the NAND cell structure.

3 is a cross-sectional view of the cell block taken along the line III-III of FIG.

4 is a cross-sectional view of the cell block taken along the line IV-IV of FIG.

5 is an equivalent circuit diagram of the cell block shown in FIG.

6 shows typical waveforms of voltage signals generated in the main part of the EPROM of the present invention in the data erase mode and the data write mode.

Fig. 7A shows the electronic transportation mechanism of the memory cells of the EPROM in the data erasing mode.

Fig. 7 (b) shows the electronic transportation mechanism of the memory cells of the EPROM in the data recording mode.

8 shows typical waveforms of voltage signals generated in the main part of the EPROM in the data reading mode.

9 is a cross-sectional view of a modified memory cell transistor that may be used in an EPROM.

10 is a diagram schematically showing the overall circuit configuration of an EEPROM according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a memory cell matrix structure of a cell unit included in the EEPROM shown in FIG.

FIG. 12 shows typical waveforms of voltage signals generated in the main part of the EEPROM shown in FIG. 10 in the data write mode.

FIG. 13 is a cross-sectional view of a NAND cell block including the memory cell matrix shown in FIG. 11 and having two select transistors. FIG.

Fig. 14 shows typical waveforms of voltage signals generated in the main part of the EPROM according to the second embodiment in the data erasing mode and the data writing mode.

FIG. 15 is a graph showing erase and write characteristics of an EEPROM. FIG.

Fig. 16 shows a partial memory cell matrix arrangement of a modification of the device of the second embodiment.

FIG. 17 shows typical waveforms of voltage signals generated in the main part of the modified EEPROM in the data erasing mode. FIG.

18 is a diagram showing a preferred decoder circuit configuration as a decoder circuit included in EEPROMs according to an embodiment of the present invention.

FIG. 19 shows a partial memory cell matrix arrangement of an EEPROM according to another embodiment of the decoder circuit shown in FIG.

FIG. 20 shows typical waveforms of voltage signals generated in the decoder circuit shown in FIG. 18 and in the main portion of the NAND cell array shown in FIG. 19 in the data write mode.

FIG. 21 is a diagram showing a circuit arrangement of a modification of the decoder circuit shown in FIG.

FIG. 22 is a diagram showing the circuit arrangement of another modified example of the decoder circuit shown in FIG.

Fig. 23 is a sectional view of a NAND cell block of an EEPROM according to the present invention.

FIG. 24 shows typical waveforms of voltage signals generated in the main part of the EEPROM in the data erase mode and the data write mode.

25 is a partial plan view of a variation of a NAND memory cell transistor that may be used in an EEPROM in accordance with the present invention.

FIG. 26 is a cross-sectional view of the memory cell transistor taken along the line XXVI-XXVI of FIG. 25. FIG.

FIG. 27 is a sectional view of a modification of the NAND cell array shown in FIG.

* Explanation of symbols for main parts of the drawings

10: cell array portion 12: address buffer portion

14,86: Thermal Decoder 16,82: Row Decoder

18: line 20: data input circuit section

22: sense amplifier circuit 24: output buffer

QL: Data input transistor 30: Contact hole

32: P-type silicon substrate 34: connection line (aluminum strip)

M1 ~ Mn: Memory cell transistor QS: Select transistor

QS1: first selection transistor QS2: second selection transistor

QCm: MOSFET 36: device isolation layer

WL: Parallel word line BL: Bit line

SGi: Gate control line CLm: Thermal control line

38: first polycrystalline silicon layer 38 ': floating gate

40: thermal oxidation insulating layer (first gate insulating layer)

42: second polycrystalline silicon layer (control gate layer)

44: gate insulating layer (second gate insulating layer) 44a, 44b: thermal oxidation layer

44b: silicon nitride layer 46: polycrystalline silicon layer

48,50,52,54,56,58,112,162: N ⁺ type diffusion layer

150,152,154,156,158,160: N type diffusion layer

60: CVD insulating layer Vbit: bit line potential

Vsg: Gate potential of select transistor (QS)

Vw1, Vw2, Vw3, Vw4: Word line potential N1, N2: Node

80: memory cell part 80: memory cell part

84: detection amplifier 88: latch circuit

90: Hang address buffer 91,93: Address signal terminal

92: open buffer Buffer 94: data input buffer

96: I / O detection amplifier 98: data output buffer

: 기록제어신호CGi: Control Gate

: Recording control signal

E: Erase control signal G1: 3 input NAND gate

G2, G3: NOR gate Cfs, Cfc: Combined capacitance

: 칩이네이블신호100: SRAM

: Chip enable signal

: 출력이네이블신호

: 기록이네이블신호

: Output enable signal

: Record enable signal

: 대기/작업신호 110 : 도전층R /

: Standby / work signal 110: conductive layer

120,130,140: Decoder circuit D1 ~ D8: Decoder

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor storage body, and more particularly to an EPROM having a large storage capacity.

[Traditional Technology and Problems]

As the demand for high performance and high reliability of digital computer systems increases, there is a great demand for the development of semiconductor memory having a storage capacity large enough to replace the existing nonvolatile data storage devices such as magnetic floppy disk units. come. Electrically erasable programmable readonly memory (EEPROM), which is currently used, is not sufficient to replace the magnetic floppy disk unit in terms of data storage capacity despite high reliability, high speed data reading and data writing. That is, each memory cell in a conventional EEPROM is typically composed of two transistors, and the data write / erase operations are randomly performed one byte at a time, thus providing a storage capacity large enough to replace the peripheral data storage device. High density integration is difficult to expect.

As a large-capacity nonvolatile semiconductor memory, an EPROM having a " NAND cell " structure is described in [VLSI symposium], R. Stewart et al., RCA, 1984, PP. 89-90. In this EEPROM, a single transistor is used as each memory cell, and a single contact between a memory cell array arranged on a substrate and a corresponding bit line for forming a " NAND cell " It is provided. Therefore, the area occupied by the memory cells in the substrate is reduced compared to the conventional EEPROM, thereby improving the degree of integration.

However, the EPROM has a problem of low reliability in terms of operation. That is, when data is written to a selected cell, an unselected cell (or a plurality of cells) adjacent to the selected cell may become electrically unstable. In this case, a cell in which data is not selected (or a plurality of cells) A malfunction recorded by) will occur. Malfunctions in which data is written to these unselected cells (or plural cells) will significantly degrade the reliability of the EEPROM.

[Objective of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a new and improved nonvolatile semiconductor memory, and is suitable for high density integration for a large storage capacity and newly improved with high reliability in terms of operation. Another aim is to provide a customized EPROM.

[Configuration and Function of Invention]

In order to achieve the above object, a nonvolatile semiconductor memory device having a NAND cell structure according to the present invention comprises a semiconductor substrate, a parallel bit line provided on the substrate, and a rewritable memory cell connected to the bit line. have. The memory cell is composed of a NAND cell block each having a select transistor connected to a corresponding bit line, and a series array of memory cell transistors having one end connected to the selection transistor and the other end connected to the substrate potential. Each cell transistor has a floating gate and a control gate. Further, in each cell transistor, the coupling capacitance between the floating gate and the substrate is set smaller than the coupling capacitance between the floating gate and the control gate. Further, a parallel word line is provided on the substrate connected to the control gate of the transistor across the bit line.

The decoder circuit is connected to the bit line and the word line so that the selection transistor of any cell block including the selected memory cell in the data write mode is turned on to electrically connect the cell block to the corresponding bit line. Applies the voltage to the word line connected to the selected cell of the cell block, applies the voltage level to the word line connected to the selected cell of the cell block, and stores a memory cell (or a plurality of memory cells) located between the selected cell and the corresponding bit line. The desired data to the selected memory cell by applying the " H " level voltage to the selected memory cell by applying the " H " level voltage to the memory cell (or a plurality of memory cells) of the cell block located between the selected cell and the substrate. To be recorded.

In order to continuously write data to the memory cells included in a cell block, the decoder circuit first selects the memory cell disposed farthest from the corresponding bit line, and finally the memory cell of the memory cell disposed closest to the bit line. The remaining memory cells are sequentially selected according to the position order. The memory cells in which data is written are continuously supplied with an LV level voltage at their gates, and other memory cells are selected. The decoder circuit erases the above-mentioned cell transistors simultaneously by applying a voltage of HV level to word lines connected to the control gates of all memory cells included in a certain cell block in the data erasing mode.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to exemplary drawings.

1 shows the cell array unit 10 and the address buffer unit 12. A diagram showing an EEPROM according to a first embodiment of the present invention, which comprises a column decoder 14 and a row decoder 16, wherein the cell array unit 10, the address buffer unit 12, the column decoder 14, and hangs. The coders 16 are all formed on a chip substrate (not shown).

A predetermined number of parallel bit lines BL1, BL2, ..., BLm are formed on the substrate so as to be insulated from each other (hereinafter referred to as " BLi "). Each bitter line is connected to a plurality of memory cells, which are called sub-arrays (hereinafter referred to as " NADN cell blocks " or simply " cell blocks "); B11, B12 ... Which is composed of one select transistor QS and a predetermined number of memory cells M (hereinafter, one of the memory cells is denoted Bij). Is composed of single gate MOSFET, and each memory cell is basically composed of double gate MOSFET with floating gate and control gate.

In each NAND cell block Bij, the series connection of the cell transistors is connected at one end to a corresponding bit line and the other end is grounded to the substrate. In this embodiment, the memory cells of each NAND cell block Bij are composed of memory cell transistors M1, M2 ... Mn, which are connected in series to form a so-called " NAND cell EPROM structure. In the following description, the number 메모리 n ＂of the memory cell transistors included in each NAND cell block Bij is set to four only for simplicity of the drawing, but in practical applications, the number of memory cells＂ n ＂is 8 or 16 It may be.

Parallel word lines WL11, WL12, ..., WL1n, WL21, ..., WL2n connected to the row decoder 16 are provided on the substrate in a form orthogonal to the bit line BL. As illustrated, the selection transistor QS and the memory cell transistor M are positioned at the intersection of the bit line BL and the word line W1 to form a cell matrix. Here, the line SG1 connected to the selection transistor QS of each NAND cell block Bij is referred to as a "gate control line" below.

The parallel column control lines CL1, CL2, ..., CLm pass vertically on the substrate with respect to the bit lines BL1, BL2, ..., BLm, and the MOSFETs QC1, QC2, ..., QCm are connected to the heat lines CL1, CL2, ..., CLm is located at the intersection of the bit lines BL1, BL2, ..., BLm, and the drains of the MOSFETs QC1, QC2, ..., QCm are commonly connected to the line 18. As shown, the line 18 is connected to transistors including a data input circuit 20, a sense amplifier circuit 22, an output buffer 24 and a data input transistor QL.

As shown in FIG. 2, a contact hole 30 is formed on the P-type silicon substrate 32 doped with a small amount of impurities in the NAND cell block (e.g., B11 '). In particular, a connected [(aluminum strip) 34 extends across the series coupling of transistors QS, M1 to M4, which are arranged in the NAND cell block B11. It overlaps with the gate of QS, M1-M4).

As shown in FIG. 3 and FIG. 4, the transistor array of the NAND cell block B11 is formed in the substrate surface region surrounded by the isolation layer 36 formed on the substrate 32. As shown in FIG. As clearly shown in FIG. 3, like the other memory cells, the MOSFET M1 forming one memory cell is first polycrystalline silicon layer 38 insulated by the thermal oxidation insulating layer 40 on the substrate 32. ) And a second polycrystalline silicon layer 42 cut off by the gate insulating layer 44 on the first polycrystalline silicon layer 38.

Here, the first polycrystalline silicon layer 38 functions as a floating gate of the MOSFET (Mi), and the second polycrystalline silicon layer 42 functions as a control gate of the MOSFET (Mi). The second polysilicon layer 42 used is formed along one direction to form a word line. (The word line WL11 is for the memory cell M1). As shown in FIG. 4, the selection transistor QS has a polycrystalline silicon layer 46 arranged insulated on the substrate 32. The polycrystalline silicon layer 46 serves as a control gate of the selection transistor QS. Function.

As shown in FIG. 4, the N ⁺ type diffusion layers 48, 50, 52, 54, 56, 58 doped with a large amount of impurities in the surface portion of the substrate 32 are transistors QS, M1, M2, M3, M4. ) it is formed by a self-alignment process (self-aligned process), that uses the gate of, N ⁺ diffusion layer of which functions as a source and a drain of the transistor. For example, the N ⁺ diffusion layers 48 and 50 function as the drain and the source of the select QS, respectively, and the N ⁺ diffusion layers 50 and 52 similarly function as the drain and the source of the cell transistor M1, respectively. On the other hand, the series coupling of the transistors arranged to form the " NAND cell " structure is represented by an equivalent circuit as shown in FIG.

The entire surface of the layer structure is covered with a CVD insulating layer 60, and a through hole is formed in the CVD insulating layer 60 as shown, which is a series transistor array of NAND cell blocks Bij. It serves as a contact hole 30 for. The contact hole 30 is located on the drain diffusion layer 48 of the select (QS), and the aluminum strip 34 passes over the CVD insulating layer 60 and passes through the contact hole 30 through the select transistor ( It is in contact with the drain diffusion layer 48 of QS). The aluminum strip 34 is selectively connected to a data input line or a data output line.

In each memory cell Mi, the coupling capacitance CFS between the floating gate 38 and the substrate 32 is preferably set smaller than the coupling capacitance Cfc between the floating gate 38 and the control gate 42. . As shown in FIG. 2, the pattern layout of the series coupling of transistors in the NAND cell block B11 is designed according to the scale of 1 mu m, in particular the view-gate width of each cell transistor Mi The width and channel width of the control gate are 1 mu m, the spacing between the gate layers of adjacent cell transistors is 1 mu m, and the width of the aluminum strip 34 is 1 mu m. For example, the first gate insulating layer 40 (see FIG. 3) is formed of a thermal oxide film having a thickness of 20 nm, and the second gate insulating layer 44 (see FIG. 3) is formed of a thermal oxide film having a thickness of 35 nm. do. Assuming that the dielectric constant of the thermal oxide film is ＂ε＂, the coupling capacitance is

[Equation 1]

Cfs = ε / 0.02

Cfs = 3ε / 0.035

It becomes Therefore, the above condition satisfies Cfs < Cfc.

Next, the operation mode of the EPROM according to the present invention will be described with reference to FIG. In FIG. 6, the potential of the corresponding bit line is represented by VV, the gate potential of the selected transistor QS is represented by Vsg, and the potentials applied to the word lines WL11, ..., WL14 are respectively represented by VV1, VV2. ＂,＂ Vw3 ＂,＂ Vw4 ＂.

EPROM erases data stored in all memory cells at the same time (because of this feature, the EEPROM according to the present invention is called flash EEPROM (dlfk)), where all cell transistors (Mi) in each NAND cell block (Bij) The data stored in) are erased simultaneously in the following manner. In other words, in the NAND cell blocks B11, B12, ..., B1m connected to the word lines WL11 to WL1n, the memory cells M1 to M4 are included in the GK. For example, it is necessary to apply + 20V to the word lines WL11 to WL1n, and to apply the HV level voltage to the heating lines CL1 to CLm and the node N2.

Here, the mechanism of data erasing will be described in detail by taking the cell block B11 as an example, but the same mechanism is applied to other NAND cell blocks Bij. In the simultaneous erasing mode (corresponding to the time interval between t1 and t2 in FIG. 6), the bit line potential Vbit for the NAND cell block force B11 is set to the low potential OV and the gate of the selection transistor QS. The potential Vsg is set to a high potential 20V. At the same time, as shown in FIG. 6, the word lines WL11, WL12, WL13, and WL14 are supplied with the H level voltage (for example, the H level is 20V). As a result, in each of the cell transistors M1 to M4, electrons are tunneled from the substrate 32 to the floating gate 38 through the gate insulating layer 40 (as shown in FIG. 6, the potential VS becomes OV). Maintained]. The threshold becomes positive. In the simultaneous erase mode, electrons in a cell transistor Mi move almost uniformly between the substrate 32 and the floating gate 38 as indicated by arrow 70 in FIG.

In the data write mode, the data input transistor QL is turned on by the control of the data input circuit 20. Here, to explain the NAND cell block B11 as an example, for example, the column decoder 14 applies the H level voltage (or L level voltage) to the heating wire CL1, and the remaining heating lines CL2 to CLm. Apply LV level voltage to the At this time, the row decoder 16 applies the H level voltage to the gate control line SG1 connected to the selection transistor QS in the NAND cell block B11 to turn on the selection transistor QS.

The memory cells M1 to M4 in the selected NAND cell block B11 are written in the following sequence. That is, the memory cell M4 located farthest from the contact hole 30 in the cell block B11 is written first, and then the memory cell M3 and the memory cell M2 are sequentially written, and the contact hole The memory cell M1 nearest from 30 is last written.

While the memory cell M4 is being written (i.e., the interval between t2 and t3), the potential of the aluminum strip 34 connected to the drain of the selection transistor QS, that is, the potential of the corresponding bit line BL1 ( Vbit) is set to a high potential (20V) or a low potential (OV) depending on whether the digital binary data to be recorded is # 1 or # 0, and the gate potential (Vsg) of the selection transistor QS is? H. It is set to the power level (20V). The potential Vw4 of the word line WL4 connected to the control gate 42 of the selected memory cell M4 is set to a low potential, and the potentials Vw1, Vw2, and V3 of the word lines WL1, WL2, and WL3 are set. Vw3) is fixed at the high potential level 20V.

In this state, the select transistor QS is brought into a conducting state, so that the bit line potential Vbit takes the channels of the transistor series array of the NAND cell block B11 to the drain layer 56 of the selected memory cell transistor M4. Is sent. Since the LV level voltage is applied to the control gate 42 of the cell transistor M4, the memory cell M4 remains in a non-conductive state so that the floating gate 38 in the memory cell M4 and the substrate ( Between 32) a high field is created.

As described above, since the coupling capacitance Cfs between the floating gate 38 and the substrate 32 is smaller than the coupling capacitance Cfc between the floating gate 38 and the control gate 42, the selected cell transistor M4 is selected. The electrons accumulated in the floating gate of the) are discharged to the deep plate 32 through the gate insulating layer 40 by the tunnel effect (as indicated by arrow 72 in FIG. 7 (b), the electrons are discharged by the floating gate 38). And the diffusion region 56 heavily doped with impurities.] In FIG. 7 (b), the voltage applied to the N ⁺ diffusion layer 56 is represented by " 18V " This is because Vbit) receives the voltage drop of the threshold voltage of the selection transistor QS. As a result, the threshold becomes negative. According to this embodiment, this means that data # 1 'is written to the memory cell M4. During the interval between t2 and t3, a high voltage 20V is applied to the control gates of the memory cells M1, M2, M3 that are not selected so that discharge of electrons from the floating electrode as in the selected memory cell M4 is prohibited. .

Then, when the memory cell M3 is selected (ie, during the interval between t3 and t4), the potential Vw3 of the word line WL13 connected to the control gate 42 in the memory cell M3 is set to the sixth. As shown in the figure, it is set to the low potential (0V) similarly to the memory cell M4. In this case, the gate voltage Vsg of the selection transistor QS and the voltages Vw1 and Vw2 of the word lines WL11 and WL12 are maintained at the HH level 20V. When the memory cell M3 is selected, the word line WL14 connected to the memory cell M4 on which data is written is maintained at a low voltage level, thereby eliminating or erasing data written to the memory cell M40. Then, data is sequentially recorded in the memory cell M2 and the memory cell M1 in the same manner as described above.

During the time when data is written into the memory cell M2 (i.e., the interval between t4 and t5), the potentials Vw4 and Vw3 of the word lines WL14 and WL13 of the memory cells M4 and M3 in which the data is completely written. Is maintained at the low level (0V). During the time (interval between t5 and t6) when data is last written to the memory cell M1, the potentials Vw4, Vw3, Vw2 of the word lines WL14, WL13, WL12 of the memory cell in which the data is written are It is maintained at the L 'level (0V).

As shown in FIG. 6, when the bit line voltage Vbit is set to 20 V, data of logic # 1 is written into the selected memory cell, and when the bit line voltage Vbit is set to ON voltage, the selected memory cell is selected. Logic data is recorded. As a result, a desired pattern of logic # 1 'and # 0' data is stored in the memory cells M1 to M4.

As shown in FIG. 8, in the data read mode, the gate voltage Vsg of the selection transistor QS is set to a voltage of 5V corresponding to the logic # 1 level. The low voltage (0V) is applied to the word line connected to the selected memory cell, and 5V is supplied to the word line connected to the remaining unselected memory cells. That is, only the cell Mi connected to the word line to which 0V is applied is selected.

As shown in FIG. 8, when low voltage (0V) is sequentially applied to the control gates of the memory cell transistors M1, M2, M3, and M4 in the NAND cell block B11, data is transferred from the memory cell M1 to the memory cell. It is sequentially read out up to (M4).

When 0V is applied to the word line WL11 and the corresponding transistor M1 is selected, the cell transistors M2 to 4 are turned on because 5V is applied to the other word lines WL2WL3 and WL4. The selected cell transistor M1 is turned off when its threshold is positive, and is turned on when the selection threshold is negative. Therefore, whether or not current flows through the cell block B11 including the selected memory cell M1 is determined only depending on the data writing state. When the memory cell M1 is selected, it is possible to discriminate the data stored in the memory cell M11 by detecting whether a current flows through the NAND cell block B11 or not. The above manner of reading also applies to other cells M2 to M4.

This configuration can effectively perform simultaneous erasing and selective recording of data. In particular, by employing such a special technique of applying a voltage as described above in the data recording mode, it becomes possible to perform an effective data recording / erase operation with improved reliability. Further, for example, in the NAND cell block B11, the memory cell M4 furthest from the contact hole 30 is written first, then the memory cells M3 and M4 are sequentially written, and finally the contact hole 30 The memory cell M1 closest to is written. Because of this, once written cell data is not destroyed or erased during subsequent write operations, which greatly improves the reliability of the EEPROM operation. For example, if data of logic # 0 is written to memory cell M4 after data of any one of the logic # 1 'of memory cells M1 to M4 is written, data # contained in cells M1 to M4 is recorded. The cell in which 1 ms is stored is forcibly set to the data erasing mode and data is undesirably erased. This undesirable phenomenon can be prevented by performing the data write operation of the above-described cell write sequence.

The EEPROM can be modified to use a memory cell of a mixed structure, each having a cross-sectional structure as shown in FIG. 9, where the second gate insulating layer 44 is formed of the floating gate 38 from the control gate 42. FIG. Adopted for electrical insulation, it is made of a laminated structure of the thermal oxidation layer 44a, the silicon nitride layer 44b and the thermal oxidation layer 44c.

The first gate insulating layer 40 has a thickness of 20 nm, and the stacked structure of the layers 44a, 44b, and 44c also has a thickness of 20 nm. By such a configuration, each of the memory cells Mi may have a coupling capacitance Cfs smaller than the coupling capacitance Cfc.

Referring to FIG. 10, the EEPROM according to the second embodiment of the present invention has an additional data buffer memory section having a larger capacity than the latch circuit, and this data buffer memory section effectively implements page mode data addressing. It is adopted to sequentially store the data applied to the latch circuit to perform.

As shown in FIG. 10, the memory cell portion 80 is coupled to the row decoder 82, the sense amplifier 84, and the column decoder 86, almost like the first embodiment. As shown in FIG. 11, the memory cell unit 80 has a memo located at the intersection of the parallel bit lines BL1, BL2, ..., BLm (m = 256 in this embodiment) and the parallel word lines WL1, WL2, ... It consists of lysels (M1, M2, ...). The memory cell transistors included in the cell block Bij are connected in series to form a " NAND cell " structure as in the above-described embodiment. One end of the series array of memory cell transistors M1, M2, ..., M4 is connected to the corresponding bit line BL1 via the first selection transistor QS1, and the sense amplifier 84 applies an output voltage. It is connected to the bit line BL for detection, and the other end of the serial array of the cell transistors M1, M2, ..., M4 is connected to the substrate potential Vs via the second selection transistor SQ2.

The latch circuit 88 is connected to the column decoder 86 to temporarily store input data input to the memory cell 80 or output data output from the memory cell unit 80. The latch circuit 88 has a latch capacitance corresponding to (the same) the number of bit lines BL of the memory cell portion 80, which is at least smaller than the bit bow. For example, if the data input operation is time-divided into four input sub-operations, the capacity of the latch circuit 88 is reduced to one quarter of the bit bow. The row address buffer 90 having the address signal terminal 91 is connected to the row decoder 82, and the open address buffer 92 having the address signal terminal 93 is connected to the column decoder 86. Input data is applied to the latch circuit 88 from the I / O front end via the data input buffer 94, and the output data from the latch circuit 88 is the I / O sense amplifier 96 and the data output buffer 98. It is supplied to I / O end via

A static random access memory (SRAM) 100 is additionally provided between the data input buffer 94 and the latch circuit 88t, which has a larger memory capacity than the latch circuit 88. . In this embodiment, the SRAM 100 is 256x4 bits (multiplied by the number of bit lines BL and the number of memory cells M1 to M4 included in each NAND cell block Bij) or 1K bits. It has a memory capacity. That is, the SRAM 100 has a static memory cell matrix having a serial array of static memory cells of the number corresponding to the number of stages in the NAND cell (4 in this embodiment). It has a page length corresponding to the number of BL).

The data addressing operation of the EEPROM in the page mode will be described with reference to the timing chart shown in FIG.

는 그 레벨이 ＂L＂일 때 EEPROM을 이네이블시킬 수 있는 칩이네이블신호이고,

는 그 레벨이 ＂H＂일 때 기록모드가 되도록 하는 출력이네이블신호이며,

는 그 레벨이 ＂H＂에서 ＂L＂로 바뀔 때 어드레스데이터의 입력을 허락하고 다시 ＂H＂로 되면 입력데이터의 입력을 허락하는 기록이 네이블신호이다.

는 기록동작동안 ＂L＂로 되고 메모리가 기록동작 등에 있다는 것을 외부에 알리는 대기/작업(Ready/Busy)신호이다. 제10도에 도시된 SRAM(100)이 설치되어 있지 않은 것으로 가정하면, 1페이지(본 실시예에서는 비트선의 개수, 즉 256)에 대응하는 횟수만큼 기록이네이블신호(

)가 ＂H＂→＂L＂→＂H＂의주기를 반복함으로써 고속으로 데이터를 기입하는 것이 가능하게 된다. 1페이지의 데이터는 비트선에 접속된 래치회로(88)에 저장되고, 이렇게 래치된 데이터는 비트선에 전송되어 어드레스 데이터에 의해 지정된 메모리셀로 기록되는바, 이는 잘 알려진 페이지모드동작이다. 예컨대, 페이지모드를 사용하지 않고 256비트의 데이터를 모두 기록하기위해서는, 소거시간이 10msec이고 기록시간이 10msce×256인 경우에 2.5sec가 걸린다. 한편, 페이지모드를 사용하면 256비트의 데이터를 기입하는데 걸리는 시간은(1μsec×256+10msec)=20.2msec가 된다. 그 결과, 데이터기록속도면에서 125배 만큼 증가하게 된다.In Figure 12,

Is the chip enable signal that enables EEPROM when the level is ＂L＂,

Is the output enable signal to enter the recording mode when the level is ＂H＂,

When the level changes from ＂H＂ to ＂L＂, the write signal allows the input of the address data, and when the level goes back to ＂H 기록, the record is the enable signal.

Is a ready / busy signal during the write operation to notify the outside that the memory is in write operation or the like. Assuming that the SRAM 100 shown in FIG. 10 is not provided, the write enable signal (the number corresponding to one page (in this embodiment, the number of bit lines, i.e., 256) is recorded.

By repeating the cycle of HH? LL? HH, data can be written at high speed. Data of one page is stored in the latch circuit 88 connected to the bit line, and the latched data is transferred to the bit line and written to the memory cell designated by the address data, which is a well-known page mode operation. For example, to record all 256-bit data without using the page mode, it takes 2.5 sec when the erase time is 10 msec and the write time is 10 msce x 256. On the other hand, when the page mode is used, the time taken to write 256 bits of data is (1 mu sec x 256 + 10 msec) = 20.2 msec. As a result, the data recording speed is increased by 125 times.

According to this embodiment, as shown in FIG. 10, the SRAM 100 is provided together with the latch circuit 88. As described above, the SRAM 100 includes one page (256 bits) x NAND cell 4 ), That is, has a capacity of 1K bits.

)의 ＂H＂→＂L＂→＂H＂주기가 256×4회 반복된다. 상기 SRAM(100)으로 기록되는 데이터에서 먼저 M41,M42,…,M4n(n=256)의 1페이지 데이터가 래치회로(88)로 전송되고, 이렇게 전송된 1페이지 데이터는 상술한 동작방법에 따라 제11도의 워드선(WL4)을 따라 256개의 메모리셀로 동시에 기록된다. 그후, M31,M32,…,M3n의 1페이지 데이터가 상기 SRAM(100)에서 래치회로(88)로 전송되어 워드선(WL3)을 따라 256개의 메모리셀에 동시에 기록된다. 이와같이, SRAM(100)에 저장된 1K비트의 데이터가 순차적으로 래치회로(88)에 기록된다.This makes it possible to write data randomly to any address of the SRAM 100 by using the page mode. That is, in order to first write 1K bits of data to the SRAM 100, a write enable signal (

The cycle of ＂H＂ → LL ＂＂ H 의 is repeated 256 × 4 times. In the data written to the SRAM 100, first M41, M42,... One page data of M4n (n = 256) is transferred to the latch circuit 88, and the one page data thus transferred is simultaneously stored into 256 memory cells along the word line WL4 of FIG. Is recorded. Then, M31, M32,... One page data of M3n is transferred from the SRAM 100 to the latch circuit 88 and simultaneously written to 256 memory cells along the word line WL3. In this manner, 1K bits of data stored in the SRAM 100 are sequentially written to the latch circuit 88.

When the SRAM 100 is not provided, it takes 20.2 msec to record one page data in the page mode as described above, and 20.2 (msec) x 4 = 80.8 msec to record 1K bits. On the other hand, according to the embodiment in which the SRAM 100 having a 1K bit capacity is installed, the time required for writing 1K bits in page mode is the time required to write 256 bits of external data (1 μsec × 256) + erasing time (10 msec). ) + Recording time (10 x 4), i.e. 50.2 msec (this connection performs data erasing only once). That is, by installing the SRAM 100, the recording time can be reduced by about 62%.

As described above, this embodiment can provide an EEPROM having high reliability by the NAND cell structure of the memory cell which performs the write and erase operations by the tunnel current between the substrate and the floating gate as in the case of the above embodiment. Will be. In addition, by providing a buffer SRAM having a capacity larger than one page together with the latch circuit 88, data writing can be made faster in the page mode. According to the above embodiments, four memory cells are connected in series to constitute one NAND cell, but the number of memory cells constituting one NAND cell is not limited to four. As the number of memory cells in the NAND cell increases, data writing can be made faster in the page mode. The eight memory cells increase the data writing speed by 56%. Then, a buffer memory for output data may be provided.

Another important feature of the second embodiment is that two select transistors QS1 and QS2 are provided in each NAND cell block Bij. As a typical example, the cross section of the NAND cell block B1 is shown in FIG.

In FIG. 13, the same reference numerals are attached to the same parts as FIG. 4, which is the drawing of the first embodiment, and detailed description thereof will be omitted. The wirings connected to the first select transistor QS1 and the second select transistor QS20 are denoted by the values 'SG1' and 'SG2', respectively. As shown in FIG. 13, the selection transistor QS2 is a substrate 32. As shown in FIG. And N-type diffusion layers 58 and 112 doped with a large amount of impurities formed on the surface of the substrate 32 in a self-aligned manner with the gate 110. ^{The plus} layer 58 is connected to the substrate potential (ground potential) VS.

The second selection transistor QS2 is provided to prevent the generation of any current flow path in the NAND cell array even when the threshold voltage of the recording cell in which data is written varies. That is, when the threshold voltage level changes in the cell in which data is written, the second selection transistor QS2 is in a non-conducting state, and the NAND cell array is insulated from the chip substrate voltage, thereby preventing generation of a current flow path. If necessary, the second selection transistor QS2 is in a non-conductive state at the same time as the first selection transistor QS1.

As shown in FIG. 14, when the EEPROM enters the simultaneous erasing mode, the gate control signals of the L level (0 V) are supplied to the gates of the first and second selection transistors QS1 and QS2, respectively. Therefore, the selection transistors QS1 and QS2 are in a non-conductive state such that the series arrays of the memory cell transistors M1 to M4 in the NAND cell block B1 are electrically separated from the corresponding bit lines BL1. That is, the drain and source N ⁺ diffusion regions 48, 50, 52, 54, 56, 58 and 112 of the NAND cell transistors M1 to M4 are in the mode electrically floating state, so that the connection to the substrate potential Vs is completely made. It is prohibited. In this state, the simultaneous erase operation ('flash erase') as in the first embodiment is performed. This configuration makes it possible to effectively avoid erroneous erasing in the simultaneous erasing mode, for the following reasons.

After erasing, the threshold of the memory cell should be lower than the " 1 " level voltage applied to the control gate of the unselected memory cell when data is read out, and the threshold of the memory cell after writing should be as low as possible to improve the sensitivity. According to the present invention, when the drain and the source of the NAND cell remain in the floating state in the erase mode, the drain having a high electron density becomes smaller than when grounded from the source to the floating gate, so that the change in the threshold value can be made small.

As shown in FIG. 14, in the following data write mode, when the EEPROM is in the data write mode, the gate control signals of the H level (23 V) are supplied to the gates of the first and second select transistors QS1 and QS2. do. Therefore, the selection transistors QS1 and QS2 are brought into a conductive state to connect the serial array of the memory cell transistors M1 to M4 to the corresponding bit line BL1 and the substrate potential Vs in the NAND cell block B1. . In this state, the same recording operation as in the first embodiment is performed.

Here, the gate control signal 'H' level applied to the selection transistors QS1 and QS2 and the 'H' level of the voltage Vwi applied to each word line connected to an unselected cell (or a plurality of cells) are Each rises to 23V, which is the sum of the bit line voltage Vbit and the threshold of the memory cell M1 in the erased state. First, in the interval between t2 and t3, the memory cell M4 is selected as the LV level voltage is applied only to the word line WL4. At this time, the HH level voltage Vbit is applied to the corresponding bit line B1. In this state, the HV level voltage is maintained in the erased state because no electric field is applied between the control transistor and the substrate in each of the selection transistor QS1 and the memory cells M1 to M3. In the data writing to the memory cell M4, when the L level voltage Vbit is applied to the bit line BL1, the data remains unchanged, which means writing the logical L0 data. This data write operation is performed in the order of the memory cells M4, M3, M2, and M1, that is, in the order of the distance from the contact hole 30 and the bit line BL1. What starts at M4) is essentially the same as in the previous embodiment.

In the data read mode, gate control signals of the H level (23 V) are applied to the gates of the first and second selection transistors QS1 and QS2, respectively. Therefore, the selection transistors QS1 and QS2 are brought into a conductive state to connect the series array of the memory cell transistors M1 to M4 in the NAND cell block B1 to the corresponding bit line BL1 and the substrate potential Vs. . For example, the LV level voltage 0V is applied to the connected word line WL3 of the memocell M3 to read from the memory cell M3, and the unselected cell transistors M1, M2, and M4 are applied. The high voltage is applied to the word lines WL1, WL2, and WL4 connected to these memory cells M1, M2, and M4 to the ON state. Therefore, by detecting whether or not current flows in the NAND cell block B1, it is possible to determine whether the data stored in the selected memory cell M3 is logical # 1 data or logical # 0 data.

FIG. 15 is a diagram showing the erasing and writing characteristics of the NAND cell block Bi in the EEPROM of this embodiment, in which the solid line represents the measured data of the device of this embodiment, and the dotted line is turned off in the erase mode. The measurement data of the comparison device in the case where there is no second selection transistor QS2 that insulates the cell block Bi from the substrate potential Vs is shown. Thus, the NAND cell block Bi is electrically separated from the substrate potential Vs. The device of the embodiment and the comparison device are the same in the recording state. As is apparent from the dotted line 14, the erasing characteristics of the comparative device vary greatly in the positive direction, which is due to the injection of electrons from the source and drain of the NAND cell array. On the contrary, the change in the erase characteristic of the embodiment device changes small in the positive direction as indicated by the solid line 116.

According to the present embodiment, in the simultaneous erase mode, the cell block is forcibly insulated from the substrate potential (Vs) so that the cell block is in an electrically floating state to allow the injection of electrons only from the inverted layer on the surface of the substrate. It is possible to prevent the injection of electrons from the source and the drain. For this reason, it is possible to minimize the positive shift of the cell threshold.

Therefore, since the cell threshold is relatively low in the 'O' state, it is possible to lower the voltage applied to the control gate of the cell which is not selected at the time of reading. In an unselected cell, false erasure that may occur when the control gate voltage becomes high for reading can be effectively prevented. This means that the simultaneous erasing operation according to the present invention has high reliability.

As shown in FIG. 16, the second select transistor QS2 can be modified to be common to the NAND cell blocks B1, B2, ..., Bn connected to the bit line BL. According to this configuration, in the erase mode, the first select transistor QS1 and the common select transistor QS2 of each NAND cell block B1 are simultaneously supplied with the 'L' level voltage (0V) as shown in FIG. And become non-conductive. In this case as well, the same advantages as in the above-described embodiments can be obtained.

18 shows an actual peripheral circuit arrangement 120 suitable for the hangcoders 16,82. In this configuration, the number of memory cells included in each NAND cell block Bi is selected as eight. In this case, as shown in FIG. 19, each ANND cell array has memory cell transistors M1 to M8. have.

As shown in FIG. 18, the decoder circuit 120 includes eight one-bit decoders D1 to D8 for accommodating an eight-bit NAND cell block Bi (e.g., B1), and the decoders D1 to D8. Designates one cell transistor among the cell transistors M1 to M8 in the NAND cell array B1. Each decoder Di is composed of a series circuit of three input NAND gates G10 and an inverter I1 and two input NOR gates G2 and G3. The output node Ni of each decoder Di is an inverter I2, It is connected to the control gate CGi of the corresponding memory cell transistor Mi through I3, I4 .. The input of the three-input NAND gate G1 is connected to receive address data a1, a2, a3. Each of the address data a1, a2, and a3 has a logic level # 1 or a level of logic 0. In the address data a1, a2, a3, each of the levels of logic # 1 and # 0 is level. The combination is such that one of the inverters I1 of the decoders D1 to D8 generates a logic # 1 level.

Each decoder Di and the NOR gate G20 are supplied with an output myth recording control signal ***** of the inverter I1, and the NOR gate G3 is output with an NOR gate G2 and an erase control signal. (E) is supplied.The output node N1 of the first stage decoder D1 is connected to supply a recording signal to one input of the NOR gate G2 of the second stage decoder D2, The output signal of the decoder Di is supplied to the control gate CGi of the corresponding memory cell transistor Mi through the cascade connection of the three inverters I2, I3, I4.

)는 논리 ＂L＂레벨로 되고, 소거제어신호(E)는 기록제어신호(

)가 ＂L＂레벨로 바뀌기 전에 논리 ＂L＂레벨로 된다.In order to write to the NAND cell block Bi shown in FIG. 19 using the decoder circuit 120 configured as described above, address data a1, a2, a3 is first applied to the decoder circuit 120 from the outside. Here, as shown in FIG. 20, it is assumed that the address data a1 and a2 have a logic 'H' level, and the address data a3 has a logic 'L' level. Record control signal

) Becomes a logic L level, and the erase control signal E is a write control signal (

) Goes to the logic level L before the level is changed to level L level.

Since the address data a3 is at the L level level, the decoder D1 is not selected because no output signal of the logical L level is generated at the output node N1. This output signal is supplied to the cell transistor M1 through the inverters I2, I3, and I4 to bring the control gate CG1 to the " H " level, and the output signal of the decoder D1 is connected to the next decoder D2. It is applied to the NOR gate G2.

)가 인가되어 그 출력노드(N2)에서는 ＂L＂레벨의 출력신호가 발생된다. 따라서, 메모리셀 트랜지스터(M2)의 제어게이트(CG2)는 ＂H＂로 되고, 또한 디코더(D20의 출력신호는 다음의 디코더(D3)에 인가된다. 마찬가지로, 디코더(Di)에는 이전의 디코더(Di-1)의 출력신호와 그자체 입력어드레스 데이터가 공급된다. 모든 디코더는 선택된 메모리어드레스가 도착할 때까지 논리 ＂L＂레벨의 출력신호를 발생시킨다.As shown in Fig. 18, the addresses a1, a2,

) Is applied to the output node N2 to generate an output signal of the L level. Therefore, the control gate CG2 of the memory cell transistor M2 becomes HH and the output signal of the decoder D20 is applied to the next decoder D3. Similarly, the decoder Di has a previous decoder ( The output signal of Di-1) and its own input address data are supplied, and all decoders generate an output signal of logic " L " level until the selected memory address arrives.

According to this example, the decoder D5 is supplied with address data a1, a2, a3, all of which are < RTI ID = 0.0 > H 'level, < / RTI > At this time, since the potential of the output node N4 of the previous decoder D4 is L, the potential of the output node N5 of the decoder D5 becomes H. Even though the next decoder D6 is not selected, the output level N6 of the previous decoder D5 is applied to the NOR gate G2 of the decoder D6 as a recording control signal. It becomes the potential of H 'level. The same applies to the output nodes N7 and N8 of the subsequent decoders D7 and D8.

In this method, as shown in FIG. 20, the HH level signal is applied to all of the control gates CG1 to CG4 of the memory cells M1 to M4 arranged on the drain side of the selected memory cell M5. The L level signal is applied to both the control gate CG5 of the memory cell M5 and the control gates CG6 to CG8 of the memory cells arranged on the source side of the selected memory cell M5. When the H level signal is applied to the bit line BL, the channels of the memory cells M1 to M4 are conductive, and a high electric field is applied between the control gate and the substrate of each of the memory cells M4 to M4. As a result, electrons accumulated in the floating gate are discharged to the substrate by the tunnel effect, whereby # 1 data is recorded in the memory cells M1 to M4. In the memocells M6 to M8 arranged on the source side of the selected memory cell M5, no electric charge is applied between the control gate and the substrate, and thus the data already recorded is not destroyed.

In the decoder circuit 120 of FIG. 18, when the erasing control signal E becomes " H ", the output nodes N1 to N8 of the decoders D1 to D8 become the " L " The 'H' level is applied to the control gates CG1 to CG8. In this state, when the bit line BL1 is turned to L, electrons are injected from the substrate into the floating gate in each of the memory cells M1 to M8 to perform a total erase.

The decoder circuit 120 may be modified as shown in FIG. 21. The modified decoder circuit 130 may include the reference address signals V0, V1, V2, and V3 and the input address data a1, a2, and the like. a3) is compared and the HH level voltage is applied to the memory cell (or the control gates (or the plurality of control gates) of the plurality of memory cells disposed at the control gate and the drain of the selected memory cell Mi And applies the L level voltage to a memory cell (or a control gate (or a plurality of control gates) of a plurality of memory cells arranged on the source side of the selected memory cell Mi). Subtraction is used to compare the addresses a1, a2, a3 and the corresponding reference addresses V1, V2, V3, where the subtraction of binary numbers is performed by adding the subtracting '2's complement of the subtraction. , The reference address (V0, V1, V2, V3) is shown in the following table. Is made up of

TABLE 1

The two's complement reference address is used to add to the input address data. In this case, however, only the size relationship between the reference address and the input address is required, and the calculation result itself does not need attention. Therefore, attention should be paid to the carry generation of the adder. The least significant bit a1 of the input address and the least significant bit V3 of the decoder address are applied to the carry generation section of the half adder. The output of the half adder and the next lower bit a2 and the next lower bit V2 are applied to the carry generation section of the full adder. Similarly, the carry generation section of the full adder is used to determine the level of the control gates CG1 to CG8. Assuming that the memory cell M5 is written in the same manner as in the previous embodiment, the input addresses are a1 = 'H', s2 = 'H', and s3 = 'L'. This is regarded as a three-digit binary number " 001 " and added to the decoder addresses V1, V2, and V3. As a result of the addition, the H level voltage is applied to the control gates CG1 to CG, and the L level voltage is applied to the control gates CG5 to CG8. Where V0 is used to detect whether the carry of the calculation up to the most significant bit is positive or negative.

22 shows a configuration according to another embodiment of the decoder circuit 140 of the present invention. The decoder circuit 140 includes (0,0,0), (0,0,1), (010), Eight combination signals of (0,1,1), (1,0,0), (1,0,1), (1,1,0), and (1,1,1) are input addresses (a1, a2, a3), and the decoder circuit 140 is configured such that the H level is applied to any one of CG1 to CG8 for each combination of the input addresses a1, a2, a3.

는 소거제어신호를 나타낸다. 이러한 구성에서 기록시에는 W=＂H＂, E=＂H＂이 인가되는 바, 이 조건하에서 예컨대 입력어드레스신호(a1,a2,a3)로서 (0,0,0)이 인가되면 CG1∼CG7에서는 ＂H＂레벨이 출력되는 반면에 CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M8)이 선택되고, 입력어드레스 신호(a1,a2,a3)로서 (0,0,1)이 인가되면 CG1∼CG6에서는 ＂H＂레벨이 출력되는 반면에 CG7과 CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M7)이 선택되며, 입력어드레스신호(a1,a2,a3)로서 (0,1,0)이 인가되면 CG1∼CG5에서는 ＂H＂레벨이 출력되는 반면에 CG6∼CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M6)이 선택되고, 입력어드레스신호(a1,a2,a3)로서 (0,1,1)이 인가되면 CG1∼CG4에서는 ＂H＂레벨이 출력되는 반면에 CG5∼CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M5)이 선택되며, 입력어드레스신호(a1,a2,a3)로서 (1,0,0)이 인가되면 CG1∼CG3에서는 ＂H＂레벨이 출력되는 반면에 CG4∼CG8에서는 ＂L＂레벨이 출력되므로 메뫼셀(M4)이 선택되고, 입력어드레스(a1,a2,a3)로서 (1,0,1)이 인가되면 CG1∼CG2에서는 ＂H＂레벨이 출력되는 반면에 CG3∼CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M3)이 선택되며, 입력어드레스(a1,a2,a3)로서 (1,1,0)이 인가되면 CG1에서는 ＂H＂레벨이 출력되는 반면에 CG2∼CG8에서 ＂L＂레벨이 출력되므로 메모리셀(M2)이 선택되고, 입력어드레스신호(a1,a2,a3)에서 (1,1,1)이 인가되면 CG1∼CG8에서는 ＂L＂레벨이 출력되므로 메모리셀(M1)이 선택된다.In FIG. 22, W denotes a recording control signal.

Denotes an erase control signal. In this configuration, W = ＂H＂ and E = ＂H＂ are applied during recording. If (0,0,0) is applied as the input address signals a1, a2, a3, under these conditions, CG1 to CG7, respectively. In the CG8, the HL level is output, while in the CG8, the memory cell M8 is selected, and when (0,0,1) is applied as the input address signal a1, a2, a3, CG1 is applied. In the CG6, the HH level is output, while in CG7 and CG8, the LH level is output, so the memory cell M7 is selected, and the input address signals a1, a2, a3 are (0, 1, 0). When this is applied, the 'H' level is output from CG1 to CG5, while the 'L' level is output from CG6 to CG8, so that memory cell M6 is selected and (0, 0) as the input address signal a1, a2, a3. When 1, 1) is applied, the ＂H 이 level is output from CG1 to CG4, while the＂ L ＂level is output from CG5 to CG8, so memory cell M5 is selected, and the input address signals a1, a2, a3 As (1,0,0) When the CG1 to CG3 outputs the H level, the CG4 to CG8 outputs the L level, so the memocell M4 is selected and the input address a1, a2, a3 is (1, 0, When 1) is applied, the ＂H＂ level is output from CG1 to CG2, while the ＂L＂ level is output from CG3 to CG8, so memory cell M3 is selected and (1) is selected as the input address (a1, a2, a3). When, 1,0) is applied, the 'H' level is output at CG1, while the 'L' level is output at CG2 to CG8, so that memory cell M2 is selected and at input address signals a1, a2, a3. When (1, 1, 1) is applied, the " L " level is output from CG1 to CG8 so that memory cell M1 is selected.

FIG. 23 is a sectional view along the lateral direction of a NAND cell block configured in an EEPROM according to a third embodiment of the present invention. In FIG. 23, the same parts as those in FIG. 4 are referred to in FIG. Reference signs are omitted, and description thereof will be omitted.

In FIG. 23, N-type diffusion layers 150, 152, 154, 156, 158, and 160 are formed on the upper surface of the substrate 32 surrounded by the device isolation insulating layer 36. These diffusion layers 150, 152, 154, 156, 158, and 160 are adjacent as in the above embodiments. N ⁺ type, which can be used as a source and a drain of the cell transistors Mi and Mi + 1 and is heavily doped with N-type impurities in the N-type diffusion layer 150 connected to the aluminum strip 34 through the contact hole 30. The diffusion layer 162 is formed so that ohmic contact resistance is low. The N-type diffusion layers 150, 152, 154, 156, 158 and 160 are sources and drains of the NAND cell transistors M1 to M4 having a lower impurity concentration than the source and drain diffusion layers of the transistors forming the peripheral circuit.

Next, a method of manufacturing the NAND cell transistor array will be described.

First, a thermal oxide layer is laminated on the substrate 32 with a thickness of 5 to 20 nm to form a first gate insulating layer 40, and a polycrystal with a thickness of 200 to 400 nm on the first gate insulating layer 40. The silicon layer 38 is formed, and a thermal oxide layer 44 is deposited on the polycrystalline silicon layer 38 to a thickness of 15 to 40 nm to form a second gate insulating layer, and the second control gate insulating layer ( A polycrystalline silicon layer 42, which will function as a control gate of the first select transistor QS1 and the cell transistors M1 to M4, is formed on the 44 with a thickness of 200 to 400 nm. Each memory cell transistor M1 is formed. The parallel word line WL is formed in the control gate 42 of -M4.

In this case, the control gate layer 42 is formed after the etching-patterning process for the floating gate layer 38 of each memory cell transistor Mi in adjacent NAND cells along the channel width direction. The floating gate layer 38 and the control gate layer 42 of Mi) are simultaneously patterned using the same etching mask in the channel width direction. As a result, the floating gate and the control gate in each memory cell transistor Mi are formed to be self-aligning with each other. The source and drain diffusion layers 150, 152, 154, 156, 158 and 160 are formed by injecting N-type impurities (e.g., phosphorus (P)) at an acceleration voltage of 40 kV and a dose of 7 x 10 ¹⁴ / cm 2 using the gate layer as a mask. The maximum impurity concentration in the diffusion layer is set to 10 ¹² / cm 3 or less, and these diffusion layers are formed in a process independent of the manufacturing process for the source and drain layers of the transistors configured in the peripheral circuit of the EEPROM. In the cell transistors M1 to M4 of the NAND cells thus formed, the source and drain diffusion layers (for example, the diffusion layers 152 and 154 in the memory cell transistor M1) overlap the floating gate layer 38 at an interval d. , This gap D is set to 0.5 m or less.

In addition, in the surface region of the diffusion layer 150 connected to the contact hole 30, arsenic is doped by, for example, ion implantation, to form an N ⁺ layer 162. In this case, the ion implantation is performed under conditions of acceleration of 100 kV. The amount is 5 × 10 ¹⁵ / cm 2. Subsequently, ion implantation is performed, followed by heat treatment at a temperature of 950 ° C. for about 30 minutes in an N ₂ gas atmosphere for activation of impurities.

According to this embodiment, since the source and the drain of the transistor constituting the NAND cell array are formed by the diffusion layer doped with a small amount of impurities, the junction break down even if a high reverse voltage is applied to the drain layer in the write mode of the EEPROM. ), And the internal pressure between the floating gate 38 and the corresponding diffusion layer in each cell transistor can be improved, thereby improving the data recording margin. Furthermore, even when the impurity concentration in the silicon substrate 32 increases with the decrease in the impurity concentration in the source and drain diffusion layers, the NAND cell array can be protected from the adverse effects of parasitic field effect transistors.

In the above embodiment, the form of application of the control voltage in the write mode can be modified as shown in FIG. 24. In FIG. 24, SG represents the gate voltage for the selection transistor, and CGi represents the NAND cell transistor (Mi; An example is shown for the control gate voltage), and BL represents the potential on the corresponding bit line.

As shown in FIG. 24, in order to write to the memory cell M4 for the first time in the data write mode, the voltage (word line voltage and selection transistor SG) on the control gates CG1 to CG4 of the cell transistors M1 to M4. The voltage on the gate SG of SG (selection gate voltage) is temporarily set to the ground potential (0V), and then the control gate voltage CG4 of the selected memory cell transistor M4 remains fixed to the ground potential, while the other The control gate voltages CG1 to CG3 of the cell transistors M1 to M3 are changed to the " H " level 23V so that data is written to the memory cell M4.

After data is written to the memory cell M4, the voltage of the corresponding bit line is forcibly logic before the control gate voltage CG3 is lowered to the ground potential to select the next memory cell M3. It is lowered to the ＂level, and this time difference is indicated by＂ τ ＂in FIG.

In addition, the voltage of the selection gate SG changes from the H level 23V to the L level (0 V) in accordance with the change of the control gate voltage CG3. Similarly, after data is written to the memory cell M3, the voltage on the corresponding bit line BL is forced before the control gate voltage CG20 is lowered to the ground potential to select the next memory cell M2. After the data is written to the memory cell M2, the voltage on the corresponding bit line BL is selected so that the control gate voltage CG1 selects the last memory cell M1. The voltage is forcibly lowered to the logic '0' level before being lowered to the ground potential.

By such a configuration, the node between the selected cell transistor Mi and the adjacent cell transistor Mi + 1 at the interval τ before the selection of the memory cell Mi can be set to a low level, and thus the memory cell. Threshold variation can be suppressed to improve the stability and reliability in the data write operation for each memory cell (Mi).

Meanwhile, each of the NAND cell transistors Mi in the above embodiments may be modified to have a cross-sectional structure as shown in FIGS. 25 and 26, which represent the memory cell M1. In FIG. 26, the same parts as those in FIG. 4 or FIG. 23 are denoted by the same reference numerals, and description thereof will be omitted.

According to this modification, the first gate insulation interposed between the silicon substrate 32 and the floating gate layer 38 'as the protrusion 150 is provided on the bottom surface of the floating gate 38. A portion of the layer 40 is thinly formed as shown in FIG. 26, and the drain and source diffusion layers 152 and 154 of the cell transistor M1 are formed on the floating gate layer 38 'on the silicon substrate 32, respectively. The N ⁺ diffusion layer 152 extends to overlap the lower portion of the protruding portion 150 of the floating gate layer 38 'or the lower portion of the thin layer portion 40a of the first gate insulating layer 940. It is. According to this configuration, since the internal electric field of the first gate insulating layer 40 becomes high in the thin layer portion 40a, the carrier between the floating gate 38 'and the drain 152 in the data recording mode or the erasing mode. The movement is made only through the thin layer portion of the gate insulating layer 40. Accordingly, even if the control gate voltage Vcg1 or the word line voltage Vw1 is not set high, carrier movement between the floating gate 38 'and the drain 152 proceeds effectively, resulting in the write / erase characteristics of the EEPROM. In addition to this improvement, speed is also increased.

On the other hand, while the specific embodiment of the present invention has been described above, the present invention can be modified in various ways without departing from the technical gist of the present invention.

For example, in the NAND cell block Bi having the first and second select transistors Qs1 and Qs2, the second select transistor QS2 is employed to selectively connect the NAND cell array to the ground potential Vs. As shown in FIG. 27, the null length L2 is made smaller than the channel length L1 of the first selection transistor QS1 employed to selectively connect the transistor array to the corresponding bit line BLi. In this configuration, the punch-ghrough of the EEPROM can be improved. In the above embodiment, memory cells each having a floating gate are used, but a memory cell having an MNOS structure in which a silicon nitride film and a silicon oxide film form a charge storage layer may be used in the EEPROM according to the present invention.

On the other hand, the reference numerals corresponding to the drawings written in the constituent elements of the claims are for the purpose of facilitating the understanding of the present invention, and the technical scope of the present invention is limited to the embodiments shown in the drawings. It is not.

[Effects of the Invention]

As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device having a NAND cell structure capable of achieving high integration while having high storage capacity and high operation reliability.

Claims (38)

The selection substrate QS connected to the semiconductor substrate 32, the parallel bit lines BLi provided on the semiconductor substrate 32, and these bit lines BLi, and connected to the corresponding bit lines BLi. A plurality of NAND cell blocks Bij having a charge storage layer and a control gate 42 and a series of memory cell transistor arrays connected to the selection transistor QS and the first node N1, In the data write mode, the select transistor QS of the NAND cell block Bij including the selected cell is brought into a conductive state to connect the NAND cell block Bij to a specific bit line BLi coupled thereto. The second voltage lower than the first voltage is applied to the control gate 42 of the memory transistor Mi selected from the specific NAND cell block Bij while applying the first voltage to the specific bit line BLi. A memory cell (or a plurality of memory cells) positioned between the selected cell and the first node N1 A turn-on voltage is applied to each control gate of the Morris cell to cause the selected memory cell transistor to become non-conductive by application of the first and second voltages, thereby tunneling data to the selected memory cell transistor Mi. And a voltage control means for storing data in the selected memory cell transistor (Mi) by recording the data. 2. The coupling capacitance Cfs between the charge accumulation layer and the substrate 32 in each of the memory cell transistors is smaller than the coupling capacitance Cfs between the charge accumulation layer and the control gate 42. Nonvolatile semiconductor memory device having a NAND cell structure, characterized in that. The memory device of claim 1, wherein the voltage control means applies a second voltage to a memory cell (or a plurality of memory cells) positioned between the selected cell and the second node N2 that is the other end of the NAND cell block Bij. Nonvolatile semiconductor memory device having a NAND cell structure, characterized in that. The method of claim 1, wherein the voltage control unit is far from the first node N1 when sequentially selecting the memory cell transistors Mi included in the specific NAND cell block Bij to write data. The memory cell transistors Mi are sequentially selected in the arrangement order starting from the memory cells, and the second voltage is applied to the control gate 42 of the selected memory cell while another memory cell is selected. A nonvolatile semiconductor memory device having a NAND cell structure. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the turn-on voltage is set higher than the first voltage. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage layer is a floating gate (38). 2. The voltage control means according to claim 1, wherein the voltage control means applies a high level voltage to the word lines connected to the control gates 42 of all the memory cell transistors Mi included in the NAND cell block Bij. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the data written to the memory cell transistor Mi is simultaneously erased by applying the same. The method of claim 1, wherein the specific NAND cell block Bij includes a second selection transistor QS2 between a second node N2, which is the other end of the NAND cell block Bij, and a ground potential. Nonvolatile semiconductor memory device having a NAND cell structure. 9. A nonvolatile semiconductor memory device having a NAND cell structure according to claim 8, wherein said specific second select transistor (QS2) is brought into a non-conductive state in a data write mode. 9. The NAND cell structure of claim 8, wherein the second select transistor QS2 is in a non-conductive state in the data erasing mode, thereby allowing the NAND cell block Bij to be electrically separated from the ground potential. Nonvolatile semiconductor memory device having. 9. The channel length of the second select transistor QS2 is smaller than the channel length of the first select transistor QS1 connecting the NAND cell block Bij to a specific bit line. A nonvolatile semiconductor memory device having a NAND cell structure. The method of claim 1, wherein each of the memory cell transistors Mi included in the NAND cell block Bij is formed on the substrate 432 and is doped with a small amount of conductive impurities opposite to that of the substrate 32. And a source and a drain formed of a semiconductor layer, wherein an impurity concentration of the semiconductor layer is lower than an impurity concentration of a source and a drain of a transistor configured in a peripheral circuit. The source and drain diffusion layers of claim 1, wherein each of the memory cell transistors Mi included in the NAND cell block Bij is formed on the substrate 32 and has a conductivity type opposite to that of the substrate 32. (48,50,52,54,56,58) and a gate insulating layer 40 formed between the substrate 32 and the charge storage layer and partially thinned to have a non-uniform thickness. A nonvolatile semiconductor memory device having a NAND cell structure. The voltage control means of claim 1, wherein the voltage control means decreases the voltage applied to the control gate of the other memory cell to select another memory cell adjacent to the selected memory cell after data is written to the selected memory cell in the data write mode. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the potential Vbit of the specific bit line BLi connected to the NAND cell block Bij is temporarily set to a ground potential. 15. The control circuit according to claim 14, wherein the voltage control means is provided to each control gate 42 of each of the memory cell transistors Mi included in the specific NAND cell block Bij when switching from the data erasing mode to the data writing mode. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the applied potential is temporarily lowered to the ground potential. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first voltage is a constant voltage and the second voltage is a ground potential. Selected transistor QS connected to the semiconductor substrate 32, a plurality of parallel bit lines BLi provided on the semiconductor substrate 32, and these bit lines BLi, and connected to the corresponding bit lines BLi. And a memory storage array having a charge storage layer and a control gate 42 positioned between the first node and the second node and connected to the selection transistor QS and the first node N1, respectively. Select transistors QS of the NAND cell block Bij including the selected cell to connect the cell block Bij to a specific bit line coupled thereto in a plurality of NAND cell blocks Bij and a data write mode. Is a conductive state and each of the memory cells (or a plurality of memory cells) located between the selected memory cell and the first node N1 while applying a first voltage to the specific bit line BLi. Apply a HH level voltage to the control gate, and select a phase from the selected memory cell. Voltage control means for storing data in the selected memory cell transistor Mi by applying a voltage of LV level to each control gate of a memory cell (or a plurality of memory cells) located in the second node N2. Nonvolatile semiconductor memory device having a NAND cell structure, characterized in that provided with. 18. The coupling capacitance Cfs between the charge accumulation layer and the substrate 32 in each of the memory cell transistors Mi is the coupling capacitance between the charge accumulation layer and the control gate 42. A nonvolatile semiconductor memory device having a NAND cell structure, characterized in that it is smaller than Cfs). 18. The method of claim 17, wherein the voltage control means starts from a memory cell far from the first node N1 when sequentially selecting the memory cells Mi included in the specific NAND cell block to write data. The memory cell transistor Mi is sequentially selected in an arrangement order in which the memory cell transistor Mi is sequentially selected, and a low level voltage is applied to the control gate while another memory cell is selected. Volatile Semiconductor Memory. 18. The nonvolatile semiconductor memory device according to claim 17, wherein the turn-on voltage is higher than the HH level voltage. 18. The nonvolatile semiconductor memory device according to claim 17, wherein the charge storage layer is a floating gate (38). 18. The device of claim 17, wherein the voltage control means applies a high level voltage to the word line connected to the control gates 42 of all the memory cell transistors Mi included in the NAND cell block Bij in the data erase mode. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the data written to the memory cell transistor Mi is simultaneously erased by applying the same. The method of claim 17, wherein the specific NAND cell block Bij includes a second selection transistor QS2 between the second node N2, which is the other end of the NAND cell block Bij, and a ground potential. A nonvolatile semiconductor memory device having a NAND cell structure. 24. The nonvolatile semiconductor memory device according to claim 23, wherein the second select transistor (QS2) is in a non-conductive state in a data write mode. 24. The NAND cell structure of claim 23, wherein the second select transistor QS2 is in a non-conductive state in the data erasing mode, thereby allowing the NAND cell block Bij to be electrically separated from the ground potential. Nonvolatile semiconductor memory device having. 24. The channel length of the second select transistor QS2 is smaller than the channel length of the first select transistor QS1 connecting the NAND cell block Bij to the specific bit line. Nonvolatile semiconductor memory device having a NAND cell structure, characterized in that. The method of claim 17, wherein the memory cell transistor Mi included in the NAND cell block Bij is formed on the substrate 32 and is doped with a small amount of conductive impurities opposite to that of the substrate 32. A nonvolatile semiconductor memory device having a NAND cell structure comprising a source and a drain formed of a semiconductor layer, wherein an impurity concentration of the semiconductor layer is lower than an impurity concentration of a source and a drain of a transistor included in a peripheral circuit. . The source and drain diffusion layer 48 of claim 17, wherein the memory cell transistor Mi included in the NAND cell block Bij is formed on the substrate 32 and has a conductivity type opposite to that of the substrate 32. NAND, 50, 52, 54, 56, 112, 58, and a gate insulating layer 40 formed between the substrate 32 and the charge storage layer and partially thinned to have a non-uniform thickness. Nonvolatile semiconductor memory device having a cell structure. 18. The method of claim 17, wherein the voltage control means writes data into the selected memory cell in the data write mode and then lowers the voltage applied to the control gate of the other memory cell to select another memory cell adjacent to the selected memory cell. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the potential Vbit of the specific bit line BLi connected to the NAND cell block Bij is temporarily lowered to a ground potential. 30. The control circuit according to claim 29, wherein said voltage control means controls each control gate 42 of each of said memory cell transistors Mi contained in said specific NAND cell block Bij when switching from the data erasing mode to the data writing mode. A nonvolatile semiconductor memory device having a NAND cell structure, wherein the potential is temporarily lowered to the ground potential. 18. The nonvolatile semiconductor memory device according to claim 17, wherein the first voltage is a constant voltage and the second voltage is a ground potential. A plurality of parallel bit lines BLi provided on the semiconductor substrate 32 and the semiconductor substrate 32, and a plurality of parallel word lines WL provided on the semiconductor substrate 32 so as to intersect the bit lines BLi. And a cell array having a series circuit of cell transistors formed corresponding to intersections of the bit line BLi and the word line WL, respectively, and functioning as a memory cell, forming a NAND cell structure. And a control gate layer, a plurality of memory cell transistors (Mi) and a gate insulating layer in which data is written by the tunneling effect of charge between the charge accumulation layer and the substrate 32 side, and corresponding to one end of the cell array. A field effect transistor 46 functioning as a selection transistor QS for selectively connecting the bit line BLi to be connected, and the specific memory cell transistor is far from a node connected to the corresponding bit line BLi. And a voltage control means for performing a data write operation for the memory cell transistor Mi in the cell array by sequentially activating the memory cell transistor Mi in an arrangement order starting from a specific memory cell transistor. Programmable read-only semiconductor memory, characterized in that. 33. The memory cell of claim 32, wherein the voltage control means is connected to gates of the bit line BLi, the word line WL, and the selection transistor QS, and the memory cell of the cell array in the data write mode. If a predetermined cell is selected from Mi, the select transistor QS is set to have a high HH level high enough to bring the selection transistor QS into a conductive state so that the cell array is connected to a specific bit line BLi coupled thereto. Is supplied to the gate of the circuit board, and the HV or LV level voltage is applied to the specific bit line BLi, and the first memory is located farthest from the specific bit line BLi in the memory cell Mi. By applying the low level voltage to the word line connected to the cell and applying the low level voltage to the word line WL connected to the remaining memory cell of the cell array, a data write operation is performed in a specific memory cell. To allow this to be done Programmable read only semiconductor memory device according to claim consisting of the coder circuit means (120). 34. The word line WL of claim 33, wherein the decoder circuit 120 is connected to the particular memory cell to subsequently select another memory cell adjacent to the particular memory cell after data has been written to the particular memory cell. A programmable read only semiconductor memory device, characterized in that a low L level is applied to another word line connected to said other memory cell while being maintained at this low L level voltage. 33. The programmable readout device of claim 32, further comprising a field effect transistor 110 having a gate layer, the field effect transistor 110 functioning as a second select transistor for electrically connecting the other end of the cell array to a ground potential. Semiconductor memory device. 33. The apparatus according to claim 32, wherein said decoder circuit means (120) has a plurality of subcoders each having an output connected to a control gate (42) of a memory cell (Mi) of said cell array and a subsequent subdivision circuit (Di). A plurality of sub-decoder circuits (Di), the plurality of sub-decoder circuits (Di) configured to receive an input address first to designate the selected memory cell, and to control the selected memory cell connected to the selected memory cell. And a sub-decoder circuit for supplying the output voltage of the L level to the gate, and sequentially transmitting the output voltage to another memory cell Mi disposed on the source side of the selected memory cell Mi. Programmable read-only semiconductor memory, characterized in that. 33. The programmable read memory device of claim 32, further comprising memory means (100) for receiving input data of the memory cell to temporarily store the input data. 38. The programmable read only semiconductor memory according to claim 37, wherein said memory means is a static RAM.

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