JPS63268194A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To electrically erase data in the unit of byte by connecting a switching TR between a serial circuit and an erasing line, selectively controlling the turning on/off of said TR to impress an erasing voltage to an erase gate in a specific serial circuit. CONSTITUTION:In the figure of equivalent circuit, the serial circuit 10 consists of eight pieces of memory cells 11 in serial connection. Each cell 11 contains a source area and a drain area, a floating gate provided on a channel area between said two areas, an erasing gate superposed on said electrode, and a control gate. The circuits 10 are arranged in a matrix formation, and one end of the circuit 10 is connected to a bit line and the other end is to a ground line. The control gates of the eight pieces of cells 11 of the circuit 10 are connected to eight pieces of row lines, and these are wired in common for the circuits 10 in the row-direction. The common erasing gate of the circuits 10 arranged in the same row is connected to one of the erasing lines via the switching TR 16, and the control gates of plural pieces of the TRs 16 are connected in common with one erase-selection line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory in which a nonvolatile transistor capable of electrically erasing data is used as a memory cell.

(Prior art) Non-volatile semiconductor memory that allows data to be erased is E F
ROM (Erasable and Program
Among them, those whose data can be erased electrically are particularly known as E''F ROM (E Iectr Memory).
It is called ically erasable PROM). Furthermore, some of these E2 FROMs are capable of erasing data in all cells at once;
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FIG. 9 is an equivalent circuit diagram of a memory cell array portion of a conventional E2PROM using the cells disclosed in the above-mentioned document. In the figure, reference numeral 50 denotes a memory cell consisting of a non-volatile transistor, each equipped with a floating gate electrode (floating gate electrode) and a control gate electrode (control gate electrode), and capable of electrically erasing data. They are arranged in rows and columns. The drains of the memory cells 50 arranged in the same row in the row direction (horizontal direction in the figure) are each commonly connected to one of the plurality of bit lines 51, and are arranged in the same row. The source of each memory cell 50 is connected to a plurality of ground lines 52
Each is commonly connected to one of the two. Further, the control gate electrodes of each memory cell 50 arranged in the same column in the column direction, which is the vertical direction in the figure, are connected to a plurality of row lines 53.
Each is commonly connected to one of the two. In such a memory, by selectively applying a predetermined voltage to the bit line 51 and the row line 53, it is possible to select a 1-bit cell and read or write data, and it is possible to read or write data to all bit lines 51 at the same time. By applying a predetermined voltage, data can be erased for all bits at once.

In this memory, a 1-bit memory cell is composed of one nonvolatile transistor, so that high cell integration can be achieved. However, there is a problem in that data erasing can only be performed for all cells at once or for each bit line, and that data cannot be erased in bytes, which is the processing unit of a parallel write/read memory.

For this reason, an E2 PROM has been announced which is capable of erasing data in units of bytes. Such a memory is described in the document r1987 1EEE, for example.
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However, in this memory, it is necessary to construct a 1-bit memory cell with two or four transistors, making it impossible to achieve high cell integration.

(Problems to be Solved by the Invention) As described above, when attempting to electrically erase data in units of bytes, there is a drawback in that the high integration of cells is impaired. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory in which data can be electrically erased in units of bytes without impairing the high integration of cells.

[Structure of the Invention] (Means for Solving Problems) The nonvolatile semiconductor memory of the present invention includes two or more memory cells each consisting of a nonvolatile transistor having an erase gate electrode and electrically erasing data. A series circuit connected in series with each erase gate electrode connected in common, an erase line to which an erase voltage is applied during erasing, and an erase line connected between the common erase gate electrode of the series circuit and the erase line when erasing data. It is composed of a switching transistor whose conduction is selectively controlled.

(Function) In the nonvolatile semiconductor memory of the present invention, the switching transistor connected between the series circuit and the erase line is selectively turned on, so that the memory cells in a specific series circuit are An erase voltage is applied only to the erase gate electrode, thereby erasing data in units of bytes.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of a memory cell array portion when the present invention is implemented in a 22 FROMM (hereinafter simply referred to as a memory). In the figure, reference numeral 10 denotes a series circuit in which eight memory cells 11 are connected in series. Each memory cell 11 in each of these series circuits 10 has a source region, a drain region, a floating gate electrode provided on a channel region between the source and drain regions, and an erase gate provided to overlap the floating gate electrode. It consists of an electrode and a control gate electrode, and is composed of a nonvolatile transistor that can electrically erase data. A plurality of these series circuits 10 are arranged in a matrix, and one end of each series circuit 10 is connected to a plurality of bit lines 121 . . . 12N, and the other end is connected to one of a plurality of grounding wires 13ri, . . . 13M to which a voltage of O■ is applied, respectively. Further, the control gate electrodes of each of the eight memory cells 11 in the series circuit 10 are connected to each of the eight row lines 1411.
, 1421 , ... 1481-14, M, 14
It is connected to each of 2M,...148M,
Each of these eight row lines ilb, 142,...14
8 is wired in common to a plurality of series circuits 10 arranged in the row direction, which is the horizontal direction in the figure. Furthermore, the erase gate electrodes of the eight memory cells 11 in each series circuit 10 are connected in common, and the common erase gate electrodes of the series circuits 10 arranged in the same column are provided for each column. Erasure line 151. ...15. is connected to any one of the transistors 1G for switching.

Furthermore, the control gate electrode of the transistor 16 connected to the common erase gate electrode of the series circuits 10 arranged in the same row is connected to the erase selection line 17! provided for each row.
, . . . 17M in common.

The element structure when a memory having such a circuit configuration is actually realized on a semiconductor chip is shown in the pattern plan view of FIG. Furthermore, the cross-sectional structure taken along the line II-I' in FIG. 2 is shown in the cross-sectional view in FIG. 3, and the cross-sectional structure taken along the line II-I' in FIG. 2 is shown in the cross-sectional view in FIG. The cross-sectional structure along line mm' in FIG. 2 is shown in the cross-sectional view of FIG. 5, respectively. In this memory, a P-type silicon semiconductor substrate, for example, is used as the substrate 20. In the surface region of the substrate 20, N+ type regions 21 which become the source and drain regions of the eight memory cells 11 constituting each of the series circuits 10 are formed separately. In FIG. 2, the N-type regions Fa21A and 2113 located at the top and center, respectively, are shared by adjacent series circuits, and one N4"-type region 21A located at the top. is the ground wire 13
used as. Furthermore, metal interconnections 23 made of aluminum, for example, are connected to the N1 type regions 21B through contact holes 22, respectively. The metal wirings 23 are used as the bit lines 12, respectively. Further, between each N+ pear-shaped region 1, an electrode 24 is formed with an electrically floating state and made of a first layer of polycrystalline silicon layer with an insulating film interposed therebetween. These electrodes 24 constitute the 70-digit gate electrode of each memory cell 11. Further, in FIG. 2, an electrode 25 made of a third layer of polycrystalline silicon is formed over a plurality of electrodes 24 arranged laterally with an insulating film interposed therebetween. These electrodes 25 constitute the control gate electrode of each memory cell 11 and the row line 14. Electrodes 26 made of a second layer of polycrystalline silicon are formed between the series circuits arranged roughly in each column with an insulating film interposed therebetween. It overlaps with a part of each electrode 24 made of a polycrystalline silicon layer. This bridge 26 constitutes a common erase gate electrode for each memory cell 11 in the series circuit.

N+ type regions 21G are formed between the N+ pear-shaped regions 1B, and a pair of N+ type regions 21D are formed in the vertical direction in the figure so as to be spaced apart from each other. The N+ type regions 1C and 21D are the sources of the switching transistor 16.

A drain region is formed, and an electrode 27 made of a third polycrystalline silicon layer is formed between the drain regions with an insulating film interposed therebetween. This electrode 21 constitutes the control gate electrode of this transistor 16 and the erase selection line 17. The electrode 26, which serves as the common erase gate electrode, is connected to the N+ type region 1D through a direct contact portion, and the N+ type region 1C is connected to the N+ type region 1C through a contact hole 28, for example, using aluminum. A metal wiring 29 made up of is connected.

This fully bent wiring 29 is used as the erase line 15.

That is, in this memory, each series circuit 10 is composed of eight memory cells 11 connected in series, and one end of each series circuit 10 is connected to a bit 1i112 made of a metal wire 923.
and the other end is connected to a grounding line 13 consisting of an N+ type region 21A.
The control gate electrode of each memory cell 11 is connected to the row line 14 constituted by the electrode 25, and the common erase gate electrode of each memory cell 11 is connected to the transistor 16 whose conduction is controlled by the signal of the erase selection line 17. The erase line 15 is connected to the erase line 15 via the erase line 15.

Next, the operation of the memory having the above configuration will be explained.

First, the operation during data writing will be explained using the timing chart of FIG. At this time, of the eight rows 1114 connected to the series circuit 10 including cells to be selected, a voltage of 10V is applied only to the row line to which the control gate electrode of the selected cell is connected, and the remaining 7 A voltage of 20V is applied to the row line of the book. Note that all other row lines are set to OV. Here, for example, the series circuit 10 including cells to be selected is connected to a bit line 121 and eight row lines 1411 to 1.
4B1 and the cell to be selected is connected to the row line 1421, then 10V is applied to only the row line 1421 of the eight row lines 1411 to 1481.
A voltage of 20V is applied to the remaining seven batting lines. Furthermore, during this data write, two different voltages are applied to the corresponding bit line 121 based on the write data at that time. For example, when writing data of "1", a voltage of 10 cm is applied to the bit line 121, while when writing data of '0', a voltage of 0 cm is applied to the bit line 121. are all made OV.

Here, seven row lines 14. except row line 1421. , .

Each of the seven memory cells 11 whose control gate electrodes are supplied with a voltage of 20V applied to 1431 to 1481 operates as a triode, so a bit line 121 and a ground line 131 are connected to the source and drain regions of the selected cell, respectively. voltage is applied almost as is.

At this time, bit @ 12. If a voltage of 10 V is applied to the selected cell, electrons travel from the source region to the drain region of the selected cell. Then, the electric field is concentrated particularly in the depletion layer generated near the drain region, thereby accelerating electrons and imparting enough energy to overcome the energy barrier of the insulating film from the surface of the substrate 20 in FIG. 3. Such electrons are called hot electrons, and these electrons are attracted to the control gate electrode of the selected cell, which is set at a high voltage of 10V, jump into the floating gate electrode, and are captured there.

As a result, the floating gate voltage of the selected cell becomes negatively charged, and the threshold voltage increases. On the other hand, bit $
If a voltage of OV is applied to 3121, the electrons do not travel as described above, and the threshold voltage remains in its original low state. In this way, data is written for each cell.

Next, the operation during data reading will be explained using the timing chart of FIG. At this time, among the eight row lines 14 connected to the series circuit 10 including the cell to be selected,
A voltage in the range of 2V to 5V is applied only to the row line to which the control gate electrode of the selected cell is connected, and a voltage in the range of 5V to 10V is applied to the remaining seven row lines. At this time, all other batting lines are set to Ov. For example,
The series circuit 10 including the cell to be selected receives bits @12. as in the case of data writing. and eight row lines 1411-1
481, and the cell to be selected is connected to the row line 1421, then 2V to 2V is applied only to the row line 1421 among the eight row lines 1411 to 1481.
A voltage in the range of 5V is applied, and the remaining 7 row lines have a voltage of 5V.
A voltage in the range ˜10V is applied. Here, each memory cell 11 has a threshold voltage set in advance according to the write state at the time of writing data, and the voltage in the range of 2V to 5V is, for example, lower than the lower threshold voltage of the cell in the erased state. For example, the voltage in the range of 5V to 10V is a voltage that is sufficiently higher than the high threshold voltage after “11Pl” is written. Therefore, such a voltage is 8
By applying the voltage to the book rows 1411 to 1481,
Seven row lines 141 t, 14i except row line 1421
The seven memory cells 11 whose control gate electrodes are connected to s~1461 are fully turned on. On the other hand, the selected cell whose control gate electrode is connected to row 1!1421 is turned on or off depending on its threshold voltage.

When reading this data, a read voltage of 1 is applied only to the corresponding bit line 121. Here, the threshold voltage of the selected cell is set low, and if it is turned on by the voltage of the row line 1421, the read voltage of 1V applied to the bit line 121 will be applied to this series circuit including the selected cell.
0 to the ground wire 131 of Ov. On the other hand, the threshold voltage of the selected cell is increased, and the row line 14
If the bit line 121 remains off even after the voltage of 21 is applied, the read voltage of 1v applied to the bit line 121 is maintained as it is. In this way, the voltage of the bit line 12 varies depending on the level of the threshold voltage m of the selected cell, and the potential difference is expressed as the bit l! By amplifying with a sense amplifier circuit (not shown) connected to 12, logical "1°', "0
At the time of data reading, the voltage applied to the row line to which the unselected cell is connected is approximately 7V.
Also, the voltage applied to the batting line connected to the selected cell is 2v.
From the viewpoint of characteristics and reliability, it is desirable to set it at a certain level.

Next, the operation during byte erasing will be explained. That is, as shown in the timing chart of FIG. 8, byte erasing of data is performed by erasing selection when all row lines 14 and bit lines 12 are set to OV and are connected to the series circuit 10 where byte erasing is to be performed. I! A high voltage of 30V is applied to the line 17, and a high voltage of 25V is applied to the erase line 15. In the example of FIG. 8, the serial circuit 10 to perform byte erasing is connected to the bit 121 and eight row lines 14.1 to 14.1. As a result, the transistors 16 connected to the plurality of series circuits 10 arranged in the same row including the series circuit to be erased by byte are turned on, and the transistors 16 are connected to the erase line 15 to which a high voltage of 25V is applied. The high voltage of the erase line 15 is applied to the common erase gate voltage of the series circuit 10 only. Series circuit 1 selected by this
A field emission called field emission occurs between the floating gate electrode and the erase gate electrode of each of the eight cells 11 in 0, and the 2 electrons accumulated in the floating gate electrode are emitted to the erase gate electrode. . As a result, the threshold voltage of each cell returns to the same low state as the initial state, and data erasure for 8 bits, ie, byte erasure, is performed.

In this way, the memory of the above embodiment can read and write data bit by bit and electrically erase data in byte units. Moreover, in constructing a memory cell array, each memory cell of 1al can be constructed with one nonvolatile transistor. Therefore, in the memory of this embodiment, the memory cells can be highly integrated. By the way, in conventional memories that can electrically erase data in bytes, one bit is made up of two or four transistors, so it is not possible to increase the integration density of cells, and the number of cells is 256 at most. It is only possible to realize a memory capacity on the order of bits. On the other hand, in the case of the above embodiment, since one bit is constituted by one transistor, it is possible to realize a memory with a degree of integration comparable to or higher than that of the batch erasing type shown in FIG. 9 above. can do. That is, in the above embodiment, it is necessary to provide one switching transistor 16 for eight memory cells 11, so 1.125 transistors are required per 1 bit, compared to the one shown in FIG. te1
An additional 0.125 transistors are required per bit. However, in the one-time erase type shown in FIG. 9, it is necessary to form a contact for each bit in order to connect each cell to the corresponding bit line. However, in the memory of the above embodiment, it is only necessary to form one contact for every eight cells, and the degree of integration is improved accordingly.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, a case has been described in which data erasure is performed in byte units;
By simultaneously applying a voltage of 5 V to each cell, it is also possible to erase data from all cells at once, as in the case of conventional memories.

Furthermore, although we have explained the case where a read voltage of 1V is applied to the bit line 12 when reading data, this read voltage is set as low as possible in order to suppress the so-called soft write phenomenon (weak write in the read mode). It is preferable to do so.

Furthermore, in the above embodiment, when data is adjusted, a voltage of 10 V is applied to only the row line to which the selected cell is connected among the eight row lines 14, and a voltage of 20 V is applied to the remaining seven row lines. Although the case has been described, it is sufficient that the voltage is high enough to inject a sufficient amount of electrons into the floating gate electrode of the selected cell and to cause the non-selected cell to operate as a triode.

In the above embodiment, the electrode 25 in FIG. 2 used as the control electrode and row line 14 of each cell is made of polycrystalline silicon. - It may be composed only of silicide, molybdenum silicide, etc., or a high melting point metal.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory that can electrically erase data in byte units without impairing the integration of cells.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell array portion of a memory according to an embodiment of the present invention, FIG. 2 is a pattern plan view showing an element structure when the circuit shown in FIG. 1 is implemented on a semiconductor chip, and FIG. , FIGS. 4 and 5 are respectively cross-sectional views of a part of the device shown in FIG. 2, FIGS. 6 to 8 are timing charts of the memory of the above embodiment, and FIG. 9 is a memory cell array of a conventional memory It is an equivalent circuit diagram of a part. 10...Series circuit, 11...Memory cell, 12...
・Bit line, 13... Ground line, 14... Row line, 15
... Erasing line, 16... Transistor for switch,
17... Erase selection line, 20... Substrate, 21, 21A
, 21B, 2IC, 210・N+ type [, 22° 28
...Contact hole, 23.29...Fully bent wiring,
24°25, 26.27... Electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 6 All fT Kura □0■

Claims (1)

[Scope of Claims] A series circuit in which two or more memory cells each consisting of a non-volatile transistor having an erase gate electrode and electrically erasing data are connected in series, and each erase gate electrode is commonly connected; An erase line to which an erase voltage is sometimes applied, and a switch transistor connected between the common erase gate electrode of the series circuit and the erase line and whose conduction is selectively controlled when data is erased. Non-volatile semiconductor memory.