JPS6254962A - Transistor - Google Patents

Abstract

PURPOSE:To form a longitudinally stacked ROM structure by setting the threshold voltage of a channel region higher than one after writing at the low level of the channel having memory function, coated with a floating gate electrode and lower than one after writing at the high level. CONSTITUTION:Since a transistor which has written is charged sufficiently negatively at a floating gate electrode 6 when a control gate electrode 12 is set to 0V, a channel region 5 becomes nonconductive. A channel region 10 is nonconductive, and the entire transistor becomes of a nonconductivity state. When the electrode 12 is set to 5V, if the electrode 6 is charged sufficiently negatively, the region 5 becomes nonconductive, but the region 10 becomes of a conducting state. Since the channel region having memory function and the channel region having approx. 1V of threshold voltage without memory function are presented in parallel, the entire transistor does not become 1V or higher of threshold voltage irrespective of the electron amount implanted to the electrode 6. Thus, a longitudinally stacking ROM structure can be electrically rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor, and particularly to a transistor used in an electrically rewritable nonvolatile semiconductor memory.

[Conventional technology]

Conventionally, this type of transistor has one
A floating gate electrode 41t is provided across the channel region between the source region 42 and the drain region 43, and the floating gate electrode 41t is provided on the floating gate electrode 41 via an insulating film.
A control gate electrode 44 which is capacitively coupled to 1 is provided.

Information is written to this transistor by injecting charges into the floating gate electrode 41 by hot carrier injection or tunnel injection, and changing the channel conductivity between the source region 42 and drain region 43. It will be done. For example, in the case of an N-channel transistor, writing is performed by injecting electrons into the floating gate electrode 41 to charge it negatively, thereby increasing the threshold voltage, and by injecting holes to charge it positively. Erasing is performed by lowering the threshold voltage. By applying a voltage intermediate between the threshold voltage after writing and the threshold voltage after erasing to the control gate electrode 44, low level data (hereinafter referred to as data ``0#'') is generated when the channel is in a conductive state. ), the stored information can be read out as high level data (hereinafter referred to as data ""1") if it is in a non-conductive state.

When such conventional transistors are integrated and used as a memory device, the select transistor Q1 and the memory transistor Ml are connected in series, as shown in FIG. 1 memory cell is configured. The reason for this is that when multiple memory transistors Mat are connected alone on the same bit line, if there is another memory transistor whose channel is conductive when reading the information of the selected nine transistors M, the focus line This is because, from this point of view, there is always a conduction path, and it becomes impossible to determine whether the selected memory transistor is conductive or nonconductive.

As described above, in the conventional electrically rewritable floating gate type nonvolatile memory, it is necessary to configure each %1 memory cell with two transistors, which has been an obstacle to miniaturization of the device.

On the other hand, in a mask ROM (a ROM in which stored information is fixed during the manufacturing process and cannot be rewritten), one select transistor Ql and multiple memory transistors Ml~ M, are connected in series, and 1 is applied to the entire transistor Ql and transistors Ml to M1.
A method of configuring a cell array (hereinafter referred to as a vertically stacked ROM) has been put into practical use, which improves the overall degree of integration by allocating a drain D and one source S to be connected to two bit lines B.

Next, a reading method for a vertically stacked ROM will be explained using FIG. For ease of understanding, all elements are of N-channel type.

Transistors Ml-M, those corresponding to data "1" K are formed in an enforcement state with a threshold voltage of about 1 V, and those corresponding to data "'0# are formed in a depletion state. Transistors Ml To read the data of ), keep the bit line Bi at a high potential, and
The gate electrode GSi of the selected transistor M0 is kept at a high potential and conductive, and the gate electrodes GM2 to GMI of the transistors M2 to Ml are connected to the gate electrode GM1f:Ov of the selected transistor M0.
Keep it at v. At this time, the channels of transistors M2 to M are all conductive regardless of data "'1" or data "'0". On the other hand, the selected transistor M1 is in a depletion state and conductive if the data is @0'', and is non-conductive if the data is 11''. In this way, the conduction or non-conduction of the transistors M1 to M can be determined by the conduction or non-conduction of the selected transistor M1, so that information on the transistor M1 can be read.

If the method for configuring the vertically stacked ROM described above can be applied to an electrically rewritable nonvolatile memory device, it will be possible to realize a nonvolatile memory device that is smaller than the conventional device. However, it is difficult to realize this method due to the following drawbacks.

Assume that a conventional transistor is placed in place of the memory transistor of the mask ROM shown in FIG. In addition,
Any method may be used to inject charges into the floating gate electrode of the transistor. As mentioned above, the transistor corresponding to the data "'0" must be in a depletion state, which can be easily achieved by injecting holes into the floating gate electrode. On the other hand, the transistor corresponding to data 11# must be in an enhancement state in which the threshold voltage is lower than the high voltage applied to the gate electrode during reading. (In the previous example of masks R and OM, the high voltage during reading was 5V, and the threshold voltage in the enhancement state was approximately 1V.Q) This means that during reading, the transistors for unselected memories are This is to make it conductive regardless of whether it is "or 0".

However, in a normal memory transistor, it is very difficult to adjust the threshold voltage to a desired value after writing, that is, after electron injection. Generally, the amount of electrons injected varies greatly depending on write conditions (V voltage, write time, etc.). Furthermore, from the viewpoint of non-volatility, it is desirable to inject sufficient electrons in order to improve the reliability of written data. Therefore, it is not only difficult but also undesirable to fully control the amount of electrons injected into the floating gate electrode in order to align the threshold voltage of the transistor corresponding to data '1' to the desired value. .

[Problem that the invention seeks to solve]

The above-described conventional transistor has the disadvantage that it is difficult to align the threshold voltage after electron injection to a desired value, and that a nine-vertical ROM structure suitable for high integration cannot be realized.

An object of the present invention is to provide a transistor suitable for realizing a vertically stacked ROM structure.

[Means for solving problems]

The present invention provides a -conductivity type semiconductor substrate, a source region and a drain region having conduction/it type with the semiconductor substrate provided on the semiconductor substrate, and a channel region between the source region and the drain region. a floating gate electrode extending from the source region to the drain region and covering a part of the gate insulating film; and a floating gate electrode provided on and over the floating gate electrode. In a transistor having a control gate electrode provided through an insulating film over the channel region, which is not covered by the floating gate electrode, the threshold voltage of the channel region, which is not covered by the floating gate electrode and does not have a memory function, is The floating gate electrode is provided so as to be set higher than the threshold voltage after low level writing and lower than the threshold voltage after high level writing of the channel region having the memory function metal covered with the gate electrode. It consists of

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A'il of the transistor shown in FIG. In this embodiment, the present invention is applied to a transistor for an N-channel memory having a three-layer polycrystalline silicon structure.

As shown in FIGS. 1 and 2, a source region 2 and a drain region 3, which are N-type regions, are formed on a P-type wheel crystal silicon substrate 1, a first gate oxide film 4, and a region from the source region 2 to the drain region. A floating gate electrode 6 made of a second layer of polycrystalline silicon is formed so as to cover part 5 of the channel region.

Furthermore, the floating gate electrode 6 extends on the thick field oxide film 7 and onto the write electrode 8 made of the first layer of polycrystalline silicon, and the write electrode 8 and the floating gate electrode 6 are insulated by a thin tunnel oxide film 9. ing.

Further, on the floating gate electrode 6 and the channel region lo not covered by the floating gate electrode 6, a control gate electrode 12 made of a third layer of polycrystalline silicon is provided with a second gate oxide film 11'fc interposed therebetween. It will be done.

By implanting P-type boron ions into the channel region, the injected voltage in the region 10 not covered by the floating gate electrode 6 is set to about 1V. Further, all boron ions are implanted into the channel region 5 under the floating gate electrode 6 at the same time, but the channel region 5 can have an arbitrary threshold voltage depending on the charging state of the floating gate electrode 6.

To write or inject electrons into this transistor, write electrode 8 is kept at a low potential and a high positive voltage is applied to control gate electrode 12. The floating gate electrode 6 capacitively coupled to the control gate electrode 12 has a positive high potential, and the write electrode 8
Electrons pass from the tunnel oxide film 9 to the floating gate electrode 6
is injected into.

To perform erasing, that is, hole injection, the control gate electrode 12 is kept at a low potential and a high positive voltage is applied to the write electrode 8. This electric field causes the floating gate electrode 6 to
Electrons are injected into the floating gate electrode 6, and holes are effectively injected into the floating gate electrode 6. After performing the write or erase operation as described above, the memory transistor of this embodiment has the following read characteristics.

In the erased transistor, when the control gate electrode 12 is set to Ov, since the floating gate electrode 6 is sufficiently positively charged, the channel region 5 under the floating gate electrode 6 becomes conductive. On the other hand, the channel region 10 under the control gate electrode 12 is in an enhancement state of 1 in terms of threshold voltage and is therefore non-conductive. As for the transistor as a whole, two transistors in a depletion state and an enhancement state are connected in parallel and are equivalent to each other, and the source and drain are brought into conduction state by the control gate voltage Ov.

The friend transistor to which writing is performed is connected to the control gate electrode 12.
When set to kOV, since the floating gate electrode 6 is sufficiently negatively charged, the channel region 5 under the floating gate electrode 6 becomes non-conductive. Furthermore, the channel region 10 under the control gate electrode 12 is also non-conductive, and the transistor as a whole is in a non-conductive state. On the other hand, the control gate electrode 121-5
When set to V, if the floating gate electrode 6 is sufficiently negatively charged, the channel region 5 under the floating gate electrode 6 becomes non-conductive, but the channel region 10 under the control gate electrode 12 becomes conductive. state. Since a channel region with a memory function and a channel region with a threshold voltage of 12 without a memory function exist in parallel, the threshold voltage of the transistor as a whole remains constant regardless of the amount of electrons injected into the floating gate electrode 6. It will never go above IV. That is,
The threshold voltage after writing can be controlled not by the amount of electrons injected into the floating gate electrode 6, but by controlling the threshold voltage of the channel region 10, which does not have a memory function, under the control gate electrode 12.

Figure 3 shows a vertically stacked RO using the transistors shown in Figure 1.
FIG. 2 is a plan view of a cell array having an M structure.

As shown in FIG. 3, one select transistor QIK and three memory transistors M1 to M3 are connected in series.

In FIG. 3, the write electrode is kept at 8ftO■ and the control gate electrodes GM1 to GM3 of transistors Ml-M3 are applied with 20V.
When e is applied, electrons are injected into the floating gate electrode through the entire tunnel oxide film 9, as described above. As a result of this operation, the threshold voltage of the channel region 5 under the floating gate electrode 6 of the transistors M1-M3 becomes 5.times. or higher, and the stored data becomes data "1".

Next, for example, data "'" is selectively applied to the transistor Ml.
To write (that is, erase) 0″″, Ov is applied to the control gate electrode GMl of the transistor Ml, and the other non-selected transistors M2 . M30 control gate electrode GM2. GM
Apply an intermediate potential of IOV to the write electrode 8, and apply the intermediate potential of IOV to the write electrode 8.
Apply 0Vi. A large electric field is generated in the tunnel oxide film 9 of the selected transistor M1 by the write voltage, and electrons in the floating gate electrode 6 are emitted to the write electrode 8 due to the tunneling phenomenon. As a result, the floating gate electrode 6 is positively charged, and the depletion state data "'0" is written. During this operation, the other unselected transistors M2. In M3, the control gate electrode GM2°GMa
Since the intermediate potential of KiOV is applied, an electric field necessary for electron emission to occur in the tunnel oxide film 9 is not applied, and no charge movement occurs.

Therefore, the data "o" in any memory transistor
1 can be written.

Next, regarding reading, it is possible to perform exactly the same operation as a conventional vertically stacked ROM. During reading, the write electrode 8 is kept at 0■. To read the data of the transistor Ml, the bit line B″f: is kept at a high potential, the control gate electrode GS of the transistor Ql is kept at a high potential and made conductive, and the transistor M1
The control gate electrode GMl of the other transistor M2 is set to 0■
．． M3 control gate electrode GM2. Keep GM3 at 5■.

At this time, transistor M2. If the data is "0#", M3 is in a depletion state and is therefore conductive. Even if the data is "'1", the channel region 1O having no memory function is conductive and is always in a conductive state.

On the other hand, the selected transistor M has data ""O"
If so, it is in a depletion state, so it is conductive and the data is
'1# is an enhancement state where the threshold voltage is 1V, so it becomes non-conductive. In this way, it is possible to determine whether only the selected transistor M1 is conductive or completely non-conductive.

Although the present invention has been described above based on the examples, the present invention is not limited to the above-mentioned examples.

In particular, regarding the writing method, in this example, a tunnel phenomenon through a tunnel oxide film on polycrystalline silicon as a write electrode was used, but writing using the entire tunnel oxide film on a silicon substrate, avalanche or channel injection may also be used. Naturally, hot carrier injection writing such as the above can also be used.

〔Effect of the invention〕

As explained above, the transistor of the present invention has a source
By providing a channel region with a full memory function and a channel region without a memory function in parallel between the drains, the threshold voltage in the enhancement state of the memory transistor can be controlled by the amount of electrons injected into the floating gate electrode. First, since it can be determined by the threshold voltage of a channel region that does not have a memory function, it is possible to easily configure an electrically rewritable nonvolatile memory cell array with a vertically stacked ROM structure, which has the effect of enabling high integration. .

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' of the transistor shown in FIG. 1, and FIG. 3 is a vertically stacked ROM structure using the transistors shown in FIG. 4 is a plan view of an example of a conventional transistor, FIG. 5 is a circuit diagram of a memory cell using the transistor shown in FIG. 4, and FIG. 6 is a mask of a vertically stacked ROM structure. It is a circuit diagram of ROM. 1... P-type nest crystal silicon substrate, 2...
・Source head, 3...Drain region, 4...
...First gate oxide film, 5...Channel region, 6...Floating gate electrode, 7...Field oxide film, 8...Write Including electrode, 9...
...Tunnel oxide film, 10...Channel region,
11... Second gate oxide film, 12...
・Control gate electrode. Agent Patent Attorney Shinka Uchihara l Figure 3 Senka 4 Concave 5 Figure 1 I! I

Claims (1)

[Claims] A semiconductor substrate of one conductivity type, a source region and a drain region having a conductivity type opposite to that of the semiconductor substrate provided on the semiconductor substrate, and a gate insulating film provided on a channel region between the source region and the drain region. a floating gate electrode extending from the source region to the drain region and covering a part of the gate insulating film; and the channel region not covered by the floating gate electrode and above the floating gate electrode. In a transistor having a control gate electrode provided thereon through an insulating film, a threshold voltage of the channel region not covered by the floating gate electrode and having no memory function is covered by the floating gate electrode. A transistor characterized in that the floating gate electrode is provided so as to be set higher than a threshold voltage after low level writing and lower than a threshold voltage after high level writing of the channel region having a memory function. .