JP3104978B2 - Control method for nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention has a floating gate and a control gate, and performs electrical writing and erasing by using hot electron injection and emission by tunnel current. The present invention relates to a method for controlling a nonvolatile semiconductor memory device (EEPROM) using enabled memory cells.

(Prior Art) In the field of EEPROM, a batch erase (flash type) EEPROM using a memory cell having a MOSFET structure having a floating gate is widely known. The memory cell array is configured by arranging memory cells at intersections of row lines and column lines that intersect each other. Writing is performed by applying a positive potential to the control gate and drain of the selected memory cell to turn it on, generating a channel current to generate hot electrons near the drain, and injecting them into the floating gate. Will be As a result, the threshold value of the memory cell moves in the positive direction and becomes "1". Batch erase is performed by keeping the control gates of all memory cells at 0 V, applying a high potential to the common source, and discharging electrons in the floating gate to the source diffusion layer by tunnel current. This allows
The memory cell enters the “0” state in which the threshold value has moved in the negative direction.

In the EEPROM using such hot electron injection / tunnel emission, a high potential is applied to the source diffusion layer at the time of erasing, so that a current due to inter-band tunneling flows on the substrate surface in a region where the floating gate and the source diffusion layer overlap. This is the cause of the drain leakage current in fine MOSFETs that has recently attracted attention, namely, the gate leakage current.
This is the same as the surface breakdown that occurs on the surface of the drain diffusion layer overlapping the gate electrode when a high voltage is applied between the drains. An electron current and a hole current are generated by this tunneling phenomenon. Among them, the holes enter the p-type well, are accelerated and become hot, and a part thereof is injected into the tunnel insulating film and trapped. This means that the barrier height of the tunnel insulating film becomes lower when viewed from the electrons, and thus causes the data retention characteristics of the memory cell to deteriorate.

(Problems to be Solved by the Invention) As described above, in the conventional EEPROM using hot electron injection / tunnel emission, there is a problem that unnecessary hole injection occurs in the floating gate at the time of erasing, which deteriorates data retention characteristics. Was.

The present invention utilizes hot electron injection / tunnel emission in which such deterioration of data retention characteristics is prevented.
An object of the present invention is to provide a method for controlling an EEPROM.

[Structure of the Invention] (Means for Solving the Problems) A method for controlling a nonvolatile semiconductor memory device according to the present invention comprises:
A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged and formed in a second conductivity type well formed on a semiconductor substrate of a first conductivity type, wherein the memory cells are formed in the second conductivity type well. Source and drain diffusion layers of the first conductivity type, a floating gate formed in a region between the source and drain diffusion layers via a tunnel insulating film, and a floating gate formed on the floating gate through an interlayer insulating film. A write mode in which the source diffusion layer is connected to a common source line, a selected memory cell is turned on, hot carriers are generated near the drain diffusion layer, and the hot carriers are injected into the floating gate. And setting the control gates of a plurality of memory cells in a predetermined range to 0 V, applying a high potential to the second conductivity type well, and floating the memory cells in the range. The chromatography bets carrier is released by the tunnel current to the second conductivity-type well, and a erasing mode for a voltage lower than the threshold voltage at the time of writing at least 0V and the threshold voltage of the memory cell.

Furthermore, a method of controlling a nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device in which a plurality of memory cells are arrayed and formed on a semiconductor substrate, wherein the memory cells include a source and drain diffusion layer, A memory having a charge storage layer formed in a channel region sandwiched by a drain diffusion layer through a tunnel insulating film, and a control gate formed on the charge storage layer through an interlayer insulating film; A first mode in which the cells are turned on to generate hot carriers and the hot carriers are injected into the charge storage layer; and a high potential is applied between the control gate and the channel region for a plurality of memory cells in a predetermined range. And a second mode in which carriers in the charge storage layer of the memory cell in the range are emitted to the channel region by a tunnel current.

(Operation) According to the present invention, at the time of erasing in the second mode, carriers of the floating gate are emitted by tunneling between the floating gate as the charge storage layer and the channel region of the well. Therefore, unlike the case where the tunneling between the floating gate and the source diffusion layer is used as in the related art, the band-to-band tunneling phenomenon does not occur in the substrate.
Unnecessary carriers are not injected into the floating gate.
Therefore, a highly reliable flash EEPROM can be obtained.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a portion of two memory cells M1 and M2 having a common drain of a flash EEPROM of one embodiment. 2 (a) and 2 (b) respectively show A-
It is A ', BB' sectional drawing. In the memory cell array region of the n-type silicon substrate 1, a p-type well 2 is formed separately from peripheral circuits, and a memory cell is formed in a region of the p-type well 2 surrounded by the element isolation insulating film 3. That is, in the memory cells M1 and M2, the floating gates 5 (51, 52) serving as charge storage layers of the first polycrystalline silicon film are formed on the p-type well 2 (on the channel region) via the tunnel oxide film 4. On top of this, a control gate 7 (71, 72) of a second-layer polycrystalline silicon film is laminated and formed via an interlayer insulating film 6. For example, the tunnel oxide film 4 has a thickness of 50 to 200 mm.
The interlayer insulating film 6 is a thermal oxide film of 140 to 400 °. The floating gate 5 is formed separately for each memory cell. The control gate 7 becomes a control gate line CG (CG1, CG2) common to a plurality of memory cells continuously in the horizontal direction of FIG. An n-type diffusion layer 8 (81, 82, 8) which is self-aligned with the control gate 7 and the floating gate 5 and serves as a source and a drain.
3, ...) are formed. The substrate on which the memory cells have been formed is covered with a CVD oxide film 9, a contact hole is formed in the substrate, and a bit line 10 is provided. In the figure,
The portion where the bit line 10 is connected to the n-type diffusion layer 83 which is a common drain of two memory cells is shown.
The source n-type diffusion layers 81 and 82 are formed as source lines SS (SS1, SS2,...) Common to memory cells (not shown) adjacent in the bit line direction and the control gate line direction, respectively.

FIG. 3 is an equivalent circuit of the above two memory cells M1 and M2. Next, the operation of the EEPROM of this embodiment will be described with reference to this equivalent circuit.

First, when writing data to the memory cell M1, a positive “H” level potential (for example, 12.5
V), a positive “H” level potential (for example, 8.5 V) is applied to the selected bit line BL, and the remaining terminals, that is, the common source line
The SS, p-type well P _WELL (including the channel region), the unselected control gate line CG2, and the unselected bit line are all set to 0V. As a result, a channel current flows in the selected memory cell M1, and hot electrons generated near the drain are injected into the floating gate via the tunnel insulating film. As a result, the threshold value moves in the positive direction and becomes, for example, 3 to 9 V, and "1" is written. Unselected memory cell M2
In this case, no channel current flows and writing is not performed.

Next, batch erasing of data involves removing all control gate lines CG.
The voltage is set to 0 V, and a positively raised positive "H" level potential (for example, 18 V) is applied to the substrate, the p-type well P _WELL including the channel region, and the bit line BL. Thereby, in all the memory cells, the floating gate is connected to the p-type well (channel region).
Electrons are emitted by the tunnel effect. As a result, the threshold value moves in the negative direction, for example, the threshold value becomes "0" state of 0 to 3V.

The data reading of the memory cell M1 is performed on the substrate and p-type well P
_{The WELL} and the common source line SS are set to 0 V, for example, 2.5 V is applied to the selected control gate line CG1, and the selected bit line BL
For example, 1 to 5V. Unselected control gate line CG2 is 0
V. At this time, “0” or “1” is determined depending on whether or not a current flows through the bit line BL.

FIG. 4 collectively shows the potential relationship in each of the above operation modes. FIG. 4 shows the potential relationship in the conventional batch erasing method for comparison.

In this embodiment, at the time of batch erasing, “H” is applied to the p-type well (including the channel region) surrounding the substrate and the memory cell array.
A level potential is applied. The current flowing at this time is a tunnel current between the floating gate of each memory cell and the p-type well (channel region) and a leak current between the p-type well surrounding the peripheral circuit and the substrate, and is at most 10 μA. It is as follows. Therefore, the "H" level potential used for erasing can be obtained by boosting the power supply potential from 5 V applied from the outside of the chip by an internal booster circuit.

In this embodiment, no surface breakdown occurs at the surface of the source or drain diffusion layer at the time of writing as well as at the time of batch erasing.
The data retention characteristics of the PROM are improved.

In the present invention, the batch erasing can be performed for all the memory cells of the memory cell array, but the block erasing is also possible. In other words, the control gate is set to 0 V in the range of the memory cell array to be erased, and the same "H" level potential as that of the p-type well (including the channel region) is applied to the control gate in the range not to be erased. Data can be retained.

In the embodiment, the NOR type EEPROM has been described. However, the present invention can be similarly applied to a NAND type EEPROM.

[Effects of the Invention] As described above, according to the present invention, there are a write mode by hot electron injection and an erase mode by tunnel emission. In the erase mode, the mode between the floating gate (charge storage layer) and the well (channel region) is provided. By using tunneling, it is possible to provide an EEPROM control method that improves reliability.

[Brief description of the drawings]

FIG. 1 is a plan view showing an EEPTOM memory cell array according to one embodiment of the present invention, FIGS. 2 (a) and 2 (b) are cross-sectional views taken along the lines AA 'and BB' of FIG. 1, and FIG. Similarly, FIG. 4 is a diagram showing a potential relationship in each operation mode. DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate, 2 ... p-type well, 3 ... element isolation insulating film, 4 ... tunnel oxide film, 5 ... floating gate, 6 ... interlayer insulating film, 7 ... control gate, 8 ... n-type diffusion layer, 9 ... CVD oxide film, 10 ... bit line.

Continuation of front page (56) References JP-A-3-295097 (JP, A) JP-A-2-11075 (JP, A) JP-A-2-11078 (JP, A) JP-A-2-1986 (JP) JP-A-64-81272 (JP, A) JP-A-63-25981 (JP, A) JP-A-57-15470 (JP, A) JP-A-62-183161 (JP, A) 61-127179 (JP, A) JP-A-55-120171 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 G11C 16/04 H01L 27/115 H01L 29 / 788 H01L 29/792

Claims (4)

(57) [Claims] A first conductive type semiconductor substrate formed on a first conductive type semiconductor substrate;
A non-volatile semiconductor storage device in which a plurality of memory cells are arrayed and formed in a conductive type well, wherein the memory cell is a first conductive type source and drain diffusion layer formed in the second conductive type well. A floating gate formed in a region interposed between the source and drain diffusion layers via a tunnel insulating film, and a control gate formed on the floating gate via an interlayer insulating film; A write mode connected to a source line, in which a selected memory cell is turned on to generate hot carriers near a drain diffusion layer and inject the hot carriers into a floating gate, and a control gate of a plurality of memory cells in a predetermined range. 0V to apply a high potential to the second conductivity type well, thereby causing the floating gate carriers of the memory cells within that range to have the second conductivity type well. A is released by the tunnel current, a threshold voltage of the memory cell
An erase mode in which the voltage is 0 V or higher and lower than a threshold voltage at the time of writing. 2. The nonvolatile memory according to claim 1, wherein in the erase mode, a control potential having the same polarity as a potential applied to the second conductivity type well is applied to a control gate of a memory cell in a range not to be erased. Method for controlling nonvolatile semiconductor memory device. 3. A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged and formed on a semiconductor substrate, wherein the memory cells are formed in a source and drain diffusion layer, and in a channel region sandwiched between the source and drain diffusion layers. A charge storage layer formed via a tunnel insulating film, and a control gate formed on the charge storage layer via an interlayer insulating film, causing a selected memory cell to be turned on to generate hot carriers, A first mode in which the hot carriers are injected into the charge storage layer; and a high potential is applied between the control gate and the channel region for a plurality of memory cells in a predetermined range, so that the charge storage layer of the memory cells in the range is A second mode in which carriers are emitted to the channel region by a tunnel current. A method for controlling a nonvolatile semiconductor memory device, comprising: Law. 4. The second mode is an erase mode. In the erase mode, a control potential having the same polarity as a potential applied to the channel region is applied to a control gate of a memory cell in a range not to be erased. 4. The method for controlling a nonvolatile semiconductor memory device according to claim 3, wherein: