JP3389003B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a non-volatile semiconductor memory device, a threshold voltage of a transistor in a memory cell section is usually changed depending on whether or not a prescribed amount of charge is stored in a floating gate, and this is changed to "0" or "1". The program is put in the state of "" and the memory is retained. Generally, as a memory cell of a non-volatile semiconductor memory device, a MOS type semiconductor device having a structure having a two-layer polysilicon gate of a floating gate and a control gate is used. The nonvolatile semiconductor memory device has a floating gate electrode on a tunnel oxide film formed on a silicon substrate, an ONO film on the floating gate electrode, and a control gate electrode on the ONO film. Further, a drain region and a source region are formed on the silicon substrate on both sides of the floating gate electrode.

Rewriting of this non-volatile semiconductor memory device is performed by injecting or extracting charges through a tunnel oxide film. For example, a potential of 15V is applied to the control gate electrode and a potential of 0V is applied to the drain region and the silicon substrate to bring the source region into a floating state, thereby injecting electrons from the drain region to the floating gate through the tunnel oxide film (erasing operation). At this time, the electric field applied to the tunnel oxide film is E _tox = [V _td + C _ono * {V _cg −V _t } / (C _ono +
C _tox )] / d _tox . Where E _tox is the tunnel oxide film electric field, C
_ono is the ONO film capacity, C _tox is the tunnel oxide film capacity, V
_cg is the control electrode voltage, V _td is the threshold voltage of the floating gate electrode, and V _t is the threshold voltage of the control gate electrode.

Further, the control gate electrode and the silicon substrate are 0
By applying a potential of 15 V to the V and drain regions to bring the source region into a floating state, electrons are extracted from the floating gate electrode to the drain region through the tunnel oxide film (writing operation). At this time, the electric field applied to the tunnel oxide film is E _tox = [V _td + {C _ono * {V _d −V _t } + (1-K
_d ) C _tox * V _d } / (C _ono + C _tox )] / d _tox . Where E _tox is the tunnel oxide film electric field, C
_ono is the ONO film capacity, C _tox is the tunnel oxide film capacity, V
_d is the voltage of the drain region, V _td is the threshold voltage of the floating gate electrode, V _t is the threshold voltage of the control gate electrode, and K _d is the tunnel oxide film capacitance in which the drain and the floating gate pass through the tunnel oxide film. It is the ratio occupied by the wrapping area. It is shown that, when the voltage applied to the drain is the same, the larger K _d is, that is, the larger the region where the drain and the floating gate electrode overlap, the smaller the electric field of the tunnel oxide film.

To read the state of the memory cell,
0V for source region and silicon substrate, 6V for drain region
When a potential of 2 is applied to the control gate electrode and a potential of 2 V or more is applied to the memory cell, it is determined whether or not a current of a specified amount or more flows, and the state of "0" or "1" is determined.

[0006]

In the memory cell shown in the conventional example, by applying a high electric field to the tunnel oxide film, charges are extracted from the floating gate electrode by utilizing the tunnel phenomenon to change the storage state. ing. At this time, if K _d is small, a high electric field is applied to a minute region of the tunnel oxide film, causing damage to the tunnel oxide film in the local region, and reducing the reliability of the memory cell.
On the other hand, if K _d is increased, the electric field applied to the tunnel oxide film is reduced, so that the reliability of the tunnel oxide film is improved, but the short channel effect of the memory cell transistor is increased, so that the punch-through breakdown voltage is lowered. There will be problems such as

Therefore, an object of the present invention is to provide a non-volatile semiconductor device which controls the short channel effect of a memory cell transistor and has a highly reliable tunnel oxide film.

[0008]

In order to solve the above problems, the present invention reduces the surface concentration of a semiconductor substrate in a region where a drain and a floating gate overlap each other, so that the drain and the floating gate overlap at the time of reading. The region is made small, and when a high voltage is applied to the drain during the program operation, the depletion layer at the end of the drain is enlarged to increase the overlap region of the drain and the floating gate.

Therefore, during a write operation in which a high electric field is applied to the tunnel oxide film, the overlap region between the drain and the floating gate becomes large, so that the density of damage to the tunnel oxide film is reduced and the reliability is high. It is intended to realize a memory cell, and realize a memory cell capable of suppressing the short channel effect by improving the punch-through breakdown voltage by reducing the overlap region of the drain and the floating gate during the read operation.

[0010]

By using the above-mentioned means, the size of the overlap region of the drain and the floating gate is changed according to each operation of the nonvolatile semiconductor memory device.
It is possible to realize a nonvolatile semiconductor memory device having high reliability and suppressing the short channel effect.

[0011]

First Embodiment Next, a first embodiment in which the present invention is applied to a nonvolatile semiconductor memory device will be described with reference to FIG. FIG. 1 is a vertical sectional view showing a nonvolatile semiconductor memory device of the present invention.

A tunnel oxide film 10 having a film thickness of 90Å is formed on a silicon substrate 101 having a p-type impurity density of 1E15 / cm ^3.
2, a floating gate 103 formed of a polycrystalline silicon film having a thickness of 1500 Å, and 10 on the floating gate 103.
An interlayer insulating film 104 composed of a composite film of a silicon oxide film having a film thickness of 0 Å, a silicon nitride film having a film thickness of 150 Å, and a silicon oxide film having a film thickness of 100 Å, and a 1500 Å film on the interlayer insulating film 104. Control gate electrode 10 formed with a large thickness
5 is formed.

The element active region of the silicon substrate 101 on one side of the control gate electrode 105 is 1.0E21 / cm ^3.
A first arsenic diffusion layer 106 having a moderate concentration is formed. Further, 2.0E15 is formed in the region of the silicon substrate 101 facing the floating gate from the first arsenic diffusion layer 106.
A boron diffusion layer 107 having a moderate concentration is formed and overlaps the floating gate. Further, the boron diffusion layer 1
Connected to the first arsenic diffusion layer 106 below 07.
A second arsenic diffusion layer 108 having a concentration of about 1.0E18 is formed, and the first arsenic diffusion layer 106 and the second arsenic diffusion layer 108 form a drain region.

Further, the silicon substrate 1 on the other side of the control gate electrode 105 and on the opposite side of the drain region.
In the element active region of 01, the third arsenic diffusion layer 109 of about 2.0E20 is formed and constitutes the source region.

In the nonvolatile semiconductor memory device shown in FIG. 1, the erase operation is performed by applying a potential of 15V to the control gate electrode 105 and a potential of 0V to the drain electrode 106 and the substrate electrode 101.
By making the source electrode 109 in a floating state, electrons are injected from the semiconductor substrate 101 to the floating gate 103 through the tunnel oxide film 102.

Further, the write operation is performed by the control gate electrode 10.
5 and 0 V for the substrate electrode 101 and 15 for the drain electrode 106.
By applying a potential of V to make the source electrode 109 in a floating state, the floating gate 10 is passed through the tunnel oxide film 102.
The electrons are extracted from 3 to the drain 106. At this time, due to the voltage applied to the drain electrode 106, the boron diffusion layer 1
Since 07 is depleted, the overlap region between the drain region 106 and the floating gate 103 is apparently large. Therefore, since the electric field applied to the tunnel oxide film 102 is small, the reliability of the tunnel oxide film 102 is high.

To read the state of the memory cell,
When a potential of 0 V is applied to the source electrode 109 and the substrate electrode 101, a potential of 6 V is applied to the drain electrode 106, and a potential of 2 V is applied to the control gate electrode 105, it is determined whether or not a current of a specified amount or more flows in the drain electrode 106. Then, the state of “0” or “1” is determined. At this time, the drain electrode 106
Since the boron diffusion layer 107 is not depleted by the voltage applied to the drain region 106 and the floating gate 103, the overlap region is small, the short channel effect does not occur, and the punch-through breakdown voltage does not decrease.

Next, a method of manufacturing the above-mentioned nonvolatile semiconductor memory device of the present invention will be described with reference to FIGS. 2A to 2C are side sectional views showing a first embodiment of the manufacturing process of the non-volatile semiconductor device of the present invention.

First, the p-type silicon substrate 201 having a specific resistance of about 10 Ω / cm ² is thermally oxidized to form a silicon oxide film 202 having a thickness of about 40Å to 50Å on the surface of the p-type silicon substrate 201. Further, in order to form the second diffusion layer, the region other than the region where the second arsenic diffusion region is formed is covered with the photoresist 203, and the photoresist 20 is formed.
5E with energy of about 70 keV using 3 as a mask
Arsenic 204 with a dose of about 14 is added to the silicon substrate 201.
Ion implantation. Further, BF ₂ ions 205 with an energy of about 30 keV and a dose of about 2E14 are ion-implanted into the silicon substrate 201 (FIG. 2A).

Next, after removing the photoresist 203, a polycrystalline silicon film 211 having a film thickness of about 1500 Å is deposited on the silicon substrate 201 by the CVD method to form a floating gate. Further, the polycrystalline silicon film 211
An interlayer insulating film 212 made of ONO (silicon oxide film, silicon nitride film, silicon oxide film) is formed by sequentially depositing a silicon oxide film of about 100 Å, a silicon nitride film of about 50 Å, and a silicon oxide film of about 100 Å on it. To do. Further, a polycrystalline silicon film 213 having a film thickness of about 1500Å is deposited by the CVD method. Next, after forming a photoresist (not shown) on the polycrystalline silicon film 213, the photoresist (not shown) is patterned by photolithography, and the photoresist (not shown) is used as a mask to form the polycrystalline silicon film. 213, the interlayer insulating film and the polycrystalline silicon 211 are sequentially etched to form the floating gate 211 and the control gate electrode 213. Then, this photoresist is removed (see FIG.
(B)).

The floating gate 211 and the control gate electrode 21
3 is formed, arsenic ions with a dose of about 3.0 × 10 ¹⁵ / cm ² are ion-implanted into the silicon substrate 201 on both sides of the control gate with an energy of about 80 keV to form the source / drain diffusion layers 221. I do. After that, the source / drain diffusion layers 221 are formed by annealing in a nitrogen atmosphere to activate the impurities (see FIG. 2C).

Further, although not shown, a non-volatile semiconductor memory device can be formed by going through an ordinary aluminum wiring forming process in a post process.

[0023]

Second Embodiment Next, a second embodiment in which the present invention is applied to a method for manufacturing a nonvolatile semiconductor memory device will be described with reference to FIG. 3A to 3D are side sectional views showing a second embodiment of the method for manufacturing a nonvolatile semiconductor memory device of the present invention.

First, the p-type silicon substrate 301 having a specific resistance of about 10 Ω / cm ² is thermally oxidized to form a silicon oxide film 302 having a film thickness of about 40Å to 50Å on the surface of the p-type silicon plate 301. Further, in order to form a boron diffusion layer, a region other than a region where a boron diffusion layer region is formed is covered with a photoresist 303, and using the photoresist as a mask, BF ₂ ions 305 with an energy of about 30 keV and a dose of about 5E14 are applied to a silicon substrate. Ions are implanted into 301 (see FIG. 3A).

Next, to form the floating gate, 1500
A polycrystalline silicon film 311 having a film thickness of about Å is deposited by the CVD method. Furthermore, 100 is formed on the polycrystalline silicon film 311.
An interlayer insulating film 312 made of ONO (silicon oxide film, silicon nitride film, silicon oxide film) is formed by sequentially depositing a silicon oxide film of about Å, a silicon nitride film of about 50 Å, and a silicon oxide film of about 100 Å. Further, a polycrystalline silicon film 313 having a film thickness of about 1500 Å is deposited on the interlayer insulating film 312 by the CVD method. Next, after forming a photoresist (not shown) on the polycrystalline silicon film 313, the photoresist (not shown) is patterned by photolithography, and using the photoresist as a mask, the polycrystalline silicon film 313, the interlayer insulating film Then, the polycrystalline silicon film 311 is sequentially etched to form a floating gate 311 and a control gate electrode 313. After that, the photoresist is removed (the above FIG. 3B).

Next, in order to form the second diffusion layer, only the source region of the memory cell is covered with the photoresist 321 by photolithography, and the photoresist 321 and the control gate 313 are used as a mask to remove from the vertical line of the semiconductor substrate. 5E with an energy of about 100 keV at an angle of 45 degrees
Arsenic 322 with a dose of about 14 is added to the silicon substrate 311.
Are ion-implanted into the substrate (FIG. 3C).

Then, after removing the photoresist 321,
3.0 × 10 to form the source / drain diffusion layer
Arsenic ion 331 with a dose amount of about ¹⁵ / cm ² is 80k
Ions are implanted into the silicon substrate 301 on both sides of the control gate electrode with energy of about eV. After that, the source / drain diffusion layers 221 are formed by annealing in a nitrogen atmosphere to activate the impurities (see FIG. 3 above).
(D)).

Further, although not shown, a non-volatile semiconductor memory device can be formed by going through a normal aluminum wiring forming process in a post process.

As described above, the nonvolatile semiconductor memory device according to the first embodiment of the present invention has the tunnel oxide film 102 formed on the silicon substrate 101 and the floating gate electrode formed on the tunnel oxide film 102. 103 and an ONO film 104 formed on the floating gate electrode 103.
And the control gate electrode 105 formed on the ONO film 104, and the source / drain 10 formed on the silicon substrate 101 on both sides of the control gate electrode 105.
9. A nonvolatile semiconductor memory device further including: 9, 106, a diffusion layer 107 containing boron only in the vicinity of the drain side of the silicon substrate 101 directly below the floating gate electrode 103, and the diffusion layer containing boron. 107
A diffusion layer 108 containing arsenic, which is a part of the drain 109, is provided below, and the diffusion layer 108 is formed so as to be in contact with the drain 109. That is, a nonvolatile semiconductor memory device is provided by providing an impurity region containing boron only in the surface layer of the silicon substrate 101 immediately below the region near the drain of the floating gate electrode, and further providing an impurity containing arsenic below the impurity region containing boron. It is possible to suppress the short channel effect in and to improve the punch-through breakdown voltage.

Further, in the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment, after the tunnel insulating film is formed on the semiconductor substrate, the N-type is formed in the selected partial selected region of the semiconductor substrate. By introducing an impurity and a P-type impurity, P in the surface layer region of the semiconductor substrate in the selected region is introduced.
Type impurities are introduced, and N type impurities are introduced into the semiconductor substrate immediately below the P type impurities in the selected region. Then, it is a step of forming a floating gate electrode on the tunnel insulating film in the selected region, and the N-type and P-type impurity regions are formed so as to be disposed at least just under one end portion of the floating gate electrode. . Next is a step of forming a pair of source / drain containing N-type impurities in the semiconductor substrate on both sides of the floating gate electrode, the drain being formed in contact with the N-type impurity region of the selected region. This suppresses the short channel effect and further improves the punch-through breakdown voltage.

Further, according to another embodiment of the method of manufacturing a nonvolatile semiconductor memory device of the present invention, after forming a tunnel insulating film on a semiconductor substrate, a P-type is formed in a selected partial selected region of the semiconductor substrate. By introducing the above impurity, P type impurities are introduced into the surface layer region of the semiconductor substrate in the selected region. After that, in the step of forming a floating gate electrode on the tunnel insulating film in the selected region, at least the P-type impurity region is formed immediately below the region near one end of the floating gate electrode. After that, an N-type impurity is introduced just below the P-type impurity region by an oblique ion implantation method. Forming a pair of source / drain containing N-type impurities on the semiconductor substrate on both sides of the floating gate electrode, wherein the drain is formed so as to contact the N-type impurity region of the selection region. This suppresses the short channel effect and further improves the punch-through breakdown voltage.

[0032]

EFFECTS OF THE INVENTION A non-volatile semiconductor having high reliability and a short channel effect suppressed by adopting a structure in which the size of the overlap region of the drain and the floating gate can be changed according to each operation of the non-volatile semiconductor memory device. A storage device can be realized.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a vertical cross-sectional manufacturing process diagram showing a manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a vertical cross-sectional manufacturing process diagram showing the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

[Explanation of symbols]

101 p-type silicon substrate 102 tunnel oxide film 103 floating gate 104 interlayer insulating film 105 control gate electrode 106 first arsenic diffusion layer (drain region) 107 boron diffusion layer 108 second arsenic diffusion layer (drain region) 109 third Arsenic diffusion layer (source region) 110 Aluminum wiring 201 p-type silicon substrate 202 Tunnel oxide film 203 Photoresist 204 Arsenic ions 205 BF ₂ ions 206 First arsenic diffusion layer (drain region) 211 Polycrystalline silicon film (floating gate) 212 Interlayer insulating film 213 Polycrystalline silicon film (control gate electrode) 221 Source / drain diffusion layer 301 p-type silicon substrate 302 Tunnel oxide film 303 Photoresist 305 BF ₂ ion 311 Polycrystalline silicon film (floating gate) 312 Interlayer insulating film 313 Multi crystal Silicon film (control gate electrode) 321 photoresist 322, arsenic ions 331 source / drain diffusion layer

Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/792

Claims (7)

(57) [Claims] 1. A tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an insulating film formed on the floating gate electrode, and formed on the insulating film. And a control gate electrode arranged to face the floating gate electrode, and a pair of source / drain containing impurities of the first conductivity type formed on the semiconductor substrate on both sides of the floating gate electrode, An impurity diffusion layer formed immediately below the floating gate electrode and in the vicinity of the drain side of the semiconductor substrate, the impurity diffusion layer containing an impurity of a second conductivity type having a conductivity type opposite to that of the first conductivity type; Further comprising at least a first conductivity type impurity diffusion layer on the semiconductor substrate immediately below the conductivity type impurity diffusion layer ,
A nonvolatile semiconductor memory device in which the first conductivity type impurity diffusion layer is formed in contact with the drain. 2. A method of manufacturing a non-volatile semiconductor memory device, comprising: a first step of forming a tunnel insulating film on a semiconductor substrate; and a first step in a selected part of a selected region of the semiconductor substrate.
By introducing an impurity of the second conductivity type having a conductivity type opposite to that of the impurity of the conductivity type and the impurity of the first conductivity type,
A second impurity region of a second conductivity type formed in the surface region of the semiconductor substrate of the selected region, further, said second impure
On the semiconductor substrate directly below the object region ,
A second step of forming an impurity region ; and a step of forming a floating gate electrode on the tunnel insulating film in the selection region, at least immediately below the one end of the floating gate electrode . A third step of forming the impurity regions so as to be arranged, and a step of forming a pair of source / drain containing impurities of the first conductivity type in the semiconductor substrate on both sides of the floating gate electrode, The drain is the first impurity region
Method of manufacturing a nonvolatile semiconductor memory device characterized by comprising a fourth step which is formed in contact with the band. 3. A method for manufacturing a nonvolatile semiconductor memory device, comprising: a first step of forming a tunnel insulating film on a semiconductor substrate; and a first step in a selected partial selected region of the semiconductor substrate.
Second step of forming a first impurity region in the surface layer region of the semiconductor substrate in the selected region by introducing an impurity of the conductivity type, and on the tunnel insulating film in the selected region. A third step of forming a floating gate electrode, the third step of forming the first impurity region so as to be arranged at least immediately below a region near one end of the floating gate electrode; A second conductivity type impurity having a conductivity type opposite to that of the first conductivity type impurity is introduced into the semiconductor substrate immediately below the first impurity region by an oblique ion implantation method to form a second impurity region.
A fourth step of forming and a fifth step of forming a pair of source / drain containing impurities of the second conductivity type on the semiconductor substrate on both sides of the floating gate electrode, wherein the drain is the selection region. In front of
Method of manufacturing a nonvolatile semiconductor memory device characterized by comprising a fifth and a step further formed to contact the serial second impurity regions. 4. The third aspect of claim 2 or claim 3.
2. The method of manufacturing a non-volatile semiconductor memory device, further comprising the step of forming an insulating film on the floating gate electrode and the step of forming a control gate electrode on the insulating film. 5. The non-volatile memory according to claim 1, wherein the first conductivity type impurity is an N type impurity, and the second conductivity type impurity is a P type impurity. Semiconductor memory device. 6. The nonvolatile memory according to claim 2, wherein the first conductivity type impurity is an N type impurity, and the second conductivity type impurity is a P type impurity. Of manufacturing a non-volatile semiconductor memory device. 7. The non-volatile semiconductor device according to claim 3, wherein the first conductivity type impurity is a P type impurity, and the second conductivity type impurity is an N type impurity. Of manufacturing a non-volatile semiconductor memory device.