JPH0329371A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory transistor in thin structure without deteriorating a gate insulating film on writing by constituting an injection region of hot electrons into a floating gate on writing and a tunnel injection region on erasure with a different lamination structure. CONSTITUTION:A conductive layer 2 which becomes a gate electrode of a memory transistor of a semiconductor substrate 1 is provided and a channel region 7b of the memory transistor is provided through an insulating film 6 and a source region 7c and a drain region 7a are provided being adjacent to this channel region 7b on this conductive layer 2. Then, a floating gate electrode 5 is provided on the channel region 7b through a second insulating film 8 and an erasure gate electrode 13 is provided on this floating gate electrode 5 through a third tunnel insulating film 12, thus obtaining a memory transistor in a fine structure without deteriorating the gate insulating film 6 on writing.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor memory device, particularly a floating gate type electrically writable and rewritable nonvolatile semiconductor memory device that is most suitable for electrical bulk erasing.

BACKGROUND ART FIG. 3 is a vertical cross-sectional view of a conventional electrical batch erasing type nonvolatile semiconductor memory device. The structure and operation of this nonvolatile semiconductor memory device will be explained with reference to FIG.

For example, on the surface of a P-type silicon substrate 10, a memory cell (memory transistor) region is formed which is electrically insulated from adjacent regions by a field insulating film 3.

In this memory cell region, an N-type drain region 7a and a source region 7C are formed in a silicon substrate 1 at a distance from each other, and a region sandwiched between the drain region 7a and the source region 7C is , a channel region 7b of the memory cell is formed.

On this channel region 7b, a first gate isolation &tl[
6, a floating gate 5 is placed on top of the floating gate 5, and a gate electrode 9 is placed on top of the floating gate 5 with a second gate insulating film 8 placed thereon.
Each layer is layered.

Note that lead electrodes (wirings) 1]a, Ilb, and Ilc are taken out from each of the drain 7a, control gate 9, and source 7c electrodes.

Here, the surface portion of the source region 7C of the first gate insulating film 6 is a tunnel injection region 4, and a tunnel current flows between it and the floating gate 5 due to the high voltage applied to the source region 7C. It is a structure.

In such a conventional nonvolatile semiconductor memory device, writing is performed by applying a high voltage to the drain region 7a and the gate electrode 9, applying a ground potential to the source region 7c, and turning on the channel region 7b. let As a result, a current flows through the channel region 7b, and the current generates hot electrons near the drain region 7a, and some of the hot electrons are injected into the floating gate 5. Since a negative potential is constantly applied to the channel region 7b by electrons jumping into the floating gate 5, the threshold voltage of the channel region 7b increases in the positive direction, and storage data is stored as the threshold voltage increases.

On the other hand, for erasing, a high positive voltage is applied to the source region 7c, and a ground potential is applied to the gate electrode 9 and drain region 7a. As a result, a tunnel current flows from the floating gate 5 to the source region 7c via the tunnel injection region 4, and as a result, the electrons accumulated in the floating gate 5 are extracted. Therefore, the threshold voltage of channel region 7b decreases to its initial value.

In the figure, 7d indicates a high voltage source region, and 10 indicates a glabella insulating film.

Problems to be Solved by the Invention However, the above-mentioned conventional nonvolatile semiconductor memory device had the following problems. First, a high voltage is applied to the source of the memory transistor when tunneling current flows between it and the floating gate.
It must have a structure that can withstand this high voltage (hereinafter referred to as high withstand voltage). Conventionally, the source has been formed as an impurity diffusion region on the surface of a silicon substrate, but in order to form a source with high breakdown voltage, the impurity diffusion region must be formed deeply. However, when the impurity diffusion region is formed deeply, the diffusion of impurities into the channel region also increases, and the effect of shortening the channel length becomes noticeable. Therefore, reduction in the length of the memory transistor in the channel direction is limited.

The second drawback is that the first gate insulating film and the tunnel injection region are on the same plane.

Normally, in the tunnel injection region, a tunnel current is passed through a thin silicon oxide film (tunnel oxide film) of less than IOOA. First game}. In order to arrange the ia edge film and the tunnel injection region on the same plane, the first gate insulating film and the tunnel oxide film may be formed of the same film, or a part of the first gate insulating film may be formed. The tunnel injection region is formed by an additional process.

However, in the former case, the first gate insulating film is
If it is below A, hot electrons will pass through the first gate insulating film below IOOA during the write operation of the memory transistor. As a result, the quality of the first gate insulating film is significantly deteriorated due to defect levels generated by the passage of hot electrons, which immediately leads to deterioration of the characteristics of the memory transistor.

On the other hand, the latter method is disadvantageous for planar reduction because it is inevitable to add a process including one-time mask alignment, and manufacturing margins associated with mask alignment must be taken into consideration.

<Differences between the invention and the prior art> In contrast to the above-described conventional nonvolatile semiconductor memory device, the nonvolatile semiconductor device according to the present invention has a structure in which a first insulating film and a second wA edge film are laminated. formed in separate layers,
Another difference is that the channel of the memory transistor is not formed in the silicon substrate but in a silicon thin film on an insulating film.

<Means for Solving the Problems> A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate provided with a conductive layer serving as a gate electrode of a memory transistor,
A channel region of the memory transistor is provided on this conductive layer via a first insulating film, a source region and a drain region are provided adjacent to this channel region, and a floating region is provided on this channel region via a second insulating film. A gate electrode is provided, and an erase gate electrode is provided on the floating gate electrode with a third tunnel insulating film interposed therebetween.

<Example> Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

In the figure, a conductive layer 2 made of an N-type impurity diffusion layer is formed in a predetermined region of the surface of a P-type silicon substrate l. That is, the conductive layer 2 is formed in a region surrounded by the field insulating film 3 on the surface of the silicon substrate l.

A silicon thin film is deposited above the conductive layer 2 with a first gate insulating film 6 interposed therebetween. A channel 7b of a memory transistor is provided in this silicon thin film. Further, on both sides of this channel 7b, a drain 7a16 and a source 7C of the memory transistor are formed adjacent to each other.

Here, this conductive layer 2 has a role as a gate electrode of a memory transistor.

On this memory transistor, there is a second gate disconnected 8MB memory transistor.
A floating gate 5 is disposed through the gate.

On this floating gate 5 is a third insulating film (Tunnel Zetsu! 1
31) An erase gate 13 is provided via 12. Although not shown in the figure, a conductive layer (gate electrode) 2,
The drain 7a, the source 7b, and the erase gate 13 are insulated from each other by a glabellar membrane, and each is provided with an extraction electrode.

Next, writing in the nonvolatile semiconductor memory device of this example,
The erase operation will be explained.

Writing is performed by applying a high positive voltage to the conductive N2, which is the gate electrode of the memory transistor, and the drain 7a.

As a result, the channel 7b is turned on, a current flows between the source 7c and the drain 7a of the memory transistor, and hot electrons are generated in the channel portion 7b.

Some of these hot electrons are injected into the conductive layer 2 and the floating gate 5, and the electrons injected into the floating gate 5 fix the potential of the floating gate 6 to a negative value. A negative potential is applied to the channel 7b from the upper surface by the floating gate 5, and this negative potential shifts the channel threshold voltage of the memory transistor in the positive direction. As a result, memory data is accumulated.

On the other hand, erasing is performed by applying a high voltage to the erasing gate 13 and applying a ground potential to the drain 7as, the source 7c, and the conductive layer 2.

As a result, a tunnel current flows between the erase gate 13 and the floating gate 5, and as a result, the electrons accumulated in the floating gate 5 are extracted to the erase gate 13 side. As a result,
The threshold voltage of channel 7b will drop to its initial value.

FIG. 2 is a longitudinal sectional view of a nonvolatile semiconductor memory device according to a second embodiment of the invention.

In this embodiment, element isolation of the memory transistor is performed by a trench-buried oxide film l4.

In this case, on the silicon substrate 1, a conductive layer 2, a first gate oxide film 6, a silicon thin film, a second gate oxide film 8,
Floating gate 5, tunnel insulating film 12, and erase gate 13 are stacked in this order.

After sequentially stacking these, grooves for element isolation are formed in the silicon substrate 1 by etching.
A memory cell can be manufactured by the step of filling this trench with the oxide film 14.

Note that the drain 7a, channel 7b, and source 7C of the memory transistor are formed in the silicon thin film.

Since the element isolation step is performed after the memory cell is formed in this manner, the memory cell region and the element isolation region are formed in a self-aligned manner, which is extremely effective in reducing the size of the memory cell.

Furthermore, there is also the advantage that the number of photolithography operations can be significantly reduced.

<Effects of the Invention> As described above, the present invention provides an electrically batch erasable type rewritable nonvolatile semiconductor memory device, which includes a region in which hot electrons are injected into a floating gate during writing;
By configuring the tunnel injection region during erasing and a different layer in the stacked structure, there is an effect that a memory transistor with a fine structure can be obtained without deterioration of the gate insulating film during writing.

[Brief explanation of drawings]

1 is a vertical cross-sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, and FIG. The figure is a longitudinal cross-sectional view of a conventional nonvolatile semiconductor memory device. 1 ● 2 ● 3 ・ 4 ● 5 ・ 6 ◆ ・Silicon substrate, ・First conductive layer, ・Field insulating film, ・Tunnel injection region, ・Floating gate, ・First gate insulating film, 7a ・ ・ ・ 7 b ・ ・ ・ 7c ・ ・ ・ 8 ・ ・ ・ ・ 9 ・ ・ ・ 1 0 ・ ◆ 11a ・ ・ 11b ● ・ 11c ◆ ● 1 2 ・ ● ◆ l 3 ・ ・ ・ Train region, channel region, source region , second gate insulating film, gate electrode, glabellar insulating film, train lead electrode, gate lead electrode, source lead electrode, tunnel insulating film, erase gate.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type, a conductive layer of the opposite conductivity type provided on this semiconductor substrate, a semiconductor thin film laminated on this conductive layer with a first insulating film interposed therebetween, and provided on this semiconductor thin film, a channel region of one conductivity type disposed on the conductive layer; a source region and a drain region of opposite conductivity type provided in the semiconductor thin film so as to sandwich the channel region;
A floating gate is laminated on the channel region with a second insulating film interposed therebetween, and a third insulating film is laminated on the floating gate with a third insulating film interposed therebetween, and charges accumulated in the floating gate are transferred to the third insulating film. An electrode for drawing tunnel current inside,
A nonvolatile semiconductor memory device comprising: