JP3298469B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an electrically erasable nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional flash memory is shown in FIGS.
9 will be described. FIG. 18 is a cross-sectional view illustrating an example of a conventional split gate flash memory (Japanese Patent Laid-Open No. 8-97304). FIG. 19 is a diagram for explaining an example of a conventional stack type flash memory (Japanese Patent Laid-Open No. 6-283721). While a stack-type flash memory originally constitutes one memory cell with one transistor, a split-gate flash memory is composed of two transistors, a select transistor part and a memory cell transistor part. ing. Figure 1
8, in FIG. 19, 1 is a semiconductor substrate, 2 is a flash memory cell section channel, and 3 is a select transistor section channel.
Le, the tunnel insulating film 4, the selection gate insulating film 5, 6 floating gates, 7,8 poly insulating film, 9 a control gate, 10 denotes a drain, 13 denotes a silicon nitride
The oxide films 12 , 17 , and 20 are silicon oxide films .

An advantage of the split gate flash memory is that the threshold value on the low level side is determined by the selection transistor. As a result, in the split gate flash memory, the variation in the threshold voltage on the low level side can be considerably reduced as compared with the variation in the threshold voltage in the stacked flash memory, and the read voltage can be easily reduced. Also, in the split gate type flash memory, the threshold value of the memory cell portion can be lowered so as to be sufficiently depleted.
On current can be increased with respect to the cell size, and high-speed reading can be realized.

A split gate flash memory is
Unlike the stack type flash memory, two types of insulating films are used between the floating gate 6 and the control gate 9. Figure 1 shows a split-gate flash memory.
As shown in FIG.
A silicon oxide film is formed on the side surfaces of the NO film (a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film) and the floating gate 6. When the ONO film is formed on the side surface of the floating gate 6, the gate insulating film 5 of the select transistor also becomes an ONO film at the same time, and electrons are trapped in the gate insulating film 5 of the select transistor while writing and erasing are repeated. This is to prevent characteristic fluctuations.

Next, a method of manufacturing a conventional split gate flash memory will be described with reference to FIGS. As shown in FIG. 20, after forming an element isolation region (not shown) in the semiconductor substrate 1 of the first conductivity type, the semiconductor substrate 1 has a thickness of about 30 nm.
Silicon oxide film 18 and silicon nitride of about 300 nm
A film 19 is formed. Next, the silicon nitride film 19 is flashed.
Memory cell section channel 2 and select transistor section channel
And patterned to leave only on the region to be a Le 3, silicone
The source 11 and the drain 10 are formed by implanting arsenic using the nitride film 19 as a mask.

[0006] Next, as shown in FIG.
Approximately 100 nm silicon on the source 11 and the drain 10
After forming the phosphorylated film 20, the silicon nitride film 19 and the sheet
The silicon oxide film 18 is removed.

Next, as shown in FIG. 22, a silicon oxide film 4 serving as a tunnel oxide film, a conductive layer 6 serving as a floating gate, a silicon oxide film 12 and a silicon nitride film are formed.
Between the ONO structure poly composed of silicon oxide film 13 and silicon oxide film 17
An insulating film is formed, and the interpoly insulating film and the conductive layer 6 are simultaneously patterned so that they remain only on the flash memory cell section channel 2 . Next, the side of the conductive layer 6 and the selection
The region of the transistor section channel 3 is thermally oxidized.

Next, as shown in FIG. 23, a conductive layer 9 serving as a control gate is formed, and a conductive layer 6 and an ONO structure are formed.
The interpoly insulating film and the conductive layer 9 are simultaneously etched to form the control gate 9 and the floating gate 6.

[0009]

However, in the above-mentioned conventional split gate type flash memory,
When the side surfaces of the conductive layer 6 are oxidized after the ONO film and the conductive layer 6 are etched, the upper part of the conductive layer 6 is covered with the nitride film. When oxidized in this state, as shown in FIG. 24 (an enlarged view showing the upper corner of the floating gate in FIG. 18), the conductive
The corners of the ends of the layer 6 are sharpened with a thin silicon oxide film. In addition, since there is a boundary between the ONO film and the silicon oxide film 8 near this corner, there is a problem that leakage from the floating gate 6 increases, and charge retention and disturb characteristics deteriorate.

In the conventional split gate type flash memory, in order to solve the above-mentioned problem, the silicon oxide film on the side surface of the floating gate 6 is formed thick, and a sufficient thickness is formed even at the corner at the upper end of the floating gate 6. I had to make it.

However, if the silicon oxide film formed on the side surface of the floating gate 6 is made thicker, the leakage from the floating gate 6 can be suppressed, but the gate oxide film 5 (see FIG. 23) of the select transistor formed at the same time becomes thicker. In addition, there is a problem that the ON current is reduced.

An object of the present invention is to enable high-speed reading,
It is an object of the present invention to provide a nonvolatile semiconductor memory device that has realized good charge retention characteristics and good disturb characteristics, and a method of manufacturing the same.

[0013]

In order to achieve the above object,
Therefore, the nonvolatile semiconductor memory device according to the present invention has the first conductivity type.
Of the second conductivity type formed on the main surface of the semiconductor substrate of the second conductivity type.
Between the source and the drain and the source and the drain
Formed inFlash memory cell section channelArea and
Select transistor section channelArea and saidFlash
Morisel channelTunnel insulating film formed on the region
And floating formed on the tunnel insulating film.
Gate and part of the top surface of the floating gate
MadeFirst insulating filmAnd the floating gate
Part of the top surface and part of the side surface of the floating gate
Formed inSecond insulating filmAnd the saidSelect transistor section
channelA select gate insulating film formed on the region,
First insulating filmAnd saidSecond insulating filmAnd the selection gate
With a control gate formed over the insulating film
A first side surface of the floating gate;
The second aspect and the third aspect are as described above.Second insulating filmThrough
Covered by the control gate,
The fourth aspect of the control gate is the control gate
Not covered with
The first side surface of the floating gate and
And an end contacting the second side surface and the third side surface,
SaidSecond insulating filmCovered with the saidFirst insulating film
Are silicon oxide, silicon nitride and silicon oxide
A three-layer structure of the membrane,First insulating filmIsSecond
Insulating filmContact with the upper surface of the floating gate
It is characterized by the following.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; forming a first conductive layer, the first conductive layer, forming a first silicon oxide film <br/> and the silicon nitride film and the second conductive layer in this order, the first Silicon oxide film and silicon nitride
A step of patterning the film and the second conductive layer, the side surface and the silicon nitride of the first silicon oxide film
Silicon oxide is applied to the side surface of the film and the side surface of the second conductive layer.
Forming a side wall consisting of film, etching the first conductive layer and the second conductive layer and the sidewall as a mask, removing the sidewalls, selected tiger
Forming a select gate insulating film Njisuta section channel region, forming a first insulating film on a part of the upper surface side and the first conductive layer of the first conductive layer, wherein
Forming a step of forming a second insulating film made of a silicon oxide film on the silicon nitride film, a third conductive layer serving as a control gate on said second insulating film, said first
Patterning the third conductive layer, the second insulating film, the first insulating film, and the first conductive layer to form the floating gate and the control gate. is there.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; and forming a floating gate on the tunnel insulating film. Forming a first conductive layer; and forming a first layer having a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the first conductive layer .
Of forming an insulating film, wherein the steps of applying a resist on the first insulating film, patterning the resist, the first conductive layer and the first insulating layer using the resist as a mask a step of patterning, a step of thinning by ashing the resist, etching the first insulating film and said tunnel insulating layer using the resist as a mask, a step of removing the resist, the selection transistor select gate insulating film and on the section channel, and forming a second insulating film on the side surface of a part and the first conductive layer of the upper surface of the first conductive layer, the first
Forming a second conductive layer serving as a control gate on the insulating film , and forming the second conductive layer and the first insulating layer on the insulating film.
Patterning the edge film, the second insulating film, and the first conductive layer to form the floating gate and the control gate.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; and a step of forming a floating gate on the tunnel insulating film. forming a first conductive layer, the first conductive layer on the first silicon oxide film及<br/> beauty silicon nitride film and the second silicon oxide film and the second
Forming a conductive layer in order, and the first silicon oxide
Film, the silicon nitride film, and the second silicon oxide
A step of patterning the film and the second conductive layer, the side surface and the first side surface and the silicon nitride film <br/> side surface and said second silicon oxide film of the first silicon oxide film
The side surface of the second conductive layer, forming a sidewall made of a silicon oxide film, etching the first conductive layer and the second conductive layer and the sidewall as a mask, the sidewalls and the first Removing the silicon oxide film of Step 2 ;
Forming a select gate insulating film to the selection transistor section channel region, forming a first insulating film on a part of the upper surface side and the first conductive layer of the first conductive layer, wherein Forming a second insulating film made of a silicon oxide film on a silicon nitride film , forming a third conductive layer serving as a control gate on the second insulating film, and forming the third conductive layer And the second insulating film and the second
Patterning the first insulating film and the first conductive layer,
Forming the floating gate and the control gate.

Further, in the nonvolatile semiconductor memory device according to the present invention, the gate oxide film of the select transistor is thin, the oxide film at the upper corner of the floating gate is formed thick, and the ONO film and the oxide film which are liable to leak are formed. Boundary
There because it is formed away from the corner of the upper end of the floating gate, while suppressing leakage from the floating gate, resulting a large on-current, it is possible to obtain a flash memory having both good retention properties and high-speed readout.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the side surface of the floating gate and the gate of the select transistor are increased by increasing the amount of phosphorus implanted into the floating gate (3E15 / cm ² or more). When oxidizing, the side surface of the floating gate is rapidly oxidized by the accelerated oxidation, and even if the gate oxide film of the select transistor is thinned, an oxide film enough to suppress leakage can be provided at the upper corner of the floating gate .

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, when oxidizing the side surface of the floating gate and the gate of the selection transistor, the floating gate is prevented from being oxidized at the upper corner of the floating gate. The ONO film on the upper surface of the gate can be formed apart from the edge of the floating gate, and at the same time, the boundary with the ONO film that easily causes leakage can be formed far from the corner of the floating gate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing Embodiment 1 of the present invention.

In FIG. 1, 1 is a semiconductor substrate, 2 is a flash memory cell section channel, 3 is a select transistor section channel, 4 is a tunnel insulating film, 5 is a select gate insulating film, 6 is a floating gate, and 7 and 8 are poly. Insulation between
The film , 9 is a control gate, 10 is a drain, and 11 is a source.

In the first embodiment of the present invention, the gate oxide film 5 of the select transistor is not excessively thickened (for example, about 30
0 °), the silicon oxide film 8 at the upper corner of the side surface of the floating gate 6 is formed thick (for example, about 400).
Å). Therefore, it is possible to suppress the leakage of electrons from the floating gate 6 while maintaining a high on-current. That is, it is possible to obtain a flash memory having high-speed reading, good holding characteristics and good disturb characteristics at the same time.

FIG. 2 shows the manufacturing method according to the first embodiment of the present invention.
This will be described with reference to FIG. As shown in FIG. 2, after forming an element isolation insulating film on the main surface of the semiconductor substrate 1, a silicon oxide film 4 serving as a tunnel oxide film and a conductive layer 6 serving as a floating gate are formed. Next, after injecting the phosphorus ions 3E15 / cm ² or more electrically conductive layers 6, a conductive layer 6
An interpoly insulating film 7 is formed thereon.

Next, as shown in FIG. 3, the poly insulating film 7
Then, the conductive layer 6 is patterned. At this time, the conductive layer 6
Is the channel that will later become the channel
Channel region 2 and later select transistor section channel
Channel region 3 to be covered.

[0026] Next, as shown in FIG. 4, the channel region 3 above
After the silicon oxide film 4 already formed is removed, a silicon oxide film 5 is formed. At this time,
An inter-poly insulating film 8 is formed on the side surface of the conductive layer 6, and a select gate oxide film 5 is formed on a channel region 3 which is to be a channel of a select transistor. The thickness of this select gate oxide film 5 is desirably about 300 °. Next, a conductive layer 9 serving as a control gate is formed. Next, the conductive layer 9 and port
The control gate 9 and the floating gate 6 are formed by patterning the inter-layer insulating film 7 and the conductive layer 6.

Next, as shown in FIG. 5, arsenic ions are implanted using the control gate 9 as a mask to form a source 11 and a drain 10.

(Embodiment 2) FIG. 6 is a sectional view showing Embodiment 2 of the present invention. Embodiment 2 of the present invention shown in FIG.
Now, the ONO film formed on the floating gate 6
Poly insulating film 7 made of, it is formed so as to be positioned inside from the end of the floating gate 6. From the upper corner of the floating gate 6 to the end of the ONO film 7,
Interpoly insulation which is a side oxide film of the floating gate 6
Covered by membrane 8.

Therefore, when the upper corner of the floating gate 6 is oxidized, the inhibition of the oxidation by the nitride film in the ONO film which has occurred in the conventional split gate flash memory is eliminated, and the conventional split gate flash memory is prevented. An oxide film thicker than that is formed. For example, when the gate oxide film 3 of the select transistor is about 300 °, the silicon oxide film formed at the corner of the floating gate 6 becomes about 400 °.

Further, since the boundary between the ONO film 7 and the side oxide film 8 where leakage tends to occur is far from the corner of the floating gate 6 where the electric field is apt to concentrate, the floating gate is smaller than the conventional split gate type flash memory. Leakage of electrons from

A method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to FIGS.
As shown in FIG. 7, after an element isolation insulating film is formed on the main surface of the semiconductor substrate 1, silicon oxide serving as a tunnel oxide film is formed.
An oxide film 4 and a conductive layer 6 serving as a floating gate are formed. Next, after injecting the phosphorus ions to the conductive layer 6, Siri
CON oxide film 12 and first silicon nitride film 13 and conductive
The layer 14 is formed. At this time, conduction with the silicon nitride film 13 is performed.
An oxide film may be interposed between the conductive layers 14.

[0032] Next, as shown in FIG. 8, the conductive layer 14 and the sheet
The silicon nitride film 13 and the silicon oxide film 12 are patterned. Next, a silicon oxide film 15 is formed, and the conductive layer 14, the silicon nitride film 13,
The side composed of the silicon oxide film on the side of the silicon oxide film 12
A wall 15 is formed.

Next, as shown in FIG. 9, the conductive layer 6 and the conductive layer 14 are etched using the side wall 15 as a mask. At this time, one end of the first conductive layer 6 is, flash memory after
The patterning is performed so as to cover the region to be the channel of the recell part .

Next, as shown in FIG. 10, after removing the side wall 15, a select gate oxide film 5 made of a silicon oxide film and an interpoly insulating film 8 are formed. At the same time, a silicon oxide film and a silicon nitride
An interpoly insulating film 7 made of a film and a silicon oxide film is formed. At this time, the method of forming the silicon oxide film may be thermal oxidation, CVD, or a combination of the two.

[0035] Next, as shown in FIG. 11, a conductive layer 9 serving as a control gate, a conductive layer 9 and the interpoly dielectric
The film 7, the interpoly insulating film 8, and the conductive layer 6 are simultaneously patterned to form the control gate 9 and the floating gate 6.

Next, as shown in FIG. 12, arsenic ions are implanted using the control gate 9 as a mask to form a source 11 and a drain 10.

Another manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 13, after forming an element isolation insulating film on the main surface of the semiconductor substrate 1, a silicon oxide film 4 serving as a tunnel oxide film and a conductive layer 6 serving as a floating gate are formed. Then, conductive
After phosphorus ions are implanted into the conductive layer 6, an interpoly insulating film 7 is formed. The interpoly insulating film 7 has an ONO structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0038] Next, as shown in FIG. 14, interpoly insulating film 7
Then, the conductive layer 6 is patterned. At this time, the conductive layer 6
Of the flash memory cell section later
Patterning so as to cover the region to be formed. Next, poly
The resist 16 used for patterning the inter-insulating film 7 and the conductive layer 6 is thinned by, for example, about 300 ° by plasma ashing.

Next, as shown in FIG. 15, anisotropic etching is performed using the resist 16 as a mask to pattern the interpoly insulating film 7. Next, after removing the resist 16,
A silicon oxide film is formed. Thus, the end portions of the side and top surfaces of the conductive layer 6 in contact with the poly insulating film 7, interpoly
An insulating film 8 is formed to serve as a channel for the select transistor portion.
A selection gate oxide film 5 is formed on that region. The Siri
The method of forming the con oxide film may be thermal oxidation or CVD, or a combination of the two.

[0040] Next, as shown in FIG. 16, a conductive layer 9 serving as a control gate, a conductive layer 9 and the interpoly dielectric
The film 7, the interpoly insulating film 8, and the conductive layer 6 are simultaneously patterned to form the control gate 9 and the floating gate 6.

Next, as shown in FIG. 17, arsenic ions are implanted using the control gate 9 as a mask to form a source 11 and a drain 10.

[0042]

As described above, according to the present invention, it is possible to obtain a nonvolatile semiconductor memory device having both high-speed reading and good holding characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view showing Embodiment 1 of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing Embodiment 2 of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing method according to Embodiment 2 of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing a manufacturing method according to Embodiment 2 of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing a manufacturing method according to Embodiment 2 of the present invention in the order of steps.

FIG. 10 is a sectional view illustrating a manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 11 is a cross-sectional view showing a manufacturing method according to Embodiment 2 of the present invention in the order of steps.

FIG. 12 is a sectional view illustrating the manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view illustrating another manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing another manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view showing another manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating another manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating another manufacturing method according to the second embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view showing a conventional split gate flash memory.

FIG. 19 is a sectional view showing a conventional stack type flash memory.

FIG. 20 is a cross-sectional view showing a method for manufacturing a conventional split gate flash memory in the order of steps.

FIG. 21 is a sectional view illustrating a method of manufacturing a conventional split gate flash memory in the order of steps.

FIG. 22 is a cross-sectional view showing a method of manufacturing a conventional split gate flash memory in the order of steps.

FIG. 23 is a sectional view illustrating a method of manufacturing a conventional split gate flash memory in the order of steps.

FIG. 24 is a cross-sectional view illustrating a method for manufacturing a conventional split gate flash memory in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Flash memory cell part channel 3 Select transistor part channel 4 Tunnel insulating film 5 Select gate insulating film 6 Floating gate 7 Interpoly insulating film 8 Interpoly insulating film 9 Control gate 10 Drain 11 Source 12 Silicon oxide film 13 Silicon nitride Film 14 Conductive layer 15 Side wall 16 Resist 17 Silicon oxide film 18 Silicon oxide film 19 Silicon nitride film 20 Silicon oxide film

Continuation of front page (56) References JP-A-6-196714 (JP, A) JP-A-61-198682 (JP, A) JP-A-63-177567 (JP, A) JP-A-8-97304 (JP, A) JP-A-2-27773 (JP, A) JP-A-4-14880 (JP, A) JP-A-9-129759 (JP, A) JP-A-6-120514 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] A first conductive type source and a drain formed on a main surface of a first conductive type semiconductor substrate; and a flash formed between the source and the drain.
Memory cell section channel region and select transistor section channel.
A channel region; a tunnel insulating film formed on the flash memory cell unit channel region; a floating gate formed on the tunnel insulating film; and a second gate formed on a part of an upper surface of the floating gate .
An insulating film , a second insulating film formed on a part of an upper surface of the floating gate and a part of a side surface of the floating gate, and a selection formed on a channel region of the selection transistor unit. A gate insulating film; and a control gate formed over the first insulating film, the second insulating film, and the select gate insulating film, and a first side surface and a second side of the floating gate.
And a third side surface are covered by a control gate via the second insulating film . A fourth side surface of the floating gate is not covered by the control gate, and an upper surface of the floating gate is provided. An end portion of the floating gate, which is in contact with the first side surface, the second side surface, and the third side surface, is covered with the second insulating film , and the first insulating film is formed of silicon. A three-layer structure including an oxide film, a silicon nitride film, and a silicon oxide film, wherein the first insulating film is in contact with the second insulating film on an upper surface of the floating gate; Semiconductor storage device. A step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; a step of forming a first conductive layer serving as a floating gate on the tunnel insulating film; on the conductive layer, a first silicon oxide film and silicon
Forming a con nitride film and the second conductive layer in this order, and patterning the first silicon oxide film and the silicon nitride film and <br/> the second conductive layer, the first silicon The side of the oxide film and the silicon nitride
Silicon on the side surface of the oxide film and the side surface of the second conductive layer.
Forming a sidewall made of an oxide film ; and using the sidewall as a mask, the first conductive layer and the second conductive layer .
Etching the conductive layer , removing the side wall, forming a select gate insulating film on the channel region of the select transistor section, and forming a side surface of the first conductive layer and the first conductive layer. A step of forming a first insulating film on a part of the upper surface; a step of forming a second insulating film made of a silicon oxide film on the silicon nitride film; and a control gate on the second insulating film Third
Forming a conductive layer , the third conductive layer, the second insulating film, and the first
Patterning an insulating film and said first conductive layer to form said floating gate and said control gate. 3. A step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; a step of forming a first conductive layer serving as a floating gate on the tunnel insulating film; Forming a first insulating film having a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the conductive layer, and applying a resist on the first insulating film A step of patterning the resist; a step of patterning the first conductive layer and the first layer using the resist as a mask;
Patterning the insulating film , ashing the resist to thin it, etching the first insulating film and the tunnel insulating film using the resist as a mask, and stripping the resist. , selection gate insulating film and on the selection transistor section channel, forming a second insulating film on the side surface of a part and the first conductive layer of the upper surface of the first conductive layer, the first insulating On the film , a second control gate
Forming a second conductive layer, the second conductive layer, the first insulating film, and the second
Patterning an insulating film and said first conductive layer to form said floating gate and said control gate. 4. A step of forming a tunnel insulating film on a main surface of a semiconductor substrate of a first conductivity type; a step of forming a first conductive layer serving as a floating gate on the tunnel insulating film; A first silicon oxide film and a silicon
Forming a silicon nitride film, a second silicon oxide film, and a second conductive layer sequentially; and forming the first silicon oxide film, the silicon nitride film, the second silicon oxide film, and the second conductive layer. Patterning a side surface of the first silicon oxide film and the silicon nitride film.
A side surface of the film and a side surface of the second silicon oxide film ;
Forming a side wall made of a silicon oxide film on a side surface of the second conductive layer; and using the side wall as a mask, the first conductive layer and the second side.
Etching the conductive layer , removing the side wall and the second silicon oxide film, forming a select gate insulating film on the select transistor unit channel region, and side surfaces of the first conductive layer. A step of forming a first insulating film on a part of the upper surface of the first conductive layer; a step of forming a second insulating film made of a silicon oxide film on the silicon nitride film ; Third control gate on insulating film
Forming a conductive layer , the third conductive layer, the second insulating film, and the first
Patterning an insulating film and said first conductive layer to form said floating gate and said control gate.