JP2002158299A - Semiconductor storage device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress drop in a current drive power which follows drop in the diffusion layer concentration in a micro flush memory for improved breakdown strength and driving power while preventing writing error. SOLUTION: A floating gate 22 is formed on a p-type silicon substrate 10 through a first gate insulating film 21, on which a control gate 24 is formed through a second gate insulating film 23. An n-type source region 15 and a drain region 16 are formed on the substrate 10 with a gate part in between. The formation parts of the floating gate 22 and control fate 24 are lower than the substrate surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a two-layer gate structure in which a floating gate (floating gate) and a control gate (control gate) are stacked, and which can be electrically rewritten and erased. And its manufacturing method.

[0002]

2. Description of the Related Art In recent years, demand for flash memories has been rapidly expanding with the rapid expansion of the market for recording media such as digital cameras and portable audio equipment such as mobile phones. At present, the demands for smaller, lighter, and more sophisticated devices are becoming more and more strict, and accordingly, the finerness, higher integration, lower power supply voltage, and higher reliability of flash memories are increasingly required. It has become. Above all, the demand for the NAND flash memory is rapidly increasing due to its high speed and easy integration.

In a NAND flash memory,
Since the power supply voltage is higher than that of a normal MOS transistor, improvement in reliability is indispensable. For example, it is important from the viewpoint of the reliability of the flash memory to suppress erroneous writing during standby and to improve the breakdown voltage of the select gate transistor.

As a measure for improving reliability, a source
It has been practiced to lower the concentration of the drain diffusion layer. Decreasing the source / drain diffusion layer concentration causes a decrease in drain current driving force due to an increase in diffusion layer resistance. However, in the fine flash memory, even if the drain current driving force is slightly reduced, the improvement in the withstand voltage and the suppression of the erroneous writing result in the improvement of the overall device characteristics. For this reason, reducing the source / drain diffusion layer concentration is one of the most effective means at present.

[0005] A remarkable decrease in the concentration of the diffusion layer causes another problem. In a NAND flash memory, by applying a positive high voltage to a control gate, electrons are written to a floating gate using a FN (Fower-Nordheim) tunnel. In this case, a negative voltage is effectively applied to the floating gate by the injected electrons.

Since an overlap capacitance exists between the floating gate and the surface of the source / drain diffusion layer, the negative voltage of the FG is transmitted to the surface of the diffusion layer by capacitive coupling. Since the diffusion layer is formed of the donor, the surface of the diffusion layer is depleted. The effect of such a depletion layer is almost negligible because the concentration of a normal source / drain diffusion layer is very high. However, since the concentration of the diffusion layer is low in a flash memory for the above-described reason, the extension of such a depletion layer is Becomes larger.

When the gate length is long, the effect of the parasitic resistance due to the depletion of the diffusion layer surface is relatively small because the channel resistance is much larger. However, in the case of a fine flash memory, the gate length is short. The channel resistance is reduced, and the parasitic resistance due to the depletion of the diffusion layer surface is relatively large. For this reason, a decrease in the source / drain diffusion layer concentration results in a decrease in the drain current.

[0008]

As described above, conventionally, the NA
In the ND type flash memory, it is necessary to lower the concentration of the diffusion layer from the viewpoint of improving the breakdown voltage and preventing erroneous writing. However, there is a problem that a decrease in the concentration of the diffusion layer causes an increase in parasitic resistance due to depletion of the surface of the diffusion layer.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to suppress a reduction in current driving force due to a reduction in diffusion layer concentration which becomes more and more remarkable in a fine flash memory and the like. It is an object of the present invention to provide a semiconductor memory device capable of improving the breakdown voltage, preventing erroneous writing, and improving the driving force, and a method of manufacturing the same.

[0010]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, according to the present invention, a floating gate and a control gate are sequentially formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and a second conductivity type is formed on a surface portion of the semiconductor substrate with the floating gate interposed therebetween. In a nonvolatile semiconductor memory device in which a source and a drain region made of an impurity diffusion layer are formed, a portion where the floating gate and the control gate are formed is such that the lower surface of the floating gate is closer to the inside of the substrate than the surface of the substrate. It is provided so that it may be located.

Here, preferred embodiments of the present invention include the following. (1) A groove is formed in the substrate, and the lower part of the floating gate is buried in the groove. (2) The shape of the floating gate is a rectangular parallelepiped. (3) The source and drain regions have a region overlapping with the gate insulating film. (4) A first conductivity type impurity diffusion region is provided in a region of the source and drain regions adjacent to the side of the floating gate.

According to the present invention, in a method of manufacturing a nonvolatile semiconductor memory device having a two-layer gate structure, a dummy gate electrode is formed on a semiconductor substrate of a first conductivity type, and the second gate electrode is formed using the dummy gate electrode as a mask. Forming source and drain regions of a mold, and, after depositing an interlayer insulating film on the substrate and the dummy gate electrode, etching back the interlayer insulating film to planarize the surface and expose the dummy gate electrode. Forming a groove by etching the substrate using the interlayer insulating film as a mask after removing the dummy gate electrode, and forming a floating gate in the groove via a first gate insulating film. Forming a control gate on the floating gate via a second gate insulating film; and removing the interlayer insulating film. And wherein the Mukoto.

(Operation) According to the present invention, since the lower surface of the floating gate is provided below the surface of the substrate, the channel is formed at a position distant from the substrate surface. For this reason, when the concentration of the source / drain diffusion layers is low and a depletion layer is generated on the surface of the drain region as in a fine flash memory, a current is injected into the drain region avoiding the depletion layer. Thus, it is possible to suppress a decrease in drain current due to parasitic resistance due to depletion of the diffusion layer. Therefore, it is possible to suppress a decrease in current driving force due to a decrease in the concentration of the diffusion layer, which becomes more and more remarkable in a fine flash memory and the like, and it is possible to improve the withstand voltage, prevent erroneous writing, and improve the driving force.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 14 is a cross-sectional view showing an element structure of the nonvolatile semiconductor memory device according to the embodiment. FIG. 1 shows the configuration of one cell portion, but this cell structure can be applied to various types of NAND, NOR, OR, and AND type memory cell units.

A groove is formed on the surface of the p-type silicon substrate 10, a first gate insulating film 21 is buried in the bottom of the groove, and a floating gate 22 is formed on the gate insulating film 21. On the floating gate 22, a control gate 24 is formed via a second gate insulating film 23. Floating gate 22
The control gate 24 is covered with an insulating film 25 for covering.

Further, an n-type source region 15 and an n-type drain region 16 are formed so as to have a region partially overlapping with the gate insulating film 21 located on the bottom surface of the floating gate 22 embedded in the silicon substrate 10. Have been. In the figure, reference numeral 11 denotes an insulating film formed on the source region 15 and the drain region 16, and reference numeral 27 denotes a side wall insulating film formed on both sides of the gate portion.

In the semiconductor memory device thus configured, the floating gate 22 and the gate insulating film 2
By embedding 1 in silicon substrate 10, a channel is formed at a position away from the substrate surface. Therefore, when a depletion layer is generated on the surface of the drain region 16, a current is injected into the drain region avoiding the depletion layer, so that a decrease in drain current due to parasitic resistance due to the depletion layer is suppressed. It becomes possible.

How far from the substrate surface actually is
Whether the floating gate 22 should be buried in
It is determined by the degree of depletion on the surface of the drain region. Immediately
That is, the drain is deeper than the depletion layer width on the drain region surface.
The loading gate 22 may be embedded. example
If the negative voltage generated for some reason
Coupling between the floating gate 22 and the drain region 16
As a result, V _oxProduces a voltage drop of magnitude
Let's say

In the following, the unit elementary charge is q, the drain diffusion layer concentration is N _A , the thickness of the insulating film 11 is t _ox , the dielectric constant of silicon is ε _s , the dielectric constant of the insulating film 11 is ε _ox , It is assumed that the capacitance per unit area of No. 11 is C _ox , and the width of a depletion layer on the drain region surface generated by V _ox is x _d . Then, there is a relationship represented by the following equation.

[0022] _{V ox = qN A x d /} C ox + qN A x d 2 / 2ε s ... (1) here, it is a _{C ox = ε ox / t ox} ... (2). Estimating the depletion layer width from a typical voltage drop _Vox results in about 60 nm.

However, to what extent the floating gate 22 should be embedded away from the substrate surface,
This is actually a design matter, and depends on how much the parasitic resistance on the surface of the drain region is allowed in the design. In reality, at most the floating gate 22
It may be embedded up to the length of about.

Next, an example of a method for manufacturing the semiconductor memory device of the present embodiment will be described with reference to FIG.

First, as shown in FIG. 2A, a thin insulating film 11 is formed on a p-type silicon substrate 10, and a dummy gate electrode 12 to be removed later is formed in a region where a gate electrode is to be formed.
To form Specifically, after depositing a polysilicon film on the entire surface of the insulating film 11, a resist pattern is formed by lithography, and the polysilicon film is selectively etched using the resist pattern as a mask to form the dummy gate electrode 12. I do. This dummy gate electrode 12
Is a rectangular parallelepiped.

Next, as shown in FIG. 2B, after a sidewall insulating film 14 is formed of a nitride film by a well-known technique of leaving a sidewall, an n-type source is formed using the dummy gate 12 and the sidewall insulating film 14 as a mask. The region 15 and the drain region 16 are formed by ion implantation and high-temperature heat treatment. Subsequently, FIG.
As shown in FIG. 1C, after an interlayer insulating film 17 is deposited on the entire surface, the interlayer insulating film 17 is etched back using CMP (Chemical Mechanical Polishing), and the dummy gate 12 is etched.
Expose the surface.

Next, as shown in FIG. 2D, after the dummy gate 12 is removed by etching, the RIE (Re
The insulating film 11 and the silicon substrate 10 are etched by active ion etching to form a groove on the substrate surface. Subsequently, as shown in FIG. 2E, the gate insulating film 2 is formed in the trench.
Form one.

Next, as shown in FIG. 2F, a floating gate 22 is formed by depositing a polysilicon layer on the first gate insulating film 21, and then a second gate insulating film 23 is formed. After that, a polysilicon layer is further deposited to form the control gate 24. Here, since the shape of the dummy gate electrode 12 formed earlier is a rectangular parallelepiped, the shape of the floating gate 22 is also a rectangular parallelepiped.

Next, the interlayer insulating film 17 and the side wall insulating film 1
4 is removed, the floating gate 22 and the control gate 24 are oxidized to form an oxide film 25, and a new sidewall nitride film 27 is formed.
The structure shown in (g) is obtained.

A structure similar to the structure described above has been proposed in some known examples. Here, the differences between the three known examples and the structure proposed in the first embodiment of the present invention will be described. In addition, 30 in FIGS.
1 denotes a first gate insulating film, 32 denotes a floating gate, 33 denotes a second gate insulating film, 34 denotes a control gate, 35 denotes a source region, and 36 denotes a drain region.

Japanese Patent Application Laid-Open No. 2000-77632 proposes a structure as shown in FIG. In this structure, electrons are injected into the floating gate 32 using the electric field concentration at the corners (2) and (3), and electrons are extracted from the floating gate using the electric field concentration at the corner (1). . It is an advantage of this structure that writing and erasing voltages can be reduced by utilizing the electric field concentration at the corner.

However, this structure is different from the first embodiment of the present invention in the following points. First, in the above structure, since the floating gate 32 is formed in the trench, the floating gate 32 has a region overlapping the source / drain regions 35 and 36 on the substrate surface. However, according to the manufacturing method of the first embodiment of the present invention, the floating gate 22 does not have a region overlapping the source / drain regions 15 and 16 on the substrate surface.

Although the source region 35 does not overlap with the bottom surface of the gate insulating film 31 in the structure of FIG. 3, the source / drain region 1 in the first embodiment of the present invention.
Both 5 and 16 have a structure that partially overlaps the bottom surface of the gate insulating film 21. Therefore, in the structure of FIG.
Since no channel is formed immediately below, there is almost no effect on the problem to be solved by the present invention.

Next, Japanese Patent Laying-Open No. 6-85274 proposes a structure as shown in FIG. In this structure, the floating gate 32 and the control gate 34 are made concave so that the time required for programming and erasing with a high degree of capacitive coupling is reduced.

As can be seen from FIG. 4, this structure is not only clearly different from the first embodiment of the present invention, but also
There is a problem that the effect is not expected when miniaturized. That is, when miniaturized, it is almost impossible to precisely process the floating gate and the control gate as shown in FIG. Therefore, the structure shown in FIG. 4 has little effect as a structure for achieving the object of the present invention.

Next, Japanese Patent Laying-Open No. 9-32154 proposes a structure as shown in FIG. As can be seen from FIG. 5, in this structure, the source region 35 does not overlap with the floating gate 32. Also,
A selection gate is formed on the control gate 34 via an insulating film. As described above, the structure shown in FIG. 5 is clearly different from the first embodiment of the present invention. In addition, the structure is not suitable for miniaturization because the size in the lateral direction increases. Therefore, the structure shown in FIG. 5 has little effect as a structure for achieving the object of the present invention.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing an element structure of the nonvolatile semiconductor memory device according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The basic structure is the same as that of FIG.
In the present embodiment, in addition to this, p-type impurity regions 65 and 66 are provided inside the source region 15 and the drain region 16 at positions immediately below the insulating film 11 and adjacent to the sides of the floating gate 22. .

The semiconductor memory device according to the second embodiment includes:
The present embodiment has the same effects as those of the semiconductor memory device of the first embodiment.
That is, in the second embodiment, in the structure in which the floating gate 22 and the gate insulating film 21 are embedded in the silicon substrate 10, the p-type impurity regions 65 and 66 are further provided, so that the distance from the substrate surface is increased. The channel formed at the position is further prevented from approaching the substrate surface. For this reason, it is possible to more effectively suppress a decrease in drain current due to the parasitic resistance due to the depletion layer.

Next, an example of a method of manufacturing the semiconductor memory device according to the second embodiment will be described with reference to FIG. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as shown in FIG. 7A, a p-type impurity region 60 is formed on the surface of the p-type silicon substrate 10 in a range wider than a region where a gate electrode is to be formed. continue,
As in the first embodiment, an insulating film 11 is formed, and a dummy gate electrode 12 to be removed later is formed in a region where a gate electrode is to be formed.

Then, similarly to the first embodiment, as shown in FIG. 7B, the side wall insulating film 14 and the source region 1 are formed.
5 and the drain region 16 are formed, and then, as shown in FIG. 7C, an interlayer insulating film 17 is deposited to planarize the surface, exposing the surface of the dummy gate 12.

Next, in the same manner as in the first embodiment, as shown in FIG. 7D, after removing the dummy gate 12, the insulating film 11 and the silicon substrate 10 are etched to form a groove. As shown in FIG. 7E, a first gate insulating film 21 is formed in the trench.

Next, as shown in FIG. 7F, a floating gate 22 is formed on the first gate insulating film 21 and a second gate insulating film 23 is formed in the same manner as in the first embodiment. Forming a control gate 24 via
Subsequently, after removing the interlayer insulating film 17 and the side wall insulating film 14, the floating gate 22 and the control gate 24 are oxidized to form an oxide film 25, and further, the side wall nitride film 2 is formed.
By forming the structure 7, the structure shown in FIG.

The present invention is not limited to the above embodiments. In the embodiment, both the source and drain regions have a structure in which both the source and drain regions partially overlap the bottom surface of the first gate insulating film. However, the source and drain regions do not necessarily have to overlap, and the source and drain regions are provided slightly outside the gate portion. You may. Further, the material and film thickness of each part can be appropriately changed according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0046]

As described above in detail, according to the present invention, in a nonvolatile semiconductor memory device having a two-layer gate structure in which a floating gate and a control gate are stacked, the floating gate and the control gate are formed from the surface of the semiconductor substrate. By forming it at a lower position (inside the substrate), it is possible to suppress a decrease in the current driving force due to a decrease in the concentration of the diffusion layer, thereby improving the withstand voltage, preventing erroneous writing, and improving the driving force.

[Brief description of the drawings]

FIG. 1 is an element structure sectional view showing a semiconductor memory device according to a first embodiment.

FIG. 2 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment;

FIG. 3 is a sectional view of an element structure showing a semiconductor memory device described in JP-A-2000-77632.

FIG. 4 is a sectional view of an element structure showing a semiconductor memory device described in JP-A-6-85274.

FIG. 5 is a sectional view of an element structure showing a semiconductor memory device described in JP-A-9-32154.

FIG. 6 is an element structure sectional view showing a nonvolatile semiconductor memory device according to a second embodiment.

FIG. 7 is a sectional view showing a manufacturing process of the semiconductor memory device according to the second embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11, 25 ... Insulating film 12 ... Dummy gate 14, 27 ... Side wall insulating film 15 ... Source region 16 ... Drain region 17 ... Interlayer insulating film 21 ... First gate insulating film 22 ... Floating gate 23 ... Second Gate insulating film 24 ... Control gate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA21 AA31 AB08 AD15 AD21 AD52 AD53 AE08 5F083 EP13 EP14 EP15 EP23 EP61 EP76 EP77 EP78 EP79 ER22 GA15 PR40 5F101 BA03 BA13 BB05 BD05 BD13 BD33 BD34 BE07

Claims (6)

[Claims] A floating gate and a control gate are sequentially formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and an impurity diffusion layer of a second conductivity type is formed on a surface portion of the semiconductor substrate with the floating gate interposed therebetween. A non-volatile semiconductor memory device having a source and a drain region formed of a floating gate and a control gate, wherein a lower surface of the floating gate is located closer to the inside of the substrate than a surface of the substrate. A semiconductor memory device provided in a semiconductor device. 2. The semiconductor memory device according to claim 1, wherein a groove is formed in said substrate, and a lower portion of said floating gate is buried in said groove. 3. The semiconductor memory device according to claim 1, wherein said floating gate has a rectangular parallelepiped shape. 4. The semiconductor memory device according to claim 3, wherein said source and drain regions have a region overlapping with said gate insulating film. 5. The semiconductor memory device according to claim 4, further comprising an impurity diffusion region of a first conductivity type in a region of said source and drain regions adjacent to a side of said floating gate. 6. A step of forming a dummy gate electrode on a semiconductor substrate of a first conductivity type and forming source and drain regions of a second conductivity type by using the dummy gate electrode as a mask; After depositing the interlayer insulating film, etching back the interlayer insulating film to flatten the surface and expose the dummy gate electrode, and after removing the dummy gate electrode, removing the substrate using the interlayer insulating film as a mask. Forming a groove by etching, forming a floating gate in the groove via a first gate insulating film, and forming a control gate on the floating gate via a second gate insulating film And a step of removing the interlayer insulating film.