KR100663608B1 - Method for manufacturing cell of flash memory device - Google Patents

Abstract

The present invention relates to a cell manufacturing method of a flash memory device capable of reducing the area of a memory cell by preventing misalignment between the floating gate and the active region. To this end, the present invention relates to a substrate defined as an active region and a field region. Providing a trench, sequentially depositing a pad oxide film and a pad nitride film on the substrate, etching the pad nitride film, the pad oxide film, and a portion of the substrate to form a trench in the field region; Forming an isolation layer to fill the trench, removing the pad nitride layer and the pad oxide layer to protrude a portion of the isolation layer, forming a tunnel oxide layer in the active region, and covering the tunnel oxide layer Depositing a material for the floating gate to separate the protruding device Etching the floating gate material to form a floating gate through a planarization process using the device isolation layer as an etch stop layer so as to be separated by the etching process, and sequentially forming a dielectric film and a control gate on the etched floating material. It provides a cell manufacturing method of a flash memory device comprising the step of forming.

Flash memory cells, planarization, floating gates, active areas, auto alignment.

Description

Cell manufacturing method of flash memory device {METHOD FOR MANUFACTURING CELL OF FLASH MEMORY DEVICE}             

1 is an equivalent circuit diagram showing a cell array of a typical flash memory device.

FIG. 2 is a plan view of a portion of the cell array shown in FIG. 1; FIG.

3A to 3C are cross-sectional views taken along the line AA ′ of FIG. 2.

4 is a plan view illustrating a cell array of a flash memory device according to a preferred embodiment of the present invention.

5A through 5F are cross-sectional views illustrating a method of manufacturing a cell of a flash memory device according to a preferred embodiment of the present invention along the AA ′ cut line shown in FIG. 4.

<Explanation of symbols for main parts of drawing>

MC0, MC1, MC2, MC3: memory cells

10, 110: semiconductor substrate 11, 111: pad oxide film

12, 112: pad nitride film 13, 114: liner oxide film

14, 115: device isolation layer 15, 116: tunnel oxide film

16, 117: polysilicon layer 16a, 117a: floating gate

17: hard mask pattern 18, 118: insulating film

19, 119: control gate 113: trench

B: field area C: active area

The present invention relates to a method for manufacturing a cell of a flash memory device, and more particularly, to a method for manufacturing a cell of a flash memory device using a shallow trench isolation (STI) process.

Recently, the demand for flash memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

In general, cells of flash memory devices have a stacked gate structure that is advantageous for high integration. The stacked gate structure includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate stacked on a semiconductor substrate.

Meanwhile, a program operation in a flash memory device is performed by F-N tunneling (Fowler-nordheim tunneling) method and hot electron injection method. The F-N tunneling method is a method in which a program operation is performed by applying a high electric field to a tunnel oxide film by injecting electrons into a floating gate from a semiconductor substrate. The hot electron injection method is a method in which a hot electron generated in a channel region near a drain is injected into a floating gate to perform a program operation. Meanwhile, an erase operation of the flash memory device is performed by releasing electrons injected into the floating gate into a semiconductor substrate or a source through a program operation.

1 is an equivalent circuit diagram illustrating a cell array of a flash memory device that is generally known. Here, a NOR type flash memory device is shown for convenience of description.

As shown in FIG. 1, as an example, a cell array of a quinoa flash memory device is composed of a plurality of memory cells MC0 to MC3. In this case, the control gate G of the memory cell is commonly connected to each row by the word line WL, and the source S or the drain D is commonly connected to each column by the bit line BL. Through this configuration, the memory cells MC0 to MC3 are selected by bias voltages applied to the word line WL and the bit line WL.

On the other hand, in the manufacturing process of a memory cell of a flash memory device, a shallow trench isolation (STI) process is widely used as a device isolation process for separating devices.

FIG. 2 is a plan view of a cell of a typical flash memory device formed using such an STI process, and FIGS. 3A to 3C illustrate a flash memory according to the prior art in a state cut along a cutting line of AA ′ shown in FIG. 2. Sectional drawing for demonstrating the manufacturing method of the cell of an element.

First, as illustrated in FIG. 3A, the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the semiconductor substrate 10 (hereinafter, referred to as a substrate), and then the substrate 10 of the field region B is deposited. The pad nitride film 12, the pad oxide film 11, and the substrate 10 are sequentially etched so that a part of the etch is etched. This forms a trench, which is not shown. Then, the liner oxide film 13 is deposited along the stepped portion of the resultant top including the trench. Then, the HDP (High Density Isolation) oxide film 14 is formed on the liner oxide film 13 to fill the trench.

Subsequently, as shown in FIG. 3B, the pad nitride film 12 and the pad oxide film 11 are sequentially removed to form an isolation layer 14 isolated by a trench. Then, the tunnel oxide film 15 is formed on the substrate 10 of the active region C. After that, a floating gate polysilicon layer 16 is deposited on the tunnel oxide layer 15, and then a gate pattern mask 17 is formed thereon. In this case, in consideration of misalignment of the gate pattern mask 17, a gap between the gate pattern mask 17 is generally narrowed.

Subsequently, as illustrated in FIG. 3C, an etching process using the gate pattern mask 17 is performed to etch the polysilicon film 16 (see FIG. 3B). As a result, as illustrated in FIG. 2, the floating gate 16a is defined to overlap the edge of the device isolation layer 14 and have a width wider than that of the active region C. Referring to FIG. Then, the dielectric film 18 and the control gate 19 are sequentially formed on the floating gate 16a to form a gate electrode.

As described above, in the cell manufacturing method of a flash memory device according to the related art, the floating gate 16a is formed by performing a photolithography process after forming the device isolation layer 14. As a result, misalignment may occur between the floating gate 16a and the substrate 10 of the active region C during the photolithography process. Therefore, since the floating gate must be formed in consideration of the misalignment margin, the width of the floating gate 16a needs to be widened. Since the design rule for the minimum spacing between the floating gate 16a and the design rule for the overlap between the floating gate 16a and the device isolation layer 14 should be considered, the spacing between the substrates in the active region is minimized. There is a problem in that the area of the memory cell is increased because it can be implemented larger than the design rule.

Accordingly, the present invention has been proposed to solve the above-described problems of the prior art, and has been proposed in the flash memory device, which can reduce the area of the memory cell by preventing misalignment between the floating gate and the active region during the cell manufacturing process of the flash memory device. It is an object of the present invention to provide a method for manufacturing a cell.

According to an aspect of the present invention, there is provided a method including: providing a substrate defined by an active region and a field region; sequentially depositing a pad oxide film and a pad nitride film on the substrate; Etching a portion of the nitride film, the pad oxide film, and the substrate to form a trench in the field region, forming a device isolation layer to fill the trench, and removing the pad nitride film and the pad oxide film to remove the device isolation film. Protruding a portion of the semiconductor substrate; forming a tunnel oxide layer in the active region; depositing a floating gate material to cover the tunnel oxide layer; and etching the device isolation layer to be separated by the protruding element isolation layer. The floating gate material is etched through a planarization process using a stop film W forming the floating gate, there is provided a method of manufacturing a flash memory cell device, comprising forming a dielectric film and a control gate on top for the etching the floating gate material sequentially.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 4 is a plan view of a cell array of a flash memory device according to a preferred embodiment of the present invention, and FIGS. 5A to 5F illustrate a flash according to a preferred embodiment of the present invention along the cutting line AA ′ of FIG. 4. FIG. 1 is a cross-sectional view illustrating a cell manufacturing method of a memory device.

First, as illustrated in FIGS. 4 and 5A, the pad oxide layer 111 and the pad nitride layer 112 are sequentially deposited on the substrate 110. In this case, the pad oxide film 111 is formed through an oxidation process using a dry oxidation method or a wet oxidation method for crystal defects and surface treatment of the upper surface of the substrate 110. In addition, it functions as a buffer oxide film that protects the substrate 110 from stress applied during the subsequent deposition process of the pad nitride film 112. On the other hand, the pad nitride film 112 is formed relatively thick by performing a deposition process using a CVD (Chemical Vapor Deposition) method.

Subsequently, a photoresist (not shown) is coated on the pad nitride layer 112, and then an exposure process and a development process using a photo mask are sequentially performed to form a photoresist pattern (not shown). At this time, the reason for using the photoresist is that it is possible to control the slope (slope) by the formation of the polymer (polymer) in the subsequent trench etching process.

Next, an etching process using a photoresist pattern as an etching mask is performed to form the trench 113 in the field region B of the substrate 110.

Subsequently, the photoresist pattern may be removed through a strip process and then cleaned.

Subsequently, as shown in FIG. 5B, the liner oxide film 114 is deposited along the step of the entire structure in which the trench 113 (see FIG. 5A) is formed.

Subsequently, a high density plasma (HDP) oxide film 115 is deposited on the entire structure so that the trench 113 is buried.

Subsequently, the chemical mechanical polishing (CMP) process is performed to planarize the HDP oxide film 115. As a result, an isolation layer 115 is formed in the trench.

Subsequently, as shown in FIG. 5C, the pad nitride layer 112 and the pad oxide layer 111 are sequentially removed so that the device isolation layer 115 protrudes from the surface of the substrate 110 in the active region C. In this case, the pad nitride layer 112 is removed by performing a wet etching process using phosphoric acid, and the pad oxide layer 111 is removed by performing a cleaning process using a diluted HF (DHF) or a buffered oxide etch (BOE) solution.

Subsequently, as shown in FIG. 5D, an oxidation process is performed to form the tunnel oxide film 116 on the surface of the substrate 110 in the active region C. At this time, the oxidation process proceeds in a dry or wet manner.

Subsequently, a polysilicon layer 117 for floating gate is deposited on the entire structure including the tunnel oxide layer 116.

Subsequently, as shown in FIG. 5E, the floating gate 117a is electrically separated by the device isolation film 115 by performing a CMP process using the device isolation film 115 as a planarization stop film to planarize the polysilicon film 117. ). In this case, the planarization process is performed without a mask to self-align the floating gate 117a with the active region C. As shown in FIG. 4, the floating gate 117a has the same width as the active region C. FIG. Is formed.

Subsequently, as shown in FIGS. 4 and 5F, a wet etching process may be performed to recess the device isolation layer 115 and the liner oxide layer 114 to a predetermined depth to form a groove (not shown). As a result, a part of the sidewall of the floating gate 117a is exposed. Therefore, since the control gate 119 to be formed through the subsequent process is formed by filling the groove, the coupling ratio with the floating gate 117a can be increased.

Subsequently, the dielectric film 118 is deposited along the step of the upper part of the resultant portion where the side of the floating gate 117a is exposed, and then the polysilicon film 119 for the control gate is deposited thereon. Thereafter, an etching process is performed to define the control gate 119. At this time, the dielectric film 118 is formed in an ONO (Oxide / Nitride / Oxide) structure.

Thereafter, a source / drain region (not shown) is formed in the active region exposed to both sides of the control gate 119 through a general process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the cell fabrication process of a flash memory device, an etching process for defining a floating gate is performed by a planarization process to self-align the floating gate with an active region, thereby forming a floating gate and an active region. Misalignment can be prevented. Therefore, the integration degree can be improved by reducing the area of the memory cell.

Claims (5)

Providing a substrate defined by an active region and a field region; Sequentially depositing a pad oxide film and a pad nitride film on the substrate; Etching a portion of the pad nitride film, the pad oxide film, and the substrate to form a trench in the field region; Forming an isolation layer to fill the trench; Protruding a portion of the device isolation layer by removing the pad nitride layer and the pad oxide layer; Forming a tunnel oxide film in the active region; Depositing a material for the floating gate to cover the tunnel oxide layer; Forming a floating gate by etching the floating gate material through a planarization process using the device isolation layer as an etch stop layer so as to be separated by the protruding device isolation layer; And Sequentially forming a dielectric film and a control gate on the etched floating gate material; Cell manufacturing method of a flash memory device comprising a. The method of claim 1, And the planarization step is a CMP step. The method of claim 1, And forming a liner oxide film along a step inside the trench after forming the trench. The method of claim 1, And recessing the device isolation layer to a predetermined depth after forming the floating gate. The method of claim 1, And the floating gate is self-aligned with the active region by the device isolation layer.

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