KR20030044146A - Method of manufacturing a flash memory cell - Google Patents
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- KR20030044146A KR20030044146A KR1020010074736A KR20010074736A KR20030044146A KR 20030044146 A KR20030044146 A KR 20030044146A KR 1020010074736 A KR1020010074736 A KR 1020010074736A KR 20010074736 A KR20010074736 A KR 20010074736A KR 20030044146 A KR20030044146 A KR 20030044146A
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- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 claims abstract description 123
- 230000008569 process Effects 0.000 claims abstract description 83
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims description 79
- 150000004767 nitrides Chemical class 0.000 claims description 17
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- 229910052710 silicon Inorganic materials 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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Abstract
Description
본 발명은 플래쉬 메모리 셀의 제조 방법에 관한 것으로, 특히 마스크 공정을 감소시켜 제품의 수율 향상과 원가 절감 효과를 가질 수 있는 플래쉬 메모리 셀의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell that can reduce the mask process to improve the yield and cost reduction of the product.
일반적으로, 플래쉬 메모리 셀(Flash memory cell)은 소자 분리 공정으로 STI(Shallow Trench Isolation) 공정을 이용하여 구현하고 있는데, 마스크 패터닝(Mask patterning)을 이용한 플로팅 게이트의 아이솔레이션(Isolation) 공정시 마스크 임계 치수(Critical Dimension; CD)의 변화(Variation)에 따라 웨이퍼 균일성(Wafer uniformity)이 매우 불량하여 균일한 플로팅 게이트 구현이 용이하지 않으며, 커플링비(Coupling ratio)의 변화에 따라 메모리 셀의 프로그램 및 소거 패일(Fail) 등의 문제가 발생하고 있다. 더욱이 고집적화되는 설계 특성상 0.15㎛ 이하의 작은 스페이스(Space) 구현시에 마스크 공정이 더욱 어려워져 균일한 플로팅 게이트 구현이 중요한 요소로 작용하는 플래쉬 메모리 셀 제조 공정이 한층 더 어려워지고 있다.In general, a flash memory cell is implemented using a shallow trench isolation (STI) process as a device isolation process, and a mask critical dimension in an isolation process of a floating gate using mask patterning. Wafer uniformity is very poor due to variation of (Critical Dimension; CD), making it impossible to implement a uniform floating gate, and programming and erasing a memory cell according to a change in coupling ratio. Problems such as fail have occurred. Furthermore, due to the highly integrated design characteristics, the mask process becomes more difficult when a small space of 0.15 μm or less is realized, and thus, a process of manufacturing a flash memory cell in which a uniform floating gate is an important factor becomes more difficult.
상기와 같은 이유로 플로팅 게이트가 균일하게 형성되지 않을 경우 커플링비의 차이가 심화되어 메모리 셀의 프로그램 및 소거 시에 과소거(Over erase)등의 문제가 발생함으로써 소자 특성에 나쁜 영향을 미치고 있다. 또한, 마스크 공정의 증가로 인해 제품의 수율 저하 및 원가 상승의 원인이 되고 있다. 그리고, STI 혹은 NS-LOCOS(Nitride-Spacer Local Oxidation of Silicon) 공정에서 공히 발생하는 모트(Moat)(즉, 필드 산화막의 활성 영역 부근이 후속 식각 공정에 의해 움푹하게 들어간 형태)로 인해 소자의 페일등이 발생하고 있는데, 고집적화되는 플래쉬 소자에 있어서 모트가 발생하지 않은 셀을 확보하여 커플링비를 높이는 것이 가장 중요한 문제로 대두되어 있다.If the floating gate is not formed uniformly for the above reason, the coupling ratio is deepened, causing problems such as over erase during program and erase of the memory cell, thereby adversely affecting device characteristics. In addition, the increase in the mask process is a cause of lowering the yield of the product and the increase in cost. In addition, the device fails due to a moat generated in the STI or the Nitride-Spacer Local Oxidation of Silicon (NS-LOCOS) process (that is, near the active region of the field oxide film is recessed by a subsequent etching process). And the like, in a highly integrated flash device, it is the most important problem to secure a cell in which no mott is generated and to increase the coupling ratio.
따라서, 본 발명은 상기의 문제를 해결하기 위해 안출된 것으로, 마스크 공정을 감소시켜 제품의 수율 향상과 원가 절감 효과를 가질 수 있는 플래쉬 메모리 셀의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory cell which can reduce the mask process and improve the yield and cost of a product.
도 1a 내지 도 1n은 본 발명의 실시예에 따른 플래쉬 메모리 셀의 제조 방법을 설명하기 위해 도시한 단면도.1A to 1N are cross-sectional views illustrating a method of manufacturing a flash memory cell according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 패드 산화막10 semiconductor substrate 12 pad oxide film
14 : 버퍼 폴리실리콘막 16 : 패드 질화막14 buffer polysilicon film 16 pad nitride film
18 : 트랜치 20 : 희생 산화막18: trench 20: sacrificial oxide film
22 : 월 산화막 24 : 라이너 산화막22: month oxide film 24: liner oxide film
26 : HDP 산화막 28 : 스크린 산화막26: HDP oxide film 28: screen oxide film
30 : 터널 산화막 32 : 제 1 폴리실리콘층30 tunnel oxide film 32 first polysilicon layer
34 : 플로팅 게이트 36 : 유전체막34: floating gate 36: dielectric film
38 : 제 2 폴리실리콘층 40 : 텅스텐 실리사이드층38: second polysilicon layer 40: tungsten silicide layer
본 발명은 반도체 기판 상부에 제 1 패드층, 버퍼층 및 제 2 패드층을 형성하는 단계; 상기 반도체 기판에 트랜치를 형성하는 단계; 전체 구조 상부에 더미층을 형성한 후 제 1 평탄화 공정을 실시하여 제 2 패드층을 노출시키는 단계; 상기 버퍼층이 노출되도록 상기 제 2 패드층을 제거하여 상기 더미층의 소정 부위를 돌출시키는 단계; 상기 버퍼층을 제거하는 동시에 돌출되는 상기 더미층이 소정 폭을 갖도록 식각하는 단계; 전체 구조 상부에 제 1 폴리실리콘층을 형성한 후 제 2 평탄화 공정을 실시하여 고립된 플로팅 게이트를 형성하는 단계; 전체 구조 상부에 유전체막 및 제 2 폴리실리콘층을 형성한 후 식각 공정을 실시하여 컨트롤 게이트를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention comprises the steps of forming a first pad layer, a buffer layer and a second pad layer on the semiconductor substrate; Forming a trench in the semiconductor substrate; Forming a dummy layer over the entire structure, and then performing a first planarization process to expose the second pad layer; Removing the second pad layer to expose the buffer layer to protrude a predetermined portion of the dummy layer; Removing the buffer layer and etching the dummy layer having a predetermined width while protruding from the buffer layer; Forming an isolated floating gate by forming a first polysilicon layer over the entire structure and then performing a second planarization process; And forming a control gate by performing an etching process after forming the dielectric film and the second polysilicon layer on the entire structure.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1n은 본 발명의 실시예에 따른 플래쉬 메모리 셀의 제조 방법을 설명하기 위해 도시한 플래쉬 메모리 셀의 단면도이다.1A to 1N are cross-sectional views of flash memory cells illustrating a method of manufacturing a flash memory cell according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 세정 공정으로 세정된 반도체 기판(10) 상부에 패드 산화막(12), 버퍼 폴리실리콘막(14) 및 패드 질화막(16)을 순차적으로 형성한다. 이때, 세정 공정은 반도체 기판(10)을 DHF(Diluted HF; 50:1의 비율로 H20로 희석된 HF용액) 또는 BOE(Buffer Oxide Etchant; HF와 NH4F가 100:1 또는 300:1로 혼합된 용액)가 채워진 용기에 담그고 DI 워터(Water)를 이용하여 세척한 다음, 반도체 기판(10)에 잔재하는 파티클(Paticle)을 제거하기 위해 다시 반도체 기판(10)을 SC-1(NH4OH/H2O2/H2O 용액이 소정 비율로 혼합된 용액)이 채워진 용기에 담그고 DI 워터를 통해 세척한 다음, 반도체 기판(10)을 건조 시키는 공정으로 이루어진다.Referring to FIG. 1A, a pad oxide film 12, a buffer polysilicon film 14, and a pad nitride film 16 are sequentially formed on the semiconductor substrate 10 cleaned by the cleaning process. At this time, the cleaning process is a semiconductor substrate 10 DHF (Diluted HF; HF solution diluted with H 2 0 at a ratio of 50: 1) or BOE (Buffer Oxide Etchant; HF and NH 4 F is 100: 1 or 300: Immersed in a container filled with 1) and washed with DI water, and then the semiconductor substrate 10 is again replaced with SC-1 (to remove particles remaining on the semiconductor substrate 10). A solution of NH 4 OH / H 2 O 2 / H 2 O solution mixed in a predetermined ratio) is immersed in a container filled with water, washed with DI water, and then the semiconductor substrate 10 is dried.
패드 산화막(12)은 상기 반도체 기판(10) 상부 표면의 결정 결함 또는 표면 처리를 위해 750 내지 900℃의 온도에서 건식 또는 습식 산화 방식을 이용하여 70 내지 100Å의 두께로 형성한다. 버퍼 폴리 실리콘막(14)은 480 내지 610℃의 온도에서 Si2H6또는 SiH4소오스 가스를 이용하여 언도프트(Undoped) 폴리실리콘 또는비정질 실리콘막으로 LP-CVD(Low Pressure Chemical Vapor Deposition) 방법으로 100 내지 150Å의 두께로 형성한다. 패드 질화막(16)은 LP-CVD 방법으로 2500 내지 3000Å의 두께로 비교적 두껍게 형성한다.The pad oxide layer 12 is formed to a thickness of 70 to 100 kPa using a dry or wet oxidation method at a temperature of 750 to 900 ° C. for crystal defects or surface treatment of the upper surface of the semiconductor substrate 10. The buffer polysilicon film 14 is a low pressure chemical vapor deposition (LP-CVD) method using an undoped polysilicon or amorphous silicon film using a Si 2 H 6 or SiH 4 source gas at a temperature of 480 to 610 ° C. To form a thickness of 100 to 150 내지. The pad nitride film 16 is formed relatively thick with a thickness of 2500 to 3000 kPa by the LP-CVD method.
도 1b를 참조하면, ISO 마스크를 이용한 STI 공정을 실시하여 상기 패드 질화막(16), 버퍼 폴리 실리콘막(14) 및 패드 산화막(12)을 포함한 반도체 기판(10)의 소정 부위를 식각함으로써 반도체 기판(10)의 소정 부위가 노출되도록 트랜치(18)가 형성된다. 이때, 트랜치(18)의 내부 경사면은 75 내지 85°정도의 경사(Slope) 각을 가지며, 패드 질화막(16)은 거의 수직한 프로파일(Profile)을 갖는다. 여기서, 반도체 기판(10)은 트랜치(18)에 의해 활성 영역과 비활성 영역(즉, 트랜치가 형성된 영역)으로 분리된다.Referring to FIG. 1B, an STI process using an ISO mask is performed to etch predetermined portions of the semiconductor substrate 10 including the pad nitride layer 16, the buffer polysilicon layer 14, and the pad oxide layer 12. The trench 18 is formed so that the predetermined part of 10 is exposed. At this time, the internal inclined surface of the trench 18 has a slope angle of about 75 to 85 degrees, and the pad nitride film 16 has a nearly vertical profile. Here, the semiconductor substrate 10 is separated into an active region and an inactive region (that is, the region where the trench is formed) by the trench 18.
도 1c를 참조하면, 월(Wall) 희생(SACrificial; SAC) 산화공정을 건식 산화방식으로 실시하여 트랜치(18)의 내부면의 실리콘을 성장시킴으로써 트랜치(18)의 내부면에 희생 산화막(20)이 형성된다. 이때, 월 희생(SAC) 산화공정을 실시하기 전에 트랜치(18)의 내부면에 형성된 자연산화막을 제거하기 위해 전처리 세정 공정이 실시되는데, 전처리 세정 공정은 DHF 또는 BOE가 채워진 용기에 담그고 DI 워터를 이용하여 세척한 다음, 파티클을 제거하기 위해 다시 반도체 기판(10)을 SC-1이 채워진 용기에 담그고 DI 워터를 통해 세척한 다음, 반도체 기판(10)을 건조 시키는 공정으로 이루어진다.Referring to FIG. 1C, a sacrificial oxide film 20 is formed on an inner surface of the trench 18 by growing a silicon on the inner surface of the trench 18 by performing a dry sac oxidation process. Is formed. At this time, the pretreatment cleaning process is performed to remove the natural oxide film formed on the inner surface of the trench 18 before the SAC oxidation process, which is immersed in a container filled with DHF or BOE, After washing, the semiconductor substrate 10 is immersed in a container filled with SC-1 again to remove particles, washed with DI water, and then dried.
월 희생(SAC) 산화공정은 공정 타겟(Target)을 최소화하여 버퍼 폴리실리콘막(14)의 산화를 최소화하도록 실시한다. 여기서, 희생 산화막(20)은 STI 공정시트랜치(18)의 내부면의 식각 손상을 보상함과 아울러 최상부의 모서리 부위(즉, 패드 산화막과 접촉되는 부위)에 라운딩을 형성하기 위해 1000 내지 1150℃의 온도에서 건식 산화방식을 이용하여 70 내지 150Å의 두께로 형성한다.The SAC oxidation process is performed to minimize oxidation of the buffer polysilicon layer 14 by minimizing a process target. Here, the sacrificial oxide film 20 is 1000 to 1150 ° C. to compensate for the etch damage of the inner surface of the STI process sheet trench 18 and to form a rounding at the uppermost corner portion (that is, the contact area with the pad oxide film). It is formed to a thickness of 70 to 150 Pa using a dry oxidation method at a temperature of.
도 1d를 참조하면, 희생 산화막(20) 두께를 타겟으로 한 세정공정을 실시하여 희생 산화막(20)을 제거한 후 트랜치(18)의 저면(Bottom)이 라운딩을 갖도록 월 산화 공정을 실시함으로써 트랜치(18)의 내부면에 월 산화막(22)이 형성된다. 이때, 월 산화 공정을 실시하기 전에 트랜치(18)의 내부면에 형성된 희생 산화막(20)을 제거하기 위해 전처리 세정공정이 실시되는데, 전처리 세정 공정은 DHF 또는 BOE가 채워진 용기에 담그고 DI 워터를 이용하여 세척한 다음, 파티클을 제거하기 위해 다시 반도체 기판(10)을 SC-1이 채워진 용기에 담그고 DI 워터를 통해 세척한 다음, 반도체 기판(10)을 건조 시키는 공정으로 이루어진다. 월 산화막(22)은 750 내지 850℃의 온도에서 습식 산화방식으로 70 내지 150Å의 두께로 형성한다.Referring to FIG. 1D, after the sacrificial oxide film 20 is removed by a cleaning process targeting the thickness of the sacrificial oxide film 20, the trench may be formed by performing a monthly oxidation process so that the bottom of the trench 18 has a rounding. A wall oxide film 22 is formed on the inner surface of 18. At this time, the pretreatment cleaning process is performed to remove the sacrificial oxide film 20 formed on the inner surface of the trench 18 before the month oxidation process, which is immersed in a container filled with DHF or BOE and using DI water. After washing, the semiconductor substrate 10 is immersed in a container filled with SC-1 again to remove particles, washed with DI water, and then dried. The wall oxide film 22 is formed to a thickness of 70 to 150 Pa by wet oxidation at a temperature of 750 to 850 ° C.
도 1e를 참조하면, 전체 구조 상부에 DCS(SiH2Cl2)을 기본으로 하는 HTO(High Temperature Oxide)를 얇게 증착한 후 고온에서 치밀화 공정을 실시하여 라이너(Liner) 산화막(24)을 형성한다. 이때, 치밀화 공정은 1000 내지 1100℃ 고온에서 N2 분위기에서 20 내지 30분 동안 실시하며, 이 치밀화 공정에 의해 라이너 산화막(24)의 조직이 치밀해져 식각 저항성이 증가함에 따라 STI 공정시 발생하는 모트의 형성을 억제함과 아울러 누설 전류(Leakage current)를 방지할 수 있다.Referring to FIG. 1E, a thin film of HTO (High Temperature Oxide) based on DCS (SiH 2 Cl 2 ) is deposited on the entire structure, and a densification process is performed at a high temperature to form a liner oxide layer 24. . At this time, the densification process is performed for 20 to 30 minutes in an N2 atmosphere at a high temperature of 1000 to 1100 ℃, by the densification process of the liner oxide film 24 is increased by the etching resistance of the mortity generated during the STI process In addition to suppressing formation, leakage current can be prevented.
도 1f를 참조하면, 트랜치(18)를 포함한 전체 구조 상부에 트랜치(18)를 매립하도록 HDP(High Density Plasma) 산화막(26)을 형성한다. 이때, HDP 산화막(26)은 트랜치(18) 내부에 보이드(Void)가 발생하지 않도록 갭 필링(Gap filling) 공정을 실시하여 5000 내지 10000Å의 두께로 형성한다.Referring to FIG. 1F, an HDP (High Density Plasma) oxide layer 26 is formed to fill the trench 18 over the entire structure including the trench 18. At this time, the HDP oxide layer 26 is formed to have a thickness of 5000 to 10000 Pa by performing a gap filling process so that voids do not occur in the trench 18.
도 1g를 참조하면, 전체 구조 상부에 패드 질화막(16)을 식각 베리어층으로 이용하는 평탄화 공정(CMP; Chemical mechanical pholishing)을 실시함으로써 HDP 산화막(26)의 소정 부위가 연마되어 패드 질화막(16)의 상부면이 노출된다. 이때, 평탄화 공정(CMP)은 패드 질화막(16)을 식각 베리어층으로 이용하여 실시하는데, 패드 질화막(16) 상부면에 잔존할 수 있는 HDP 산화막(26)을 제거하기 위해 BOE 또는 HF를 이용한 세정 공정을 더 포함하여 실시한다. 또한, 패드 질화막(16)이 너무 과도하게 식각되지 않도록 평탄화 공정(CMP)을 실시한다.Referring to FIG. 1G, a planarization process (CMP; chemical mechanical pholishing) using the pad nitride film 16 as an etch barrier layer is performed on the entire structure to polish a predetermined portion of the HDP oxide film 26 to form the pad nitride film 16. The top surface is exposed. In this case, the planarization process (CMP) is performed by using the pad nitride layer 16 as an etch barrier layer, and using BOE or HF to remove the HDP oxide layer 26 that may remain on the top surface of the pad nitride layer 16. The process is further included. In addition, a planarization process (CMP) is performed to prevent the pad nitride film 16 from being excessively etched.
도 1h을 참조하면, H3PO4(인산)을 이용한 식각 공정을 실시하여 버퍼 폴리실리콘막(14)이 노출되도록 HDP 산화막(26)을 제외한 패드 질화막(16)을 식각한다. 이때, HDP 산화막(26)은 도시된 바와 같이 1500 내지 2000Å 정도의 높이를 가진 니플(nipple) 형태로 돌출된다. 사실상, HDP 산화막(26)의 양측벽에는 라이너 산화막(24)이 잔재할 수 도 있으나, 여기서는 HDP 산화막(26)과 라이너 산화막(24)이 동일한 산화막 계열의 물질로 형성됨에 따라 그에 대한 설명은 생략하기로 한다.Referring to FIG. 1H, the pad nitride layer 16 except the HDP oxide layer 26 is etched by performing an etching process using H 3 PO 4 (phosphate) to expose the buffer polysilicon layer 14. At this time, the HDP oxide layer 26 is protruded in the form of a nipple (nipple) having a height of about 1500 ~ 2000Å as shown. In fact, the liner oxide layer 24 may remain on both sidewalls of the HDP oxide layer 26, but the description thereof is omitted as the HDP oxide layer 26 and the liner oxide layer 24 are formed of the same oxide-based material. Let's do it.
도 1i를 참조하면, 전체 구조 상부에 습식 산화방식을 이용하여 버퍼 폴리실리콘막(14) 두께의 두배 이상으로 산화 공정 타겟을 설정하여 산화 공정을 실시함으로써 버퍼 폴리실리콘(14)이 두배의 두께로 산화되어 성장된다. 이때, 산화 공정은 750 내지 900℃ 온도에서 습식 산화방식으로 실시한다.Referring to FIG. 1I, the buffer polysilicon 14 is doubled by performing an oxidation process by setting an oxidation process target to at least twice the thickness of the buffer polysilicon film 14 using a wet oxidation method over the entire structure. Oxidized and grown. At this time, the oxidation process is carried out by a wet oxidation method at a temperature of 750 ~ 900 ℃.
도 1j를 참조하면, 세정 공정을 실시하여 버퍼 폴리실리콘막(14) 및 패드 산화막(12)을 식각하여 제거하는 동시에 니플 형태로 돌출되는 HDP 산화막(26)을 식각한다. 이때, 세정 공정은 DHF가 채워진 용기에 담그고 DI 워터를 이용하여 세척한 다음, 파티클을 제거하기 위해 다시 반도체 기판(10)을 SC-1이 채워진 용기에 담그고 DI 워터를 통해 세척한 다음, 반도체 기판(10)을 건조 시키는 공정으로 이루어진다. 또한, 세정 공정시, 식각 타겟으로 딥 타임(Dip time)을 조절하여 HDP 산화막(26)을 식각함으로써 원하는 두께만큼 식각할 수 있어 모트가 형성되는 것을 방지할 수 있으며, 후속 공정에 의해 형성되는 플로팅 게이트의 스페이싱(Spacing)을 최소화할 수 있다. 이어서, 활성 영역 상부에 750 내지 900℃의 온도에서 습식 또는 건식 산화방식으로 50 내지 70Å의 두께로 스크린 산화막(28)을 형성한다.Referring to FIG. 1J, the buffer polysilicon layer 14 and the pad oxide layer 12 are etched and removed, and the HDP oxide layer 26 protruding in the form of nipples is etched. At this time, the cleaning process is immersed in a container filled with DHF and washed with DI water, and then again to remove the particles, the semiconductor substrate 10 in a container filled with SC-1 and washed with DI water, and then the semiconductor substrate It consists of the process of drying (10). In addition, during the cleaning process, the HDP oxide layer 26 may be etched by adjusting the dip time with an etching target to etch to a desired thickness to prevent the formation of a moat, and may be formed by a subsequent process. Spacing of the gate can be minimized. Subsequently, the screen oxide film 28 is formed on the active region at a thickness of 50 to 70 Pa by wet or dry oxidation at a temperature of 750 to 900 ° C.
도 1k를 참조하면, 웰 이온 주입 공정을 실시하여 반도체 기판(10)의 활성 영역에 웰 영역(도시하지 않음)을 형성하고, 문턱 전압 이온 주입 공정을 실시하여 불순물 영역을 형성한다.Referring to FIG. 1K, a well ion implantation process is performed to form a well region (not shown) in an active region of the semiconductor substrate 10, and a threshold voltage ion implantation process is performed to form an impurity region.
이어서, 세정 공정을 실시하여 스크린 산화막(28)을 제거한 후 스크린 산화막(28)이 제거된 부위에 터널 산화막(30)을 형성한다. 이때, 세정 공정은 DHF가 채워진 용기에 담그고 DI 워터를 이용하여 세척한 다음, 파티클을 제거하기 위해 다시 반도체 기판(10)을 SC-1이 채워진 용기에 담그고 DI 워터를 통해 세척한 다음, 반도체 기판(10)을 건조 시키는 공정으로 이루어진다. 터널 산화막(30)은 750 내지 800℃의 온도에서 습식 산화방식을 실시하여 형성한 후 반도체 기판(10)과의 계면결함 밀도를 최소화하기 위해 900 내지 910℃의 온도에서 N2를 이용하여 20 내지 30분 동안 열처리를 실시하여 형성한다.Subsequently, after the screen oxide film 28 is removed by a cleaning process, the tunnel oxide film 30 is formed at the portion where the screen oxide film 28 is removed. At this time, the cleaning process is immersed in a container filled with DHF and washed with DI water, and then again to remove the particles, the semiconductor substrate 10 in a container filled with SC-1 and washed with DI water, and then the semiconductor substrate It consists of the process of drying (10). The tunnel oxide layer 30 is formed by performing a wet oxidation method at a temperature of 750 to 800 ° C. and then 20 to 20 using N 2 at a temperature of 900 to 910 ° C. to minimize the density of interfacial defects with the semiconductor substrate 10. Formed by heat treatment for 30 minutes.
이어서, 그레인 크기가 최소화되어 전계 집중을 방지하도록 전체 구조 상부에 SiH4또는 Si2H6와 PH3가스 분위기에서 560 내지 620℃의 온도와 0.1 내지 3Torr의 낮은 압력 조건의 LP-CVD 방식으로 플로팅 게이트용 제 1 폴리실리콘층(32)을 1000 내지 2000Å의 두께로 형성한다. 또한, 제 1 폴리실리콘층(32)은 1.5E20 내지 3.0E20 atoms/cc 정도의 도핑 레벨로 P가 주입된다.Subsequently, the mixture is floated by LP-CVD at a temperature of 560 to 620 ° C. and a low pressure of 0.1 to 3 Torr in an SiH 4 or Si 2 H 6 and PH 3 gas atmosphere to minimize grain size to prevent electric field concentration. The gate first polysilicon layer 32 is formed to a thickness of 1000 to 2000 kPa. Further, P is injected into the first polysilicon layer 32 at a doping level of about 1.5E20 to 3.0E20 atoms / cc.
도 1l을 참조하면, 전체 구조 상부에 HDP 산화막(26)을 식각 베리어층으로 이용하는 평탄화 공정(CMP)을 실시하여 제 1 폴리실리콘층(32)의 소정 부위를 연마함으로써 HDP 산화막(26)의 상부면이 노출된다. 이로 인해, HDP 산화막(26)을 경계로 제 1 폴리실리콘층(32)이 고립되어 플로팅 게이트(34)가 형성된다.Referring to FIG. 1L, a planarization process (CMP) using the HDP oxide layer 26 as an etch barrier layer is performed on the entire structure to polish a predetermined portion of the first polysilicon layer 32 to thereby top the HDP oxide layer 26. The face is exposed. As a result, the first polysilicon layer 32 is separated from the HDP oxide film 26 to form the floating gate 34.
도 1m을 참조하면, 세정 공정을 실시하여 플로팅 게이트(34) 사이에 돌출되는 HDP 산화막(26)을 원하는 타겟 만큼 식각한다. 이와 같이 플로팅 게이트(34) 간의 스페이싱은 종래의 플로팅 게이트 마스크를 이용한 식각 공정을 통하여 구현하는 것 보다 더 작은 폭을 가질 수 있다.Referring to FIG. 1M, a cleaning process is performed to etch the HDP oxide layer 26 protruding between the floating gates 34 to a desired target. As such, spacing between the floating gates 34 may have a smaller width than that achieved through an etching process using a conventional floating gate mask.
도 1n을 참조하면, 전체 구조 상부에 ONO(Oxide/Nitride/Oxide) 구조의 유전체막(36)을 형성한다. 이때, 유전체막(36)을 형성하기 전에 니플 형태로 돌출된 HDP 산화막(26)을 소정 두께로 제거하여 플로팅 게이트(34)의 표면적을 확보하기 위해 세정 공정을 실시하되, 세정 공정은 HF 또는 BOE를 이용하여 실시한다.Referring to FIG. 1N, a dielectric film 36 having an ONO (Oxide / Nitride / Oxide) structure is formed on the entire structure. At this time, before the dielectric film 36 is formed, a cleaning process is performed to remove the HDP oxide film 26 protruding in the form of a nipple to a predetermined thickness to secure the surface area of the floating gate 34, but the cleaning process is HF or BOE. It is carried out using.
유전체막(36)의 하부와 상부를 형성하는 산화막(Oxide)은 부분적인 우수한 내압과 TDDB(Time Dependent Dielectric Breakdown)특성이 우수한 DCS(SiH2Cl2)와 N2O 가스를 소오스로 하는 HTO로 35 내지 60Å의 두께로 형성하고, 하부와 상부 사이에 형성되는 질화막(Nitride)은 반응가스로서 NH3와 DCS 가스를 이용하여 1 내지 3Torr의 낮은 압력하에서 650 내지 800℃의 온도에서 LP-CVD 방식으로 50 내지 65Å의 두께로 형성한다.Oxides forming the lower and upper portions of the dielectric layer 36 are HTO sourced from DCS (SiH 2 Cl 2 ) and N 2 O gas having excellent partial pressure resistance and TDDB (Time Dependent Dielectric Breakdown) characteristics. Nitride is formed to a thickness of 35 to 60 kPa, and the nitride film formed between the lower part and the upper part is LP-CVD at a temperature of 650 to 800 ° C. under a low pressure of 1 to 3 Torr using NH 3 and DCS gas as reaction gases. To form a thickness of 50 to 65 내지.
이어서, 유전체막(36)의 질을 향상시키고 반도체 기판(10) 상부에 형성된 층들의 인터페이스(Interface)를 강화하기 위해 습식 산화방식으로 750 내지 800℃의 온도에서 스팀 열처리를 실시하여 유전체막(36) 상부에 베어(Bare) 실리콘 W/F(Monitoring wafer) 기준으로 150 내지 300Å 두께의 산화막(도시하지 않음)을 형성한다. 여기서, 유전체막(36)과 유전체막(36) 상부에 형성되는 산화막 형성 공정은 소자 특성에 부합되는 두께로 형성하도록 실시하되, 각 층 사이에 자연산화막 또는 불순물 오염을 예방하기 위해 공정간 거의 지연시간 없이 실시된다.Subsequently, in order to improve the quality of the dielectric film 36 and to strengthen the interface of the layers formed on the semiconductor substrate 10, the dielectric film 36 is subjected to steam heat treatment at a temperature of 750 to 800 ° C. by a wet oxidation method. An oxide film (not shown) having a thickness of 150 to 300 Å is formed on the bare silicon W / F (Monitoring wafer). Here, the oxide film forming process formed on the dielectric film 36 and the dielectric film 36 is performed to have a thickness corresponding to the device characteristics, but almost delayed between processes to prevent natural oxide film or impurity contamination between the layers. It is done without time.
이어서, 전체 구조 상부에 제 2 폴리실리콘층(38) 및 텅스텐 실리사이드층(40)을 순차적으로 형성한다.Subsequently, the second polysilicon layer 38 and the tungsten silicide layer 40 are sequentially formed on the entire structure.
이때, 제 2 폴리실리콘층(38)은 후속 공정인 텅스텐 실리사이드층(40)을 형성시 유전체막(36)에 치환 고용되어 산화막 두께의 증가를 유발할 수 있는 불소(F)의 확산을 방지하기 위해 도프트층과 언도프트층의 2중 구조로 LP-CVD 방식을 이용하여 형성한다. 여기서, 후속 텅스텐 실리사이드층(40) 형성시 심(seam) 형성을 억제하여 워드라인 Rs를 감소시키기 위해 도프트층과 언도프트층의 박막 두께는 1:2 내지 6:1의 비율로 플로팅 게이트(34)의 스페이싱의 충분한 매립이 이루어지도록 전체 두께가 500 내지 1000Å 정도로 형성한다. 도프트층과 언도프트층은 도프트 폴리실리콘막을 SiH4또는 Si2H6와 같은 실리콘 소오스 가스와 PH3가스를 이용하여 도프트층을 형성한 후 PH3가스를 챔버내로 제공하지 않고 연속적으로 언토프트층을 형성한다. 또한, 제 2 폴리실리콘층(38)은 510 내지 550℃의 온도에서 0.1 내지 3Torr의 낮은 압력 조건으로 형성한다.In this case, the second polysilicon layer 38 is substituted to the dielectric film 36 when forming the tungsten silicide layer 40, which is a subsequent process, to prevent diffusion of fluorine (F), which may cause an increase in the oxide film thickness. A double structure of a doped layer and an undoped layer is formed using the LP-CVD method. Here, the thin film thickness of the dopant layer and the undoped layer in the ratio of 1: 2 to 6: 1 in order to suppress the formation of seams in the subsequent formation of the tungsten silicide layer 40 to reduce the word line Rs 34 The total thickness is formed to about 500 to 1000 mm 3 to allow sufficient embedding of the spacing of the wires. The dopant layer and the undoped layer form an dope layer using a silicon source gas, such as SiH 4 or Si 2 H 6 , and a PH 3 gas, to form a doped polysilicon layer, and then continuously undo the PH 3 gas without providing the PH 3 gas into the chamber. Form a layer. In addition, the second polysilicon layer 38 is formed under a low pressure of 0.1 to 3 Torr at a temperature of 510 to 550 ° C.
텅스텐 실리사이드층(40)은 낮은 불소(F) 함유량, 낮은 열처리 스트레스(Stress) 및 좋은 접착 강도를 갖는 MS(SiH4) 또는 DCS와 WF6의 반응을 이용하여 300 내지 500℃의 온도에서 적절한 스텝 커버리지(Step coverage)를 구현하면서 Rs를 최소화시킬 수 있는 2.0 내지 2.8의 화학적양론비로 형성한다.The tungsten silicide layer 40 has a suitable step coverage at a temperature of 300 to 500 DEG C using a reaction of MS (SiH4) or DCS and WF6 with low fluorine (F) content, low heat treatment stress and good adhesive strength. Step coverage) is formed with a stoichiometric ratio of 2.0 to 2.8 to minimize Rs.
이어서, 전체 구조 상부에 SiOxNy또는 Si3N4를 이용하여 반사 방지막(도시하지 않음)을 형성한 후 게이트용 마스크를 이용하여 반사 방지막, 텅스텐 실리사이드(40), 제 2 폴리실리콘층(38) 및 유전체막(36)을 순차적으로 식각하여 컨트롤 게이트(도시하지 않음)를 형성한다.Subsequently, an anti-reflection film (not shown) is formed on the entire structure by using SiO x N y or Si 3 N 4 , and then the anti-reflection film, tungsten silicide 40, and second polysilicon layer are formed using a gate mask. 38) and the dielectric film 36 are sequentially etched to form a control gate (not shown).
상기에서 설명한 바와 같이 본 발명은 플로팅 게이트 형성 공정까지 마스크 공정으로 ISO 마스크 공정만을 실시함으로써 ISO 마스크, 키(Key) 마스크 및 플로팅 게이트용 마스크를 포함하여 3번의 마스크 공정이 이루어지는 종래 기술의 공정에 비해 월등히 공정 단순화에 기여할 수 있어 제품의 수율 향상과 원가 절감 효과가 있다.As described above, the present invention provides a mask process up to a floating gate forming process, and thus, compared to a conventional process in which three mask processes are performed including an ISO mask, a key mask, and a floating gate mask. It can greatly contribute to process simplification, resulting in improved product yield and cost reduction.
또한, 본 발명은 갭 필링된 HDP 산화막을 남긴 후 버퍼 폴리실리콘막을 모두 산화시키고 활성 영역 상에 형성된 타겟을 이용하여 DHF 세정 공정을 실시함으로써 니플 형태로 돌출되는 HDP 산화막의 폭을 조절함에 따라 모트가 발생하지 않는 STI의 프로파일 형성이 용이하다.In addition, the present invention controls the width of the HDP oxide film protruding in the form of nipple by leaving the gap-filled HDP oxide film and then oxidizing all of the buffer polysilicon film and performing a DHF cleaning process using a target formed on the active region. It is easy to form profiles of STIs that do not occur.
또한, 본 발명은 상기에서 설명한 바와 같이 작은 크기의 소자 구현이 용이하며 마스크 및 식각 공정으로 행해오던 종래의 기술을 탈피함으로써 마스크 및 식각 공정에 따른 임계치수(CD) 변화를 최소화하여 웨이퍼 전반에 걸쳐 균일한 플로팅 게이트를 구현할 수 있다.In addition, the present invention facilitates the implementation of a small size device as described above, and by minimizing the change in the critical dimension (CD) according to the mask and etching process by eliminating the conventional technique that has been performed in the mask and etching process throughout the wafer It is possible to implement a uniform floating gate.
또한, 본 발명은 균일한 플로팅 게이트를 구현함으로써 커플링비의 변화를 감소시켜 플래시 메모리 소자의 특성을 향상할 수 있고, 활성 임계치수를 작게 함으로써 커플링 비를 극대화 할 수 있다.In addition, the present invention can improve the characteristics of the flash memory device by reducing the change in the coupling ratio by implementing a uniform floating gate, it is possible to maximize the coupling ratio by reducing the active threshold.
또한, 본 발명은 패드 질화막 두께를 이용한 HDP 산화막의 높이 조절, 버퍼 폴리실리콘막의 산화를 이용한 활성 영역 상의 산화막 두께 증가 조절 및 DHF 딥 타임 조절에 따른 모트 발생 억제가 가능하며, 폴리실리콘층의 평탄화공정을 통해 플로팅 게이트 높이의 조절이 가능하고, 유전체막 전처리 공정을 통한 플로팅 게이트의 표면적 조절 등 다양한 공정 마진 확보가 가능하다.In addition, the present invention is capable of controlling the height of the HDP oxide layer using the thickness of the pad nitride layer, controlling the increase in the thickness of the oxide layer on the active region using the oxidation of the buffer polysilicon layer, and suppressing the generation of the mott according to the DHF deep time control, and planarizing the polysilicon layer. It is possible to adjust the height of the floating gate through, and to secure a variety of process margins, such as adjusting the surface area of the floating gate through the dielectric film pretreatment process.
또한, 본 발명은 복잡한 공정/장비의 추가 소요 없이 기존의 장비와 공정을이용하여 응용/적용 가능함에 따라 0.13㎛급 이상의 고집적 플래쉬 메모리 셀의 구현을 위한 공정 마진 확보가 용이하다.In addition, the present invention is easy to secure a process margin for the implementation of a highly integrated flash memory cell of 0.13㎛ class or more according to the application / application using existing equipment and processes without the need of complicated processes / equipment.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100663608B1 (en) * | 2004-12-30 | 2007-01-02 | 매그나칩 반도체 유한회사 | Method for manufacturing cell of flash memory device |
| KR100665397B1 (en) * | 2002-07-06 | 2007-01-04 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
| KR100691938B1 (en) * | 2005-06-30 | 2007-03-09 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
| KR100799056B1 (en) * | 2005-12-21 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for fabricating a semiconductor device |
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2001
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100665397B1 (en) * | 2002-07-06 | 2007-01-04 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
| KR100663608B1 (en) * | 2004-12-30 | 2007-01-02 | 매그나칩 반도체 유한회사 | Method for manufacturing cell of flash memory device |
| KR100691938B1 (en) * | 2005-06-30 | 2007-03-09 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
| KR100799056B1 (en) * | 2005-12-21 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for fabricating a semiconductor device |
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