KR100673224B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, and when forming a floating gate electrode pattern, a polymer film is first formed on sidewalls of a mask pattern to form an inclined surface at an upper edge portion of the floating gate electrode, thereby preventing a leakage current problem of the dielectric film. By forming the upper edge portion of the floating gate electrode in a triangular shape by using the polymer film, it is possible to prevent a phenomenon in which the crack occurs in the tungsten silicide film due to the step difference.

Polymer Films, Floating Gates, Self-Aligned Cellulose Trench Isolation

Description

Method of manufacturing a flash memory device             

1 is a cross-sectional view of a flash memory device formed through a conventional process.

2A to 2F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

3 is an SEM photograph of a flash memory device formed by the manufacturing method of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate 12, 112: device isolation film

14, 114 tunnel oxide film 30 dielectric film

34, 134: tungsten silicide film 118: pad nitride film

122: barrier film 124: photosensitive film pattern

126 polymer film 130 dielectric film

16, 20, 32, 116, 120, 132: polysilicon film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of forming an inclined surface on an edge portion of an upper portion of a floating gate electrode.

In the recent flash device implementation, a self-aligned shallow trench isolation (SA-STI) process is formed in which a tunnel oxide film and a first polysilicon film are formed before a pad nitride film and etched to form trenches. Doing.

1 is a cross-sectional view of a flash memory device formed through a conventional process.

Referring to FIG. 1, a tunnel oxide layer 14, a first polysilicon layer 16, and a second polysilicon layer 20 are deposited on a semiconductor substrate 10 on which the device isolation layer 12 is formed. A floating gate electrode is formed by performing the patterning process. The dielectric film 30, the third polysilicon film 32, and the tungsten silicide film 34 are deposited on the entire structure, and then patterned to form the dielectric film 30 and the control gate electrode. As design rules are reduced and devices are integrated, securing a coupling ratio has become important in the manufacture of flash devices. By increasing the floating gate height, it is possible to secure the coupling ratio. have. However, as the height of the floating gate increases and the inter-cell space decreases, a concave-convex shape is formed during the deposition of the second polysilicon film 20 for the control gate electrode after the deposition of the dielectric film 30. Induces crack formation (region A in FIG. 1). In addition, when the upper portion of the floating gate is vertically etched, a sharp tip is formed when a portion of the floating gate is oxidized during the subsequent oxidation process or deposition of the ONO structure dielectric film 30. An electric field concentration phenomenon occurs to deteriorate the quality of the dielectric film 30.

Therefore, in order to solve the above problems, the present invention provides a dielectric film and an inclined surface on the upper edge portion of the floating gate by performing an etching process using a polymer to form a mask on the sidewall of the mask for forming the floating gate electrode. A method of manufacturing a flash memory device capable of increasing embedding of a polysilicon film, preventing cracking of tungsten silicide, and preventing electric field concentration of the dielectric film.

A device isolation film is provided in a field region according to the present invention, and a semiconductor substrate including a tunnel oxide film and a first polysilicon film is provided in an active region, and a second polysilicon film and a barrier film are sequentially deposited on the entire structure. Forming a photoresist pattern on the photoresist, etching the barrier layer and a portion of the second polysilicon layer using the photoresist pattern as an etch mask to form a polymer film in the form of a spacer on the sidewall of the barrier layer, and the photoresist pattern Patterning the second polysilicon film by an etching process using the barrier film having the polymer film formed on the sidewalls as an etching mask, removing the photoresist pattern, the polymer film and the barrier film, and controlling the dielectric film and the control on the entire structure. Forming a gate Provides a method of manufacturing a flash memory device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2A to 2F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

Referring to FIG. 2A, a screen oxide layer (not shown) serving as a buffer layer is deposited on a semiconductor substrate 110 to suppress crystal defects or surface treatment and implant ions, followed by ion implantation to form wells. After removing the screen oxide layer, the tunnel oxide layer 114, the first polysilicon layer 116, and the pad nitride layer 118 are deposited.                     

The pad nitride layer 118, the first polysilicon layer 116, the tunnel oxide layer 114, and the semiconductor substrate 110 are sequentially etched through ISO mask patterning to allow shallow trench isolation (STI). Trenchs in the structure are defined to define active and field regions. The corner portion of the trench is rounded by performing a dry oxidation process to compensate for the etch damage of the trench sidewalls of the STI structure. A thin film of High Temperature Oxide (HTO) is deposited on the entire structure and a densification process is performed at a high temperature to form a liner oxide film (not shown). Of course, the above-described liner oxide film deposition process may be omitted to simplify the process.

A high density plasma (HDP) oxide film is deposited on the entire structure to fill the trench. A planarization process using the pad nitride film 118 as a stop layer is performed to remove the HDP oxide film and the liner oxide film on the pad nitride film 118. This forms an isolation layer 112 for isolation between the elements.

Specifically, for cleaning the semiconductor substrate 110 before the screen oxide film is formed, a mixture ratio of H ₂ O and HF is 50: 1 composed of DHF (Dilute HF), NH ₄ OH, H ₂ O _2, and H ₂ O. 1 was the BOE (Buffered Oxide Etch) and NH ₄ OH, H ₂ O ₂ and H ₂ O: - SC-1 a (Standard Cleaning 1), or from, NH ₄ F and HF in a mixing ratio of 100: 1 to 300 The pretreated washing process is performed using the configured SC-1. Dry or wet oxidation is performed within a temperature range of 750 to 800 ° C. to form the screen oxide film having a thickness of 30 to 120 Pa.

After ion implantation, the screen oxide film is etched using SC-1 composed of DHF having a mixing ratio of H ₂ O and HF of 50: 1, and NH ₄ OH, H ₂ O _2, and H ₂ O. The tunnel oxide film 114 was formed to a thickness of 85 to 110 Pa by wet oxidation at a temperature of 750 to 800 ° C., and then heat-treated for 20 to 30 minutes using N ₂ at a temperature of 900 to 910 ° C. after the deposition of the tunnel oxide film 114. By performing the process, the defect density at the interface between the tunnel oxide film 114 and the semiconductor substrate 110 is minimized.

Chemical Vapor Deposition (CVD), Low Pressure CVD (LP-CVD), Plasma Enhanced Chemistry at a temperature of 480 to 550 ° C. and a pressure of 0.1 to 3.0 torr on the tunnel oxide layer 114. First polysilicon which is an undoped amorphous silicon film having a thickness of 250 to 500 kPa using SiH ₄ gas by means of plasma enhanced CVD (PE-CVD) or atmospheric pressure chemical vapor deposition (AP-CVD). A film 116 is deposited. As a result, the particle size of the first polysilicon layer 116 may be minimized to prevent electric field concentration. The pad nitride film 118 is formed on the first polysilicon film 116 to a high thickness of about 900 to 1500 kPa by the LP-CVD method.

In order to form the trench, a photoresist film is coated on the entire structure, and then a photolithography process using a photoresist mask is performed to form a photoresist pattern (not shown). An etching process using the photoresist pattern as an etching mask is performed to etch the pad nitride layer 118, the first polysilicon layer 116, the tunnel oxide layer 114, and the semiconductor substrate 110 to form trenches having an STI structure. In forming the trench, the semiconductor substrate 110 is etched to have a 75 to 85 ° inclination. In order to compensate for damage to the trench sidewalls due to the above-described etching process, dry or wet oxidation processes are performed in a temperature range of 800 to 1100 ° C. in order to round the trench upper corners to form sidewall oxide films 50 to 50. It is formed to a thickness of 150Å. By performing a lower dry oxidation process than the prior art to minimize the diffusion of the implanted ions to control the well or threshold voltage (Vt) to maintain a normal junction and well.

In order to improve the adhesion between the oxide film and the trench of the subsequent process, and to prevent the occurrence of moat, it is deposited by a thickness of 50 to 150Å with HTO formed using DCS (Dichloro Silane; SiH ₂ Cl ₂ ) gas, A high temperature densification process is performed for 20 to 30 minutes using N ₂ at a temperature of 1000 to 1100 ° C. to form a liner oxide film (not shown). The high temperature densification process densifies the structure of the liner oxide, increasing the etch resistance, suppressing the formation of motes in the STI implementation, and helping to prevent leakage currents.

In order to fill the trench gaps, an HDP (High Density Plasma) oxide film is formed to a thickness of about 4000 to 10000 GPa. At this time, the HDP oxide film is deposited to form a device isolation layer 112 so that an empty space is not formed in the trench.

A planarization process using CMP using the pad nitride film 118 as a stop film is performed. Proceed as a method of leaving a nitride film of a desired thickness by the CMP process to leave an HDP oxide film of a suitable thickness to realize the uneven shape deposition during the deposition of the second polysilicon film formed through the subsequent process to maximize the floating gate surface area do.

The post-cleaning process using BOE or HF is performed in order to remove the oxide film which may remain on the pad nitride film 118. At this time, excessive etching should be suppressed as much as possible to reduce the height of the HDP oxide film. The HDP oxide layer fills the inside of the trench, and the upper portion of the HDP oxide layer is protruded to form an isolation layer 112 that isolates the floating gate electrodes formed by a subsequent process from each other.

2B and 2C, the pad nitride layer 118 is etched by performing a nitride strip process using phosphoric acid (H ₃ PO ₄ ). A pretreatment cleaning process using DHF is performed to remove the native oxide film and residues formed on the first polysilicon film 116. The second polysilicon layer 120 and the barrier layer 122 are deposited on the entire structure, and then the photoresist layer pattern 124 is formed on the barrier layer 122.

Specifically, the strip process is performed to expose the first polysilicon film 116, and then the wet cleaning process is performed to minimize the interface effect between the first and second polysilicon films 116 and 120. In addition, the delay time between the pretreatment cleaning process and the deposition of the second polysilicon film 120 is set within 2 hours to suppress the growth of the additional natural oxide film.

The second polysilicon film 120 is a two-layer structure of a doped film and an undoped film. The second polysilicon film 120 may be formed by CVD, PE-CVD, and the like at a temperature of about 500 to 550 ° C. and a pressure of 0.1 to 3 torr. It is preferable to deposit with an amorphous silicon film whose surface roughness is stable using LP-CVD or AP-CVD. In addition, the ratio of the doped film and the undoped film is set at a ratio of 1: 2 to 19: 1, and is formed in a form of unevenness in the form of unevenness within a range capable of maximizing the coupling ratio of the device. When forming the second polysilicon film 120 having the two-layer structure, a doped film is formed using SiH ₄ or Si ₂ H ₆ and PH ₃ gas, and thereafter, the PH ₃ gas is blocked and not continuously doped. It is preferable to form a film. Due to the step between the first polysilicon film 116 and the device isolation film 112, the second polysilicon film 120 is not formed to have a constant thickness but is formed to have a constant thickness. In this case, a step is generated on the second polysilicon layer 120 by the device isolation layer 112 protruding higher than the first polysilicon layer 116 while the pad nitride layer 118 is removed.

The barrier film 122 forms a nitride film having a thickness of 500 to 1500 mW using a CVD, PE-CVD, LP-CVD, or AP-CVD method.

After the photoresist is coated on the barrier layer 122, a photolithography process using a mask for forming the device isolation layer 112 is performed to form a photoresist pattern 124 that opens an upper portion of the device isolation layer 112. The portion to be etched is opened at the intermediate point of the inclined surface (region C of FIG. 2C) by the photosensitive film pattern.

2D and 2E, the etching process using the photoresist pattern 124 as an etching mask is performed to remove the barrier layer 122, and a portion of the second polysilicon layer 120 is etched to form the barrier layer 122. A polymer film 126 in the form of a spacer is formed on the sidewalls. An etching process is performed using the barrier layer 122 including the photoresist pattern 124 and the polymer layer 126 as an etching mask to etch the second polysilicon layer 120 to form a floating gate electrode. The photosensitive film pattern 124, the polymer film 126, and the barrier film 122 are removed.                     

Specifically, a part of the barrier layer 122 and the second polysilicon layer 120 is dry etched so that a polymer made of a mixture of etching by-products and etching chemicals generated during the etching process is formed on the sidewall of the barrier layer 122. In the form of a spacer. That is, an etching process using at least one of CF4 gas, CHF3 gas, C2F6 gas, C4F8 gas, and HBr gas is performed to etch a portion of the barrier film 122 and the second polysilicon film 120 to form a barrier film 122. A polymer film 126 in the form of a spacer is formed on the sidewalls. This is because a large amount of polymer is generated by etching using an etching gas having a high C / F ratio. Therefore, since the polymer film 126 is generated at the same time as the barrier film 122 and the second polysilicon film 120 are etched, the interface between the polymer film 126 and the second polysilicon film 120 is along the etching direction. Is formed. In addition, since a polymer film 126 having a predetermined thickness is formed on the sidewall of the barrier film 122, a misalignment margin with the lower active region may be secured.

The floating gate electrode is formed by performing an etching process using the photoresist pattern 124 and the barrier layer 122 having the polymer layer 126 formed on the sidewalls as an etching mask. In this case, the upper portion of the device isolation layer 112 is formed to be recessed through a transient etching to remove a portion of the exposed device isolation layer 112 to ensure isolation of the floating gate electrode, thereby minimizing the loss of the device isolation layer 112. The photosensitive film pattern 124, the polymer film 126, and the barrier film 122 remaining on the second polysilicon film 120 are removed. The barrier film 122 is removed using an aqueous solution of phosphoric acid. As a result, an inclined surface (see region D in FIG. 1E) is formed at the upper edge portion of the floating gate electrode. It is possible to prevent the leakage current due to the pointed edge on the conventional floating gate electrode, it is possible to reduce the step due to the lower element separator.

Referring to FIG. 2F, a cleaning process is performed to remove the natural oxide film formed on the entire structure surface including the floating gate electrode, and then the third polysilicon layer is a material film for forming the dielectric film 130 and the control gate over the entire structure. The film 132 and the tungsten silicide film (WSi _x ; 134) are sequentially formed, followed by patterning the dielectric film 130, the third polysilicon film 132, and the tungsten silicide film 134 to form a control gate electrode. do.

Specifically, the cleaning process performs wet cleaning using BOE or HF to remove the oxide film that may remain on the entire structure.

As the dielectric film 130, various types of dielectric films used in semiconductor devices are deposited. In this embodiment, ONO (oxide film / nitride film / oxide film (SiO ₂ -Si ₃ N ₄ -SiO ₂ )) or ONON structure dielectric film is deposited. 130 is deposited. In the ONO structure dielectric film 130, the oxide film in the ONO structure uses a low pressure of 0.1 to 3 torr and about 810 to 850 ° C. using DCS (SiH ₂ Cl ₂ ) and N ₂ O gas having good internal pressure and TDDB characteristics. It is deposited by the LP-CVD method at a thickness of about 35 to 60 kPa under a temperature of. In the ONO structure, the nitride film is deposited by the LP-CVD method using DCS and NH ₃ gas at a thickness of about 50 to 65 kPa under a low pressure of 1 to ₃ torr and a temperature of about 650 to 800 ° C.

After performing the ONO process, a thickness of about 150 to 300Å based on a monitoring wafer at a temperature of about 750 to 800 ° C. by a wet oxidation method is used to improve the quality of the ONO oxide film and to strengthen the interface between the layers. Steam anneal may be performed to oxidize. Further, when the ONO process and the steam annealing are performed, a delay time between the processes is performed without a time delay within several hours to prevent contamination with a natural oxide film or impurities.

The third polysilicon layer 132 may be substituted with the dielectric layer 130 during deposition of tungsten silicide 134 to prevent the diffusion of hydrofluoric acid, which may increase the thickness of the oxide layer. doped and undoped), which is deposited into an amorphous silicon film by LP-CVD at a temperature of about 510 to 550 ° C. and a pressure of 0.1 to 3 torr. At this time, the ratio of the doped film and the undoped film is set at a ratio of 1: 2 to 6: 1, and the amorphous silicon film is formed to a thickness of about 500 to 1000 mm so that the space between the floating gate electrodes is sufficiently buried. When the tungsten silicide 132 is deposited, the gap formation may be suppressed to reduce the word line resistance Rs. When forming the double layer of the third polysilicon film 132, a doped film is formed using SiH ₄ or Si ₂ H ₆ and PH ₃ gas, and then the PH ₃ gas is blocked and is not continuously doped. It is preferable to form a film.

The tungsten silicide layer 134 may be prepared by using a reaction of MS (SiH ₄ ) or DCS (SiH ₂ CL ₂ ) with WF ₆ having low fluorine content, low post annealed stress, and good adhesive strength. Proper step coverage is achieved at temperatures between 500 ° C and growth is about 2.0 to 2.8, a stoichiometric ratio that can minimize the word line resistance (Rs).

A hard mask film and an ARC layer (not shown) are deposited on the tungsten silicide layer 134 using SiO _x N _y or Si ₃ N ₄ , and a gate mask and etching process, a self-aligned mask, A self-aligned mask and etching process is performed to form the control gate electrode.

3 is an SEM photograph of a flash memory device formed by the manufacturing method of the present invention.

Referring to FIG. 3, a sharp tip shape is not formed near the upper edge of the floating gate, and an inclined surface (triangle shape) having a gentle slope is formed (see region E of FIG. 3). Thereby, the leakage current by electric field concentration can be prevented. In addition, it can be seen that the level difference in the upper portion of the floating gate becomes smooth so that no crack is formed in the tungsten silicide layer on the floating gate.

As described above, when the floating gate electrode pattern is formed, the polymer film is first formed on the sidewalls of the mask pattern to form an inclined surface at the upper edge portion of the floating gate electrode, thereby preventing the leakage current problem of the dielectric layer.

In addition, due to the polymer film, misalignment due to the photosensitive film pattern can be prevented.                     

In addition, by forming a trench of the STI structure to prevent the gate oxide thinning that is deposited in the upper corner of the trench smaller than the desired thickness, it is possible to secure the active area of the desired threshold dimension, the electrical characteristics of the device Can be improved.

In addition, damage to the tunnel oxide film through the subsequent process can be prevented to form a uniform tunnel oxide film within the channel width.

In addition, by forming the upper edge portion of the floating gate electrode in a triangular shape to reduce the step, it is possible to prevent the phenomenon that the crack occurs in the tungsten silicide film due to the step.

Claims (7)

(a) forming a tunnel oxide film, a first polysilicon film, and a pad nitride film over the semiconductor substrate, and then etching a predetermined region for device isolation to form a trench; (b) forming an oxide layer to fill the trench and forming a device isolation layer by performing a planarization process to expose the pad nitride layer, and then removing the pad nitride layer; (c) sequentially depositing a second polysilicon film and a barrier film on the entire structure, and then forming a photoresist pattern on the barrier film; (d) etching the barrier layer and a portion of the second polysilicon layer using the photoresist pattern as an etch mask to form a polymer film in a spacer form on sidewalls of the barrier layer; (e) patterning the second polysilicon layer by an etching process using the barrier layer having the polymer layer formed on the photoresist pattern and sidewalls as an etching mask; (f) removing the photoresist pattern, the polymer film and the barrier film; And (g) forming a dielectric film and a control gate over the entire structure. The method of claim 1, The pad nitride film is formed using a nitride film having a thickness of 500 to 1500 Å. The method of claim 1, And the second polysilicon film is a film in which a doped amorphous silicon film and an undoped amorphous silicon film are sequentially stacked. The method of claim 3, wherein And a ratio of the doped amorphous silicon film and the undoped amorphous silicon film in the second polysilicon film is 1: 2 to 19: 1. The method of claim 1, wherein in step (e), A method of manufacturing a flash memory device, wherein an edge of a region where the device isolation layer and the second polysilicon layer overlap with each other becomes thinner. The method of claim 1, wherein step (f) comprises: And forming the polymer film using at least one of CF4 gas, CHF3 gas, C2F6 gas, C4F8 gas, and HBr gas. The method of claim 1, wherein step (a) comprises: Sequentially forming a tunnel oxide film, a first polysilicon film, and a pad insulating film on a semiconductor substrate; Etching a portion of the pad insulating film, the first polysilicon film, the tunnel oxide film, and the semiconductor substrate through a patterning process to form a trench in the semiconductor substrate; And Depositing an oxide film over the entire structure including the trench, and then performing a planarization process to remove the pad insulating film and the oxide film on the first polysilicon film.

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