KR100602126B1 - Flash memory cell and method for manufacturing the same - Google Patents

Abstract

A plurality of trench lines and trenches formed in parallel in a flash memory cell in which an STI sidewall, a first polycrystalline silicon, a second oxide film, and a second polycrystalline silicon are formed on a semiconductor substrate on which active and trench regions are formed. A plurality of gate lines formed in a direction perpendicular to the lines, and formed between the gate lines, including a common source region ion-implanted on the surfaces of the active region and the trench region in a direction parallel to the gate line; A wall is a flash memory cell formed in part of an active region and in a trench region.

Flash memory, self-aligned source, common source, STI

Description

Flash memory cell and manufacturing method therefor {FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME}

1 is a layout view of a flash memory cell according to an embodiment of the present invention,

2A through 2E are cross-sectional views illustrating a process of manufacturing a flash memory cell according to an embodiment of the present invention.

The present invention relates to a flash memory cell and a method for manufacturing the same, and more particularly, to a method for manufacturing a device isolation film.

In general, a flash memory device is manufactured by taking advantage of EPROM having programming and erasing characteristics and EEPROM having electrical programming and erasing characteristics. Such a flash memory device includes a tunnel oxide film of a thin film formed on a silicon substrate, a floating gate and a control gate stacked under a shallow trench isolation (STI), and a source and drain region formed in an exposed substrate portion. As a single transistor, the storage state of one bit is realized, and the programming and erasing are performed electrically.

In order to manufacture such a flash memory device, a pad oxide film is first formed on a semiconductor substrate, and a nitride film and a TEOS film are formed thereon.

The pad oxide film, nitride film, and TEOS are then patterned and used as a mask to etch the semiconductor substrate to form a trench, and then deposit an STI sidewall on the trench inner wall.

The trench is then filled with high density plasma (HDP). Subsequently, the TEOS and the HDP formed on the nitride film are subjected to chemical mechanical polishing (CMP) process and planarized.

Next, the nitride film is removed using a phosphate material. Through this process, an isolation layer is formed. The device isolation layer is an insulating layer for preventing an electrical effect between the cell and the cell of the flash memory.

As described above, the first oxide film, the first polycrystalline silicon, the second oxide film, and the second polycrystalline silicon are sequentially formed on the trench region where the device isolation film is formed and the semiconductor substrate on which the active region is formed.

Next, the first oxide film, the first polycrystalline silicon, the second oxide film, and the second polycrystalline silicon are etched to form a gate line. Subsequently, after removing the device isolation layer of the common source region formed between the gate lines adjacent to each other using a SAS mask, ions are implanted into the active region to form the common source region and the drain region.

The SAS mask exposes a portion of the gate line and between neighboring gate lines, the exposed boundary line of which is aligned with the gate line above the gate line.

On the other hand, when the etching process is performed several times to form the device isolation layer, as the portion of the STI sidewall and the gate insulating film is etched by the etchant, the thickness thereof becomes thinner, and thus, the thickness of the first oxide film formed in the subsequent process is reduced. Difficult to control the thickness

Such a thin gate insulating film is influenced by a high electric field by a bias applied when erasing information stored in the flash memory, which causes a decrease in reliability and performance of the flash memory device.

In addition, if the information is stored for a long period of time in the program state, the electric field is large, which has a fatal adverse effect on the product.

An object of the present invention is to improve a flash memory cell and a method of manufacturing the same that can improve cell characteristics of a flash memory device.

The flash memory cell according to the present invention is formed in parallel in a flash memory cell in which an STI sidewall, a first polycrystalline silicon, a second oxide film, and a second polycrystalline silicon are formed on a semiconductor substrate on which an active region and a trench region are formed. A plurality of trench lines, a plurality of gate lines formed in a direction perpendicular to the trench lines, and formed between the gate lines and implanting ions into surfaces of the active region and the trench region in a direction parallel to the gate lines. And a common source region, wherein the STI sidewall is formed in a portion of the active region and in the trench region.

The active region may be a source region and a drain region.

The trench line may be parallel to the bit line direction, and the gate line may be parallel to the word line direction.

Sequentially forming a pad oxide film, a nitride film, and a TEOS film on the semiconductor substrate, patterning the pad oxide film, the nitride film, and the TEOS film as a mask to etch the semiconductor substrate to form a trench, and a part of the pad oxide film Removing a portion of the semiconductor substrate; etching the exposed portion of the semiconductor substrate by a predetermined thickness; depositing an STI sidewall on an entire surface of the semiconductor substrate upper structure; forming an insulating film on the STI sidewall; and on the nitride film Chemically polishing the TEOS film and the insulating film to be planarized, and removing the nitride film and the pad oxide film to form an isolation layer, a first oxide film on the semiconductor substrate, and a second oxide film on the first polycrystalline silicon. And forming a second polycrystalline silicon, said second polycrystalline seal Patterning the cone, the second oxide film, and the first polycrystalline silicon to form a plurality of gate lines, and etching a portion formed between the side surface of the preliminary common source region and the side surface of the gate wiring to form a common source region. And proceeding with ion implantation using a SAS mask.

The trench region may be formed by etching with an inclination of 15 to 45 degrees.

The exposed portion of the semiconductor substrate may be etched to a thickness of about 25 ~ 50Å.

The STI side wall may be formed to a thickness of about 100 ~ 300Å.

Both ends of the pad oxide layer may be etched to about 50 to 100Å.

The nitride layer and the pad oxide layer may be removed with phosphoric acid.

The trench region may be parallel to the bit line direction, and the gate line may be parallel to the word line direction.

The SAS mask may expose a portion of the gate line and a gate line adjacent to each other.

By the ion implantation, ions may be implanted into the surface of the source region and the trench region included in the common source region.

The insulating film can be HDP.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A flash memory cell and a method of manufacturing the same according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a layout view of a flash memory cell according to an embodiment of the present invention.

As shown in FIG. 1, in the flash memory cell according to the exemplary embodiment, trench lines 19 corresponding to device isolation regions are formed on the semiconductor substrate 100, and a plurality of trench lines 19 may be formed. It is formed parallel to the bit line BL direction Z. Here, the dotted line represents the boundary of the side wall inclined surface of the trench line 19.

A common source region 12 formed by implanting impurities into the word line WL is formed under the surface of the semiconductor substrate 100.

The plurality of gate lines 13 are formed in a direction perpendicular to the trench line 19, that is, in a direction parallel to the word line WL. A drain region 15 is formed in a region opposite to the common source region 12 based on the gate line 13, and a drain contact 17 is formed in part of the drain region.

The SAS mask 200 exposes a portion of the gate line 13 and between neighboring gate lines 13, and an exposed boundary line of the SAS mask 200 is connected to the gate line 13 above the gate line 13. It is arranged side by side.

Next, a method of manufacturing a flash memory cell according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a flash memory cell according to an exemplary embodiment of the present invention.

In the method of manufacturing a flash memory cell according to an embodiment of the present invention, first, as shown in FIG. 2A, a pad oxide film 2, a nitride film 3, and a TEOS film 4 are sequentially formed on a semiconductor substrate 1. Deposit.

Then, as shown in FIG. 2B, the pad oxide film 2, the nitride film 3, and the TEOS film 4 are patterned, and the semiconductor substrate 1 is etched using this as a mask to form the trench regions 5a and 5b. To form. In this case, the semiconductor substrate 1 is etched by a slop etching having an angle of about 15 to 45 degrees.

Next, as shown in FIG. 2C, both ends of the pad oxide film 2 are removed by about 50 to 100 kPa through wet etching.

Then, the semiconductor substrate 1 is etched by about 25 ~ 50Å by isotropic poly etching. This causes the vertices of the trapezoidal trench regions 5a and 5b to be curved. Subsequently, the first oxide film 7 is deposited on the sidewalls of the trench regions 5a and 5b, the pad oxide film 2, the nitride film 3, and the TEOS film 4. STI side wall 7 is formed to a thickness of about 100 ~ 300 ~.

Here, the STI sidewalls 7 are also formed in the active region that forms part of the curve of the semiconductor substrate 1. The cross section of the STI sidewall 7 formed in the active region is formed thicker than the sidewalls of the inclined trench regions 5a and 5b. As a result, the characteristics of the STI sidewall 7 for preventing damage during formation of the device isolation layer 6 are improved.

Next, a high density plasma (HDP) 6 is formed on the STI sidewall 7, and then the TEOS film 4 and the HDP 6 formed on the nitride film 3 are subjected to chemical mechamical polishing. ) And planarize.

Next, as shown in FIG. 2D, the STI sidewall 7, the nitride film 3, and the pad oxide film 2 formed on the semiconductor substrate 1 are removed using phosphoric acid. In this case, the device isolation layer 13 is formed. The device isolation layer 13 is an insulating film for preventing an electrical effect between the cell and the cell of the flash memory.

 Next, as shown in FIG. 2E, the first oxide film 8, the first polycrystalline silicon 9, the second oxide film 10, and the second polycrystalline silicon 11 are formed on the semiconductor substrate 1. These are etched to form the gate line 13. Through this process, a plurality of gate lines 13 are formed in a direction perpendicular to the trench line 19, that is, in a direction parallel to the word line WL.

Next, the device isolation layer 6 filling the common source region 12 is removed using the SAS mask 200 exposing the neighboring gate lines 13 to form the common source line 12. . Then, an ion implantation process is performed on the common source region 12 and the drain region 15.

The flash memory cell and the method of manufacturing the same according to the present invention form an active region from which a portion of the pad oxide film is removed to be curved through isotropic poly etching and form an STI sidewall thereon. Accordingly, as the deposition rate of the STI sidewall is improved, the characteristics of the STI sidewall may be improved, thereby reducing the influence of the electric field of the flash memory.

Accordingly, when the information is stored for a long time in the program state, the electric field is kept constant to stabilize the flash memory cell.                     

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims (13)

A flash memory cell in which an STI sidewall, a first polycrystalline silicon, a second oxide film, and a second polycrystalline silicon are formed on a semiconductor substrate on which active regions and trench regions are formed, A plurality of trench lines formed in parallel, A plurality of gate lines formed in a direction perpendicular to the trench lines; A common source region formed between the gate lines and implanted into the surfaces of the active region and the trench region in a direction parallel to the gate line Including, And the STI sidewall is formed in a portion of the active region and in the trench region. In claim 1, And the active region is a source region and a drain region. In claim 1, And the trench line is parallel to the bit line direction and the gate line is parallel to the word line direction. Sequentially forming a pad oxide film, a nitride film, and a TEOS film on a semiconductor substrate, Patterning the pad oxide film, the nitride film, and the TEOS film as a mask to etch the semiconductor substrate to form a trench; Removing a part of the pad oxide layer; Etching the exposed portion of the semiconductor substrate by a predetermined thickness; Depositing an STI sidewall over the semiconductor substrate superstructure; Forming an insulating film on the STI sidewall, Chemically polishing and polishing the TEOS film and the insulating film formed on the nitride film; Removing the nitride layer and the pad oxide layer to form an isolation layer; Forming a first oxide film and a second oxide film and a second polycrystalline silicon on the semiconductor substrate, Patterning the second polycrystalline silicon, the second oxide film, and the first polycrystalline silicon to form a plurality of gate lines; Etching a portion formed between the side of the preliminary common source region and the side of the gate wiring to form a common source region, and Performing Ion Implantation Using a SAS Mask Method of manufacturing a flash memory cell comprising a. In claim 4, And forming the trench region by etching at an inclination of 15 to 45 degrees. In claim 4, And exposing the exposed portion of the semiconductor substrate to a thickness of about 25 to about 50 microns. In claim 4, The STI sidewall is formed in a thickness of about 100 ~ 300 로 flash memory cell manufacturing method. In claim 4, A method of manufacturing a flash memory cell for etching both ends of the pad oxide film to about 50 ~ 100Å. In claim 4, And the nitride film and the pad oxide film are removed with phosphoric acid. In claim 4, And the trench region is parallel to the bit line direction and the gate line is parallel to the word line direction. In claim 4, And the SAS mask exposes a portion of a gate line and a gate line adjacent to each other. In claim 4, And implanting ions into a surface of the source region and the trench region included in the common source region by the ion implantation. In claim 4, And the insulating film is HDP.

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