KR20080039113A - Method for forming a resistor of flash memory device - Google Patents

Abstract

A method for forming a resistance of a flash memory device is provided to prevent electrostatic the increase of capacitance between a floating gate and a substrate by preventing boron from being injected into an active region. A cell region and a peripheral circuit region are defined on a substrate(110). A gate insulating layer, a first polysilicon layer and a pad nitride layer are formed on the substrate. The plural trenches are formed on the substrate. Wherein, an active region which is defined by the trench has wider width at the resistance region than the cell region. A leakage current prevention region is formed within the trench. A device isolation layer(117) is formed to fill up the trench. A dielectric layer(118), a second poly-silicon layer and a conductive layer(120) are formed on the entire structure. A control gate is formed in the memory cell region, and a resistance element is formed in the resistance region. A metal line is formed.

Description

METHODS FOR FORMING A RESISTOR OF FLASH MEMORY DEVICE

1 is a cross-sectional view showing a resistance element of the NAND flash memory device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of forming the resistance element illustrated in FIG. 1.

Figure 3 is a graph showing a malfunction example according to the doping concentration by the boron ion implantation process 15 carried out in Figure 2c.

4A to 4I are cross-sectional views illustrating a method of forming a resistor in a NAND flash memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10, 110: substrate 11, 111: gate insulating film

12, 19, 112, 119: polysilicon film 13, 113: pad nitride film

14, 114, 124: trench 16, 116: leakage current prevention area

17, 117: device isolation film 18, 118: dielectric film

20, 120: conductive layer 121: spacer

122, 123. 125: interlayer insulating film 126: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a resistance forming method used in a voltage divider circuit provided in a charge pump among driving circuits of a flash memory device that is a nonvolatile memory device. It is about.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the term 'program' refers to an operation of writing data to a memory cell, and 'erase' refers to an operation of removing data written to the memory cell.

As a result, a plurality of memory cells are connected in series, that is, a structure in which adjacent cells share a drain or a source with each other for high integration of a nonvolatile memory device. A NAND flash memory device forming a string has been proposed. Unlike NOR-type flash memory devices, NAND flash memory devices are memory devices that read information sequentially and use a Fowler-Nordheim (FN) tunneling scheme. The program and erase operations are performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into the floating gate.

In general, a NAND flash memory device is divided into a memory cell array region in which a plurality of memory cells for storing data are formed, and a peripheral circuit region in which a driving circuit for driving the plurality of memory cells is formed. Each of the plurality of memory cells includes a gate electrode including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate, and a source / drain region formed in a substrate exposed between the gates. Meanwhile, the driving circuit includes various signal delay circuits, high voltage stabilization circuits, and reference voltage generation circuits. In particular, it includes a charge pump that receives an external voltage and generates a higher high voltage, which charge pump essentially comprises a voltage divider circuit for distributing the voltage, which circuit comprises a resistor.

In the manufacturing process of a NAND flash memory device, a method of forming a resistor using a floating gate is generally used, instead of using a control gate functioning as a word line to reduce an area of a resistor. It is becoming.

This resistance forming method will be described with reference to FIG. 1. 1 is a cross-sectional view illustrating a resistance forming method in a NAND flash memory device according to the prior art.

Referring to FIG. 1, the resistance R of the voltage distribution circuit of the NAND flash memory device according to the related art has the same gate structure as that of the memory cell MC, that is, the tunnel oxide film 11A, the floating gate 12A, and the dielectric film ( 18), a gate structure having a laminated structure consisting of the control gate 19 and the conductive layer 20 for the cell word line is fabricated, and then the conductive layer 20, the control gate 19, and the dielectric film 18 are etched. The etched portion is formed by burying the conductive layer 21 for metal wiring.

Specifically, the description will be given with reference to FIGS. 2A to 2F.

2A to 2F are cross-sectional views illustrating a method of forming a resistor illustrated in FIG. 1, and show a method of forming a resistor of a NAND flash memory device using an ASA-STI (Advanced Self Aligned-Shallow Trench Isolation) process. It was.

First, as shown in FIG. 2A, a memory cell array region MC (hereinafter, referred to as a memory cell region) in which a plurality of memory cell regions are to be formed, and a region in which a resistance element of a voltage distribution circuit is to be formed in a peripheral circuit region. A semiconductor substrate 10 defined by R (hereinafter referred to as a resistive region) is provided.

Subsequently, the gate insulating film 11 in which FN tunneling occurs on the substrate 10 including the memory cell region MC and the resistance region R, and the polysilicon film 12 for floating gate (hereinafter, referred to as first polysilicon) Film) and the pad nitride film 13 are sequentially deposited.

Subsequently, as illustrated in FIG. 2B, the pad nitride film 13, the first polysilicon film 12, the gate insulating film 11, and the substrate 10 may be etched by performing a shallow trench isolation (STI) etching process. To form a trench 14. In this case, the trenches 14 may be formed to have different widths according to the respective regions MC and R, but the widths W1 = W2 of the active regions defined by the trenches 14 are the same. It is formed in width. As a result, the pad nitride film pattern 13A, the first polysilicon film pattern 12A (hereinafter referred to as floating gate), and the gate insulating film pattern 11A are formed.

Subsequently, as illustrated in FIG. 2C, an ion implantation process 15 using boron B is applied to the active region exposed to the inner surface of the trench 14, thereby forming the inner surface of the trench 14. The leakage current prevention region 16 is formed in the recess. Here, the leakage current prevention region 16 is formed only on the inner wall of the trench 14, but may also be formed at the bottom of the trench 14.

Subsequently, as shown in FIG. 2D, the isolation layer 17 is formed so that the trench 14 (see FIG. 2C) is completely embedded.

Subsequently, as illustrated in FIG. 2E, the pad nitride film pattern 13A (see FIG. 2D) is removed.

Subsequently, the dielectric film 18 is formed along the stepped surface of the entire structure including the device isolation film 17.

Subsequently, a control gate polysilicon film 19 (hereinafter referred to as a second polysilicon film) is formed so as to cover the top of the dielectric film 18.

Subsequently, the conductive layer 20 is formed on the second polysilicon film 19.

Subsequently, as illustrated in FIG. 2F, the conductive layer 20 and the second polysilicon film 19 are etched. As a result, a control gate is formed in the memory cell region MC, and a resistance element is formed in the resistive region R. FIG.

Subsequently, the resistive region R etches the conductive layer 20, the second polysilicon film 19, and the dielectric film 18 to form a contact hole (cotact hole, not shown) to which the floating gate 12A is exposed. do.

Subsequently, the conductive layer 21 for metal wiring is formed to fill the contact hole. As a result, the metal wiring connected to the floating gate 12A which functions as a resistance element in the resistance region R is completed.

However, the following problems occur in the method of forming a resistor of the NAND flash memory device according to the related art.

As shown in FIG. 2B, in the resistive formation method of the NAND flash memory device according to the related art, since the ASA-STI process is applied, the floating gate serving as the resistive element is defined by the trench 14, which is the same as the active region. It is formed in width. Furthermore, when the area is reduced for high integration, the size of the floating gate is also reduced, and eventually the active area is also reduced in the same way as the floating gate because the active area is defined at the same time as the floating gate in the technology using the ASA-STI process. .

Accordingly, as shown in FIG. 2C, the leakage current between the cell and the substrate due to the area reduction due to the high integration is also increased. In order to prevent the leakage current, the inside of the trench 14 after the formation of the trench 14 is increased. An ion implantation process 15 using boron is performed on the surface to form the leakage current prevention region 16 on the inner wall of the trench 14 of the memory cell region MC. At this time, the leakage current prevention region 16 is formed in the same manner as the memory cell region MC not only in the memory cell region MC but also in the region where the voltage distribution circuit is formed.

As described above, the leakage current prevention region 16 formed in the resistance region R increases the doping concentration of the active region located below the floating gate 12A, and thus is used as the floating gate 12A. And depletion capacitance between the substrate 10 and the substrate 10. As a result, the RC time (Resistance / Capacitance time) between the floating gate 12A and the substrate 10 which functions as a resistance element is increased, thereby causing a malfunction during charge pump operation, thereby causing an undesired high voltage. . Furthermore, this problem is further exacerbated when the width of the active region decreases due to high integration, because the boron is not only a sidewall of the active region during the ion implantation process 15 for forming the leakage current preventing region 16. Because it is injected into the center.

On the other hand, Figure 3 is a graph showing a malfunction example according to the doping concentration by the boron ion implantation process 15 performed in Figure 2c, the X-axis is a bias voltage (V) applied to the floating gate 12A , Y-axis represents the capacitance PF between the floating gate 12A and the substrate 10. As shown in FIG. 3, it can be seen that as the boron doping concentration increases, the capacitance between the floating gate 12A and the substrate 10 increases correspondingly.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and the resistance formation of the flash memory device according to the prior art using a floating gate formed at the same time as the active region through the ASA-STI process as a resistance element. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a resistance of a flash memory device capable of preventing an increase in RC time due to an increase in capacitance between a floating gate and a substrate.

According to an aspect of the present invention, there is provided a substrate including a memory cell region in which a memory cell is to be formed, and a resistance region in which a resistance element is to be formed in a peripheral circuit region. Forming a gate insulating film, a first polysilicon film, and a pad nitride film, and forming a plurality of trenches in the substrate, wherein the active region defined by the trench has a wider width in the resistance region than in the memory cell region. Forming a leakage current prevention region on an inner surface of the trench, forming an isolation layer to fill the plurality of trenches, removing the pad nitride film, and removing the first polysilicon. Sequentially forming a dielectric film, a second polysilicon film, and a conductive layer over the entire structure including the film; and the memory cell Inversely, the conductive layer and the second polysilicon layer are etched to form a control gate, and in the resistance region, the conductive layer, the second polysilicon layer, the dielectric layer, and the first polysilicon layer are etched to form the control gate. Forming a resistance element made of a polysilicon film, and forming a metal wiring separated from the conductive layer and the second polysilicon film and connected to the resistance element. to provide.

As described above, in the resistance formation method of a flash memory device according to the prior art, which applies an ASA-STI process and an ion implantation process for forming a leakage current prevention region on an inner wall thereof after a trench process, the ion In order to prevent a problem of increasing capacitance between the floating gate serving as a resistive element and the substrate due to boron injected to the center of the active region during the implantation process, the active region formed under the floating gate serving as the resistive element according to the present invention. By increasing the width of the substrate to be larger than the memory cell region, it is possible to prevent the boron from being injected to the center of the active region during the ion implantation process, thereby preventing an increase in capacitance between the floating gate and the substrate.

On the other hand, the floating gate or the control gate described below is not limited to the polysilicon film, any conductive film having a conductive material can be used.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same elements.

Example

4A to 4I are cross-sectional views illustrating a method of forming a resistance of a NAND flash memory device according to an exemplary embodiment of the present invention. Here, a method of forming a resistor of a NAND flash memory device using the ASA-STI process is illustrated.

First, as shown in FIG. 4A, a memory cell array region MC (hereinafter referred to as a memory cell region) in which a plurality of memory cell regions are to be formed, and a region in which a resistance element of a voltage distribution circuit is to be formed in a peripheral circuit region. A semiconductor substrate 110 defined by R (hereinafter referred to as a resistive region) is provided.

Subsequently, a gate insulating film 111 in which FN tunneling occurs on the substrate 110 including the memory cell region MC and the resistance region R, and a polysilicon film 112 for floating gate (hereinafter, referred to as a first polysilicon film) The buffer oxide film (not shown) and the pad nitride film 113 are sequentially deposited. Here, the gate insulating layer 111 is formed of a structure in which an oxide film and a nitride film are stacked to improve data retention characteristics, and the buffer oxide film is formed by the first polysilicon film 112 during the deposition process of the pad nitride film 113. It is formed to prevent it from being damaged.

Subsequently, as illustrated in FIG. 4B, an STI etching process is performed to etch the pad nitride layer 113, the buffer oxide layer, the first polysilicon layer 112, the gate insulating layer 111, and the substrate 110. (Not shown) is formed. In this case, the trenches 114 may be formed to have different widths according to the respective regions MC and R, and the widths W3 and W2 of the active regions defined by the trenches 114 may have different widths W4>. W3). Preferably, the width W4 that is at least two times larger than the width W3 of the active region of the memory cell region MC to minimize an increase in capacitance due to boron implanted during the subsequent ion implantation process 115 (see FIG. 4C). To have). That is, the width W4 of the active region of the resistance region R is large so that the profile of the resistance element 112B defined in FIG. 4F and the final leakage current prevention region 116 (see FIG. 4C) do not overlap each other. Form. As a result, the pad nitride film pattern 113A, the first polysilicon film pattern 112A (hereinafter referred to as floating gate), and the gate insulating film pattern 111A are formed.

Subsequently, as shown in FIG. 4C, the ion implantation process 115 using boron is performed to the active region exposed to the inner surface of the trench 114 to prevent the leakage current region 116 from the inner surface of the trench 114. To form. At this time, since the width W4 (see FIG. 4B) of the active region is larger in the resistance region R than that of the memory cell region MC, the profile of the leakage current prevention region 116 in the resistance region R is defined. Is distributed in the sidewall region far from the center of the active region relative to the memory cell region MC. As a result, an increase in capacitance due to boron of the leakage current prevention region 116 can be minimized.

Subsequently, as shown in FIG. 4D, a single layer film using an HDP (High Density Plasma) film alone or an HDP film and a PSZ (polisilazane) film are stacked as an insulating film for device isolation so that the trench 114 (see FIG. 4C) is completely embedded. After forming a laminated film, a chemical mechanical polishing (CMP) process is performed to form an isolation layer 117.

Subsequently, as shown in FIG. 4E, the pad nitride film pattern 113A (see FIG. 4D) is removed. In this case, the pad nitride layer pattern 113A may be removed through an etching process using phosphoric acid (H ₃ PO ₄ ).

Subsequently, a washing process is performed to remove the residue of the pad nitride film remaining without being completely removed.

Subsequently, the pad nitride layer pattern 113A may be removed to remove the exposed buffer oxide layer. In this case, the buffer oxide layer may be left as it is without being removed. In this case, the buffer oxide layer may be removed during the etching process for adjusting the effective field oxide height (EFH) of the subsequent device isolation layer 117.

Subsequently, after the photoresist film is coated on the entire structure from which the pad nitride film pattern 113A has been removed, the photoresist pattern (not shown) is sequentially formed by sequentially performing an exposure and development process (hereinafter, collectively referred to as a photo process) using a photo mask. Form. In this case, the photoresist pattern has a structure in which the peripheral circuit region including the resistance region R is closed and only the memory cell region MC is opened.

Subsequently, an etching process using the photoresist pattern as an etching mask is performed to selectively recess only the device isolation layer 117 of the memory cell region MC to a predetermined depth. As a result, the EFH of the device isolation film 117 formed in the memory cell region MC is controlled.

Next, the photoresist pattern is removed.

Subsequently, the dielectric film 118 is formed along the stepped surface of the entire structure including the device isolation film 117. In this case, the dielectric film 118 is formed in an oxide-nitride-oxide (Oxide-Nitride-Oxide) structure.

Subsequently, a control silicon polysilicon film 119 (hereinafter referred to as a second polysilicon film) is formed to cover the top of the dielectric film 118. In this case, the second polysilicon film 119 is formed to a thickness thicker than that of the floating gate 112A. In addition, the second polysilicon film 119 is formed of a doped polysilicon film doped with n-type impurities or p-type impurities.

Subsequently, the conductive layer 120 is formed on the second polysilicon film 119. At this time, the conductive layer 120 is formed of a tungsten silicide layer, tungsten or a laminated structure in which these are stacked.

Subsequently, as shown in FIG. 4F, a photo process is performed to form a control gate forming photoresist pattern (not shown), followed by an etching process using the photoresist pattern as an etching mask to form a conductive layer 120 and 2 Polysilicon film 119 is etched. As a result, a control gate is formed in the memory cell region MC, and a resistance element is formed in the resistive region R. FIG. In this case, the resistance element is formed to have a width smaller than the width of the active region, and preferably not overlapped with the leakage current prevention region 116 formed in FIG. 4C. Meanwhile, '118A' is a dielectric film pattern, '119A' is a second polysilicon film pattern, and '120A' is a conductive layer pattern. In addition, '112B' means a floating gate pattern.

Subsequently, as shown in FIG. 4G, both side walls of the gate structure including the control gate in the memory cell region MC, the floating gate pattern 112B, the dielectric layer pattern 118A, and the first region in the resistance region R are formed. 2, spacers 121 are formed on both sidewalls of the polysilicon film pattern 119A and the conductive layer pattern 120A.

Subsequently, although not shown, source / drain regions are formed in the substrate 110 exposed to both sides of the spacer 121. Of course, the source / drain regions are also formed in the peripheral circuit region.

Subsequently, an insulating film 122 (hereinafter referred to as a first interlayer insulating film) is formed so as to fill the step portion between the spacers 121. In this case, the first interlayer insulating layer 122 is formed of an oxide-based material.

Next, a CMP process is performed to planarize the first interlayer insulating film 122. In this case, the CMP process is performed until the conductive layer pattern 120A is exposed.

Subsequently, as shown in FIG. 4H, an insulating film 123 (hereinafter referred to as a second interlayer insulating film) is formed on the entire structure including the first interlayer insulating film 122.

Subsequently, an etching process is performed to form the second interlayer insulating film 123, the conductive layer pattern 120A (see FIG. 4G), the second polysilicon film pattern 119A (see FIG. 4G), and the dielectric film pattern in the resistance region R. 118A (refer to FIG. 4G) is formed to form a contact hole 124 in which the floating gate pattern 112B is exposed in the conductive layer pattern 120B, the second polysilicon layer pattern 119B, and the dielectric layer pattern 118B. .

Subsequently, as shown in FIG. 4I, an insulating film 125 (hereinafter referred to as a third interlayer insulating film) is formed along the step of the upper surface of the entire structure including the contact hole 124 (see FIG. 4H).

Subsequently, an etching process is performed to etch the third interlayer insulating layer 125. In this case, the third interlayer insulating layer 125 remains only on the inner sidewall of the contact hole 124 to expose a portion of the floating gate pattern 112B.

Subsequently, a metal wiring material is deposited so as to fill the contact hole 124 and then etched to form a metal wiring 126 electrically connected to the floating gate pattern 112B through the contact hole 124.

Through the above process, the memory cell is formed in the memory cell region MC, and the resistance element is formed in the resistive region R. FIG.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the width of the active region formed under the floating gate functioning as a resistance element of the voltage distribution circuit of the charge pump is formed by increasing the width of the active region formed in the memory cell region. During the ion implantation process to form the leakage current prevention region, the boron may be controlled to not be injected to the center of the active region, thereby preventing the capacitance from increasing between the floating gate and the substrate.

Claims (6)

Providing a substrate defined by a memory cell region where a memory cell is to be formed and a resistance region where a resistive element is to be formed in the peripheral circuit region; Forming a gate insulating film, a first polysilicon film, and a pad nitride film on the substrate; Forming a plurality of trenches in the substrate, wherein the active region defined by the trench has a wider width in the resistive region than in the memory cell region; Forming a leakage current prevention region on an inner surface of the trench; Forming an isolation layer to fill the plurality of trenches; Removing the pad nitride film; Sequentially forming a dielectric film, a second polysilicon film, and a conductive layer on the entire structure including the first polysilicon film; In the memory cell region, the conductive layer and the second polysilicon layer are etched to form a control gate, and in the resistance region, the conductive layer, the second polysilicon layer, the dielectric layer, and the first polysilicon layer are etched. Forming a resistance element made of the first polysilicon film; And Forming a metal wiring separated from the conductive layer and the second polysilicon layer and connected to the resistance element Resistance forming method of a flash memory device comprising a. The method of claim 1, And forming the active region in the resistance region at least twice as wide as in the memory cell region. The method of claim 1, Forming the metal wires, Forming a first interlayer insulating film exposing the conductive layer; Forming a second interlayer insulating film on the entire structure including the first interlayer insulating film; Etching the second interlayer insulating layer, the conductive layer, the second polysilicon layer, and the dielectric layer in the resistance region to form a contact hole through which the resistance element is exposed; Forming a third interlayer insulating film along a step of an upper surface of the entire structure including the contact hole; Etching the third interlayer insulating layer so that the third interlayer insulating layer remains on an inner sidewall of the contact hole and exposes the resistance element; And Forming the metal interconnection in which the contact hole is buried and connected to the resistance element Resistance forming method of a flash memory device comprising a. The method of claim 1, After forming the resistive element, the memory cell region is formed on both sidewalls of the conductive layer and the second polysilicon layer, and in the resistive region, the conductive layer, the second polysilicon layer, the dielectric layer, and the And forming spacers on both side walls of the resistive element, respectively. The method of claim 1, And the resistance element constitutes a voltage distribution circuit of a charge pump. The method of claim 1, And forming the resistor and the leakage current preventing region so that they do not overlap each other.

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