CN113690173B

CN113690173B - Three-dimensional memory and preparation method thereof

Info

Publication number: CN113690173B
Application number: CN202111052991.4A
Authority: CN
Inventors: 陈亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2024-04-05
Anticipated expiration: 2041-09-07
Also published as: CN113690173A

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory includes: a first semiconductor device comprising: a substrate; a plurality of peripheral devices, a portion of the peripheral devices being located in a well of the substrate; a semiconductor layer disposed adjacent to the substrate; a plurality of memory string structures located on the semiconductor layer and electrically coupled to the semiconductor layer; and a deep trench isolation structure comprising: a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; a second portion extending through the substrate and surrounding the well to electrically isolate the peripheral devices from each other. The three-dimensional memory and the preparation method thereof can simplify the isolation structure and the preparation process thereof, reduce the manufacturing cost, improve the performance of peripheral devices and avoid the problem of punch-through between the peripheral devices. In addition, interactions between peripheral devices and multiple memory string structures are weakened or even avoided.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a three-dimensional memory and a method of manufacturing the same.

Background

In a three-dimensional memory (3D NAND) based on the xcharging architecture, peripheral circuits responsible for data I/O and memory cell operation are formed on the same substrate, while a memory string structure is formed on another substrate. After the two semiconductor structures are prepared, the two semiconductor structures are connected in a bonding way so as to enable the memory string structure and the peripheral circuit to be connected.

However, as the number of stacked layers of the 3D NAND technology increases, the size of the semiconductor structure used to form the memory string structure decreases while achieving the same memory capacity. Accordingly, the semiconductor structure having peripheral circuits, which is bonded to the semiconductor structure having the memory string structure, is also required to be reduced, which affects the arrangement formation of the peripheral circuits and thus the circuit-on performance of the peripheral circuits and the memory string structure.

In addition, some peripheral circuits (e.g., bit line drivers for page buffers) require the use of high voltages to support storage functions, such as erasing and programming memory cells. However, as the size of peripheral circuit chips becomes smaller, isolation between individual peripheral devices becomes complex, which is detrimental to achieving a desired isolation effect between peripheral devices and/or between peripheral devices and a memory string structure.

Disclosure of Invention

The present application provides a three-dimensional memory, the three-dimensional memory comprising: a first semiconductor device comprising: a substrate; a plurality of peripheral devices, a portion of the peripheral devices being located in a well of the substrate; a semiconductor layer disposed adjacent to the substrate; a plurality of memory string structures located on the semiconductor layer and electrically coupled to the semiconductor layer; and a deep trench isolation structure comprising: a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; a second portion extending through the substrate and surrounding the well to electrically isolate the peripheral devices from each other.

In some embodiments, the peripheral devices include high voltage MOS devices.

In some embodiments, the substrate includes a first side formed with a plurality of peripheral devices, and a second side opposite the first side, wherein the deep trench isolation structure extends from the second side through the substrate and/or the semiconductor layer.

In some embodiments, the three-dimensional memory further comprises: and the back-end-of-line interconnect layer is positioned on the second side of the substrate, and the deep trench isolation structure sequentially penetrates through the back-end-of-line interconnect layer, the substrate and/or the semiconductor layer from the second side.

In some embodiments, the three-dimensional memory further comprises: shallow trench isolation structures located between the well and the deep trench isolation structures extend in the substrate and through a portion of the substrate.

In some embodiments, the shallow trench isolation structure extends from the first side to the second side and through a portion of the substrate.

In some embodiments, the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

In some embodiments, the critical dimensions of the shallow trench isolation structures are smaller than the critical dimensions of the deep trench isolation structures.

In some embodiments, a second semiconductor device is located on a side remote from the substrate and is bonded to the first semiconductor device, wherein the second semiconductor device includes a plurality of low-voltage MOS devices and/or ultra-low voltage MOS devices.

The application also provides a preparation method of the three-dimensional memory. The preparation method comprises the following steps: forming a plurality of peripheral devices in a first region of a substrate, a portion of the peripheral devices being located in a well of the substrate; forming a plurality of memory structures in a second region of the substrate; removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures; and forming a deep trench isolation structure, wherein the deep trench isolation structure comprises: a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion penetrating the substrate and disposed around the well to electrically isolate the peripheral devices from each other.

In some embodiments, removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures includes: a portion of the substrate corresponding to the first region is removed to expose the well, wherein a thickness of the semiconductor layer is the same as a thickness of the well.

In some embodiments, the peripheral devices include high voltage MOS devices.

In some embodiments, the substrate includes a first side formed with a plurality of peripheral devices, and a second side opposite the first side, wherein the step of forming the deep trench isolation structure includes: forming a first trench penetrating the substrate and/or the semiconductor layer from the second side; and filling dielectric material in the first trench to form a deep trench isolation structure.

In some embodiments, the step of forming a first trench from the second side through the substrate and/or the semiconductor layer comprises: forming a back-end-of-line interconnect layer on a second side of the substrate; and forming a first trench penetrating the back-end-of-line interconnect layer and the substrate and/or semiconductor layer in sequence from the second side.

In some embodiments, prior to the step of forming the deep trench isolation structure, the method further comprises: shallow trench isolation structures are formed, wherein the shallow trench isolation structures are located between the well and the deep trench isolation structures, extend in the substrate and through a portion of the substrate.

In some embodiments, the substrate includes a first side formed with a plurality of peripheral devices, and a second side opposite the first side, wherein the step of forming the shallow trench isolation structure includes: forming a second trench extending from the first side to the second side and through a portion of the substrate; and filling dielectric materials in the second trenches to form shallow trench isolation structures.

In some embodiments, the memory string structure includes an outer wall structure of the memory layer and the channel layer from outside to inside, and the memory string structure extends into the substrate, wherein the step of removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures includes: removing a portion of the memory layer of the memory string structure extending into the substrate to expose the channel layer; and forming a semiconductor layer covering the channel layer.

According to the three-dimensional memory and the preparation method thereof, the deep trench isolation structure is used for providing electrical isolation between a plurality of peripheral devices and between the peripheral devices and a plurality of memory string structures, so that the formation of isolation structures such as deep N-well and high-doping concentration areas can be avoided, the isolation structures and the preparation process thereof can be simplified, and the manufacturing cost is reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep groove isolation structure divides each peripheral device into relatively independent devices, so that the problem of punch-through between the peripheral devices can be avoided. In addition, since the deep trench isolation structure has a relatively good electrical isolation effect, the interaction between the peripheral device and the memory string structure is weakened or even avoided.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present application;

FIG. 2 is a schematic top view of a portion of a three-dimensional memory according to an embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a peripheral device of a prior art three-dimensional memory;

FIG. 4 is a schematic cross-sectional view of a three-dimensional memory according to another embodiment of the present application;

FIG. 5 is a schematic top view of a portion of a three-dimensional memory according to another embodiment of the present application;

FIG. 6 is a partial enlarged view of the three-dimensional memory according to FIG. 4;

FIG. 7 is a flow chart of a method of fabricating a three-dimensional memory according to an embodiment of the present application; and

fig. 8A to 8E are process cross-sectional views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes," "including," and/or "having," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

The description herein refers to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function and shape and dimensional deviations, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the locations of the components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying structure or superstructure, or can have a range less than the underlying structure or superstructure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically and/or along tapered surfaces. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, and/or thereunder. The layer can comprise a plurality of layers.

Fig. 1 is a schematic cross-sectional view of a three-dimensional memory 10 according to an embodiment of the present application. Fig. 2 is a schematic top view of a portion of a three-dimensional memory 10 according to an embodiment of the present application. Wherein the peripheral devices 120-2 and 120-3 shown in fig. 1 may have a cross-sectional structure along a cross-sectional line BB' in fig. 2. As shown in fig. 1 and 2, the three-dimensional memory 10 includes: a substrate 110, a semiconductor layer 136, a plurality of peripheral devices 120, a plurality of memory string structures 131, a deep trench isolation structure 140. A portion of peripheral device 120 is located in well 121 of substrate 110. The semiconductor layer 136 may be disposed adjacent to the substrate 110. A plurality of memory string structures 131 are located on semiconductor layer 136 and are electrically coupled to semiconductor layer 136. The deep trench isolation structure 140 includes a first portion 141 and a second portion 142, wherein the first portion 141 extends through the substrate 110 and/or the semiconductor layer 136 to electrically isolate the semiconductor layer 136 from the substrate 110. The second portion 142 extends through the substrate 110 and is disposed around the well 121 to electrically isolate the plurality of peripheral devices 120 from one another.

The substrate 110 may include silicon (e.g., monocrystalline silicon, polycrystalline silicon, doped silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, group III-V compound semiconductors, and any other suitable materials.

At least a portion of the plurality of peripheral devices 120 (e.g., 120-1, 120-2, 120-3, 120-4, 120-5) are located in the well 121 of the substrate 110. Peripheral devices 120 may include any suitable semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), bipolar Junction Transistors (BJTs), diodes, resistors, inductors, capacitors, and the like. In semiconductor devices, P-type MOSFETs and/or N-type MOSFETs (i.e., CMOS) are used herein as examples of peripheral devices 120, as they are widely implemented in logic circuit designs.

In some embodiments, where peripheral device 120 is a P-type MOSFET and/or an N-type MOSFET, the P-type MOSFET is located in an N-type doped well of substrate 110, the N-type MOSFET is located in a P-type doped well of substrate 110, and the N-type doped well and the P-type doped well may be referred to as N-well 121-2 and P-well 121-3, respectively. The dopant profile and concentration of well 121 affects the device characteristics of peripheral device 120. For MOSFET devices with low threshold voltages (Vth), the well 121 is doped at a lower concentration to form a low voltage P-well or a low voltage N-well. For MOSFET devices with high threshold voltages, the well 121 is doped at a higher concentration to form a high voltage P-well or a high voltage N-well, thereby forming a high voltage P-type MOSFET in the high voltage N-well and a high voltage N-type MOSFET in the high voltage P-well.

In some embodiments, N-type dopants such As phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof may be used to form N-well 121-2 in substrate 110. Similarly, a P-type dopant, such as boron (B), may be used to form P-well 121-3 in substrate 110. In addition, the doping of dopants may be achieved by ion implantation, activation annealing, and the like.

In some embodiments, the P-type MOSFET and/or the N-type MOSFET may include a gate stack 122 (e.g., 122-2). Gate stack 122 is located in substrate 110 with N-well 121-1 and/or P-well 121-2 away from above substrate 110. The gate stack 122 may include a gate dielectric layer and a gate conductive layer sequentially disposed in a direction away from the substrate 110. The material of the gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, and lanthanum oxide. The material of the gate conductive layer may include a metal material such as tungsten, cobalt, nickel, copper, or aluminum. Alternatively, the material of the gate conductive layer may also include polycrystalline semiconductor materials such as polysilicon, poly-germanium-silicon, conductive materials such as titanium nitride, tantalum nitride, and any other suitable materials. Alternatively, the polycrystalline semiconductor may be combined with any suitable type of dopant, such as boron, phosphorus, arsenic, and the like. In addition, the process of forming the gate dielectric layer and the gate conductive layer may include Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), sputtering, thermal oxidation/nitridation, or any combination thereof.

In some embodiments, the P-type MOSFET and/or the N-type MOSFET may include isolation sidewalls 123. Isolation sidewalls 123 are disposed around the gate stack 122 and expose a surface of the gate stack 122 remote from the substrate 110. The material of the isolation sidewall 123 may include silicon oxide, silicon nitride, silicon oxynitride, or any combination of dielectric materials. And the dielectric material may be applied to the gate stack 122 using methods such as CVD, PVD, ALD, sputtering, or a combination thereof. Further, an anisotropic dry etch process such as Reactive Ion Etching (RIE) may be employed to remove portions of the dielectric material located on the surface of the gate stack 122 remote from the substrate 110, thereby exposing the surface of the gate stack 122 remote from the substrate 110 to form the isolation sidewalls 123.

In some embodiments, peripheral device 120 further includes source/drain 124 located on both sides of gate stack 122 and in well 121. The source/drain 124 is doped with a high concentration of dopant. For an N-type MOSFET, the dopant of the source/drain 124 may include an N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof. For a P-type MOSFET, the dopant of the source/drain 124 may include a P-type dopant such as boron. In addition, the doping of the dopants may be achieved by ion implantation and activation annealing, etc., or by in situ doping during the preparation of the epitaxial layer of the MOSFET active area. The source/drain 124 of the peripheral device 120 may be the same material as the substrate 110. Alternatively, the material of the source/drain 124 of the peripheral device 120 may be different from the material of the substrate 110 to improve the electrical performance of the peripheral device 120.

In some embodiments, peripheral devices 120 (e.g., high voltage N-type MOSFETs and/or high voltage P-type MOSFETs) may have Lightly Doped Drain (LDD) regions 125 between drain 124 and gate stack 122. The lightly doped drain region 125 reduces the peak electric field when the drain 124 is applied with a high voltage, thereby reducing the hot carrier injection effect.

It should be understood that peripheral device 120 is not limited to MOSFETs. The structure of other peripheral devices (e.g., diodes, resistors, inductors, BJTs, etc.) may be formed simultaneously during the process of fabricating the MOSFET by different mask designs and layouts.

In some embodiments, the plurality of peripheral devices 120 may be used to form any digital, analog, and/or mixed signal circuit for peripheral circuit operation. The peripheral circuitry may, for example, perform row/column decoding, timing and control, reading, writing, and erasing data of the memory cells, and the like.

The semiconductor layer 136 is disposed adjacent to the substrate 110. In some embodiments, at least one of the two opposing surfaces of semiconductor layer 136 is disposed flush with at least one of the two opposing surfaces of substrate 110. Alternatively, in the embodiments of the present application, the thicknesses of the semiconductor layer 136 and the substrate 110 are the same, so that two opposite surfaces of the semiconductor layer 136 are disposed flush with two opposite surfaces of the substrate 110, respectively. In some embodiments, the semiconductor layer 136 may be formed as part of the semiconductor material substrate 110 and subjected to, for example, a doping process. Alternatively, the semiconductor layer 136 may be formed in a different process step from the substrate 110, which is not specifically limited herein.

In some exemplary embodiments, the semiconductor layer 136 may include a semiconductor material having an N-type dopant with a uniform doping concentration, such as single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. The N-type dopant may include, for example, phosphorus, arsenic, antimony, or any combination thereof, and the doping of the dopant may be accomplished using ion implantation and activation annealing processes.

A plurality of memory string structures 131 may constitute a memory string structure array. Each memory string structure 131 may be located above the semiconductor layer 136 and extend into the semiconductor layer 136, and a portion of the memory string structure 131 extending into the semiconductor layer 136 may be electrically coupled with the semiconductor layer 136. In some embodiments, as shown in fig. 1, the three-dimensional memory 10 may include a stacked structure 132 on a semiconductor layer 136. The stacked structure 132 may include dielectric layers 133 and conductive layers 134 alternately stacked in a direction perpendicular to the semiconductor layer 136. And the memory string structure 131 is formed in the stacked structure 132.

In some embodiments, the dielectric layer 133 in the stack structure 132 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The conductive layer 134 in the stack structure 132 may be made of a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. And dielectric layer 133 and conductive layer 134 may be formed using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The number of stacked layers of the dielectric layer 133 and the conductive layer 134 may be 8, 32, 64, 128, etc., and the greater the number of stacked layers of the dielectric layer 133 and the conductive layer 134, the higher the integration of the memory cell. Conductive layer 134 may serve as a word line for memory cells in memory string structure 131.

In some embodiments, a plurality of memory string structures 131 (e.g., 131-1, 131-2, 131-3, 131-4) may be two-dimensionally arranged on a plane parallel to the semiconductor layer 136. Each of the memory string structures 131 may include a plurality of memory cells arranged one-dimensionally in a direction perpendicular to the semiconductor layer 136, such that the memory cells are arranged three-dimensionally in the corresponding space of the semiconductor layer 136. The memory string structure 131 is disposed through the stacked structure 132 and extends in the direction of the semiconductor layer 136. The memory string structure 131 may have a general shape of a cylinder, a cone, a cuboid, and may include an outer wall structure of a memory layer 1311 and a channel layer 1312 disposed sequentially from outside to inside. Alternatively, a portion of the channel layer 1312 in the memory string structure 131 extending to the semiconductor layer 136 may be in contact with the semiconductor layer 136 to generate electrical coupling. Alternatively, the channel layer 1312 may be electrically coupled with the semiconductor layer 136 through an epitaxial layer (not shown) of the memory string structure 131 adjacent to the semiconductor layer 136.

It should be appreciated that where the plurality of memory string structures 131 are electrically coupled in common with the semiconductor layer 136, the N-doped semiconductor layer 136 can be used to effect performing a GIDL erase operation for memory cells in the plurality of memory string structures 131. It is noted that the semiconductor layer 136 may also include a semiconductor material having a P-type dopant with a uniform doping concentration. The P-doped semiconductor layer 136 can be used to enable performing a P-well bulk erase operation for memory cells in the plurality of memory string structures 131.

In some embodiments, the memory layer 1311 may be a composite layer structure of a blocking layer, a charge trapping layer, and a tunneling layer. The materials of the blocking layer, the charge trapping layer, and the tunneling layer may be silicon oxide, silicon nitride, and silicon oxide in this order, thereby forming the memory layer 1311 having an ONO structure. The material of the channel layer 1312 may be a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon. The memory string structure 131 may be formed through a photolithography and etching process and a thin film deposition process.

It will be appreciated that the portion of the memory layer 1311 and channel layer 1312 in the memory string structure 131 corresponding to each conductive layer 134 and the conductive layer 134 together form a memory cell. The conductive layer may correspond to a control terminal of the memory cell. The plurality of memory cells in the memory string structure 131 are arranged in series in a direction perpendicular to the semiconductor layer 136 and share the channel layer 1312.

In some embodiments, the memory string structure 131 may further include a channel plug 135 at an end of the memory string structure 131 remote from the semiconductor layer 136. The channel plug 135 may be made of the same semiconductor material as the channel layer 1312 and is in contact with the channel layer 1312. The channel plug 135 may function as a drain of the memory string structure 131.

In some embodiments, the step structure is disposed at an edge region of the stacked structure 132, and may be formed by performing a multiple "trim-etch" cycle process on the plurality of dielectric layers 133 and the plurality of conductive layers 134 that are alternately stacked. Wherein the exposed conductive layer 134 of the stair step structure in a direction parallel to the semiconductor layer 136 may serve as an electrical connection contact area for a conductive via (not shown). Since the conductive layer 134 can be used as a word line of the memory cells in the memory string structure 131, the conductive layer 134 can be connected to a plurality of peripheral devices in the peripheral circuit through conductive channels to control the memory cells to realize the functions of storing and reading data.

As shown in fig. 1 and 2, the deep trench isolation structure 140 includes a first portion 141 and a second portion 142. The first portion 141 may extend through the substrate 110 and/or the semiconductor layer 136 near the interface of the substrate 110 and the semiconductor layer 136 to electrically isolate the semiconductor layer 136 from the substrate 110. Since the first portion 141 of the deep trench isolation structure 140 completely penetrates the substrate 110 and/or the semiconductor layer 136, interactions with peripheral devices during, for example, erase operations performed on memory cells in the memory string structure 131 using the semiconductor layer 136 may be avoided, thereby enabling the formation of a three-dimensional memory device compatible with GIDL and/or P-well bulk erase operations using the arrangement of memory string structures and peripheral devices described above. Similarly, second portion 142 extends completely through substrate 100 and is disposed around well 121 to electrically isolate the plurality of peripheral devices 120 from one another.

In some embodiments, the deep trench isolation structures 140 may be formed by patterning the substrate 110 and/or the semiconductor layer 136 through photolithography and etching processes, filling an insulating material, and a mechanical chemical polishing (CMP) process. The insulating material for the deep trench isolation structures 140 may include silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, or any combination thereof. And the insulating material may be filled using a process such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof.

Fig. 3 is a schematic cross-sectional view of a peripheral device of a conventional three-dimensional memory. As shown in fig. 3. In the prior art, in the case of a P-type substrate 1 as a carrier for peripheral devices 3, shallow Trench Isolation (STI) 2 is typically employed to achieve electrical isolation of peripheral devices 3 on the P-type substrate 1. For example, in the case where the peripheral device 3 is a high voltage N-type MOSFET, in order to provide electrical isolation of the peripheral device 3 from the P-type substrate 1, a deep N-well 6 may be formed below the high voltage P-well 4 such that a PN junction is formed between the high voltage P-well 4 and the deep N-well 6 and between the deep N-well 6 and the P-type substrate 1. The shallow trench isolation structure 2 is typically 3000-4000A deep and extends into the high voltage P-well 4 in the direction of the P-type substrate 1. In order to provide electrical isolation between adjacent peripheral devices 3, the concentration of dopant ions may be increased in the region 5 of the high voltage P-well 4 under the shallow trench isolation structure 2 between adjacent peripheral devices 3 to increase the drain voltage between adjacent peripheral devices 3, thereby achieving complete electrical isolation between adjacent peripheral devices 3.

However, in the existing isolation technology to solve the problem of complete isolation between peripheral devices, the complexity of preparing the peripheral devices is increased due to the need of matching multiple isolation structures such as deep N-well, shallow trench isolation structures, and high doping concentration regions. At the same time, the number and types of masks used to form deep N-wells, shallow trench isolation structures, and high doping concentration regions, etc. are increased, thereby increasing manufacturing costs. In addition, the deep N well structure is added, so that the substrate depth required by the peripheral device is increased, and the performance of the finally formed peripheral device is affected. On the other hand, in the case where the substrate for forming the peripheral device is brought into contact with the semiconductor layer for forming the memory string structure, the isolation effect of the shallow trench isolation structure also causes the peripheral device and the memory cells in the memory string structure to affect each other when, for example, an erase operation is performed.

According to the three-dimensional memory, the deep trench isolation structure is used for providing electrical isolation between a plurality of peripheral devices and a plurality of memory string structures, the formation of deep N-well, high doping concentration areas and other structures can be avoided, the isolation structure and the preparation process thereof can be simplified, and the manufacturing cost is reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep trench isolation structure divides each peripheral device into relatively independent devices, so that a punch-through problem (punch-through) between the peripheral devices can be avoided. In addition, since the deep trench isolation structure has a relatively good isolation effect, interactions between the peripheral devices and the plurality of memory string structures are weakened or even avoided.

In some embodiments, as shown in fig. 1 and 2, deep trench isolation structures 140 may extend from a second laterally opposite first side of substrate 110 and/or semiconductor layer 136 where peripheral devices 120 are not formed, and through substrate 110 and/or semiconductor layer 136. In this embodiment, since the deep trench isolation structure 140 is formed extending from the backside (second side) of the substrate 110 toward the first side, the deep trench isolation structure may be referred to as a "Backside Deep Trench Isolation (BDTI) structure. The critical dimension of the deep trench isolation structure 140 at the first surface 101 may be smaller than the critical dimension at the second surface 102, so that the spacing distance between adjacent peripheral devices may be reduced on the premise of achieving complete isolation between adjacent peripheral devices, thereby increasing the integration level of the peripheral devices.

In some implementations, the three-dimensional memory 10 can also include a back end of line Cheng Hulian (BEOL) layer 160. The back-end-of-line interconnect layer 160 is located on the second side of the substrate 110 and/or semiconductor 136 and is in contact with the second surface 102. The back-end-of-line interconnect layer 160 is used to implement pad extraction to pass electrical signals of the peripheral device 120 and/or the memory string structure 131. The back-end-of-line interconnect layer 160 may include through contacts (not shown) electrically connected to at least a portion of the peripheral device 120 and/or the memory string structure 131 and dielectric isolation between the through contacts. Wherein the material of the through contact may comprise a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The material of the dielectric isolation may comprise a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Alternatively, the deep trench isolation structures 140 may penetrate the dielectric isolation structures in the back-end-of-line interconnect layer 160 from the second side of the substrate 110 and/or the semiconductor layer 136 and be formed simultaneously with the penetrating contacts, thereby making the fabrication process of the deep trench isolation structures compatible with the fabrication process of the back-end-of-line interconnect layer 160. It is to be understood that the above description is given as to the structure of the first semiconductor device 100 in the three-dimensional memory 10. In some embodiments, the three-dimensional memory 10 may further include a second semiconductor device 200. The second semiconductor device 200 is located at a side remote from the substrate 110 and is bonded to the first semiconductor device 100. The second semiconductor device 200 may include a plurality of peripheral devices formed therein. The plurality of peripheral devices in the second semiconductor device 200 may collectively constitute a digital, analog, and/or digital-analog hybrid circuit module that implements various functions. Illustratively, the circuit module may include a page buffer, an address decoder, and a read amplifier. Alternatively, the first semiconductor device 100 may be used to form a high-voltage MOS device, and the second semiconductor device 200 may be used to form a low-voltage MOS device and/or an ultra-low voltage MOS device. The arrangement is beneficial to the process compatibility of the high-voltage MOS device and the memory string structure in the preparation process.

Fig. 4 is a schematic cross-sectional view of a three-dimensional memory 10' according to another embodiment of the present application. Fig. 5 is a schematic top view of a portion of a three-dimensional memory 10' according to another embodiment of the present application. Wherein the peripheral devices 120-2 and 120-3 shown in fig. 4 may have a cross-sectional structure along the cross-sectional line BB' in fig. 5. As shown in fig. 4 and 5, in this embodiment, the three-dimensional memory 10' further includes a shallow trench isolation structure 150 as compared to the three-dimensional memory 10. Since other structures in the three-dimensional memory 10' are identical to the three-dimensional memory 10 and the same reference numerals are used to designate the same structures, the description thereof is omitted herein.

In some embodiments, shallow trench isolation structures 150 may be located between well 121 and deep trench isolation structures 141 and disposed around well 121. Shallow trench isolation structures 150 extend in substrate 110 and through portions of substrate 110. Wherein shallow trench isolation structures 150 are disposed around wells 121 (active regions) of peripheral device 120 for optimizing the corner rounding during the process of forming the active regions of peripheral device 120, thereby avoiding that peripheral device 120 affects the performance of the peripheral device due to the corner rounding problem of the active regions. The shallow trench isolation structure 150 may be formed by patterning the substrate 110 through photolithography and etching processes, filling an insulating material, and mechanochemical polishing processes. The insulating material for the shallow trench isolation structure 150 may include silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, or any combination thereof. And the insulating material may be filled using a process such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof. Wherein the critical dimension of the shallow trench isolation 150 decreases gradually in a direction away from the first surface 101.

In some embodiments, the shallow trench isolation structure 150 may be formed extending from a first side of the substrate 110 where the peripheral devices 120 are formed to a second side. It should be noted that, in this embodiment, since the function of the shallow trench isolation structure 150 is to optimize the rounded corners during the process of forming the active region of the peripheral device 120, the shallow trench isolation structure 150 extends from the first side to the second side to a depth less than 3000-4000A of the conventional shallow trench isolation structure. Alternatively, in the present embodiment, the shallow trench isolation structure 150 has a depth of about 1000A. In addition, the shallow trench isolation structures 150 may be formed simultaneously during the process of forming the peripheral device 120.

Fig. 6 is a partial enlarged view of the three-dimensional memory 10' shown in fig. 4. As shown in fig. 6, in some embodiments, there is a predetermined distance l, e.g., less than 150nm, between the shallow trench isolation structure 150 and the deep trench isolation structure 140 at the first surface 101. The shallow trench isolation structure and the deep trench isolation structure are arranged at a preset distance, so that the mutual influence between the shallow trench isolation structure and the deep trench isolation structure formed subsequently can be avoided.

In some embodiments, as shown in fig. 6, a critical dimension s of the shallow trench isolation structure 150 is less than a critical dimension d of the deep trench isolation structure 140 at the first surface 101. Illustratively, the critical dimension s of the shallow trench isolation structure 150 may be 50nm and the critical dimension d of the deep trench isolation structure 140 may be 200nm. The critical dimension of the shallow trench isolation structure is smaller than that of the deep trench isolation structure, so that enough process windows can be provided for the deep trench isolation structure formed later, and the mutual influence between the shallow trench isolation structure and the deep trench isolation structure is avoided.

Fig. 7 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application. Fig. 8A to 8E are schematic process cross-sectional views of a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application. The method 1000 of fabricating a three-dimensional memory is used to form a three-dimensional memory of any of the implementations described hereinabove. As shown in fig. 7, the preparation method 1000 may include steps S110 to S140. It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 7.

A plurality of peripheral devices are formed in a first region of the substrate at step S110, a portion of the peripheral devices being located in a well of the substrate, as shown in fig. 8A, the substrate 110 may include silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, gallium nitride, silicon carbide, glass, III-V compound semiconductors, or any combination thereof.

In some embodiments, the process thereof is described in detail taking the formation of P-type and/or N-type MOSFETs as examples. An N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof may be doped into the N-well 121-2 formed in the substrate 110 and/or a P-type dopant such as boron may be doped into the P-well 121-3 formed in the substrate 110 using ion implantation and activation annealing.

In some embodiments, the substrate 110 may be patterned, filled with an insulating material, and a mechanochemical polishing process using photolithography and etching processes to form shallow trench isolation structures 150 surrounding wells 141 (active areas) of the peripheral devices 120 on the substrate 110. The material of the shallow trench isolation structure 150 may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, and any combination thereof.

In some embodiments, MOSFET structures such as gate stack 122, isolation sidewalls 123, source/drain 124, and lightly doped drain region 125 may be formed using photolithography and etching processes, thin film deposition processes such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation, and doping processes such as ion implantation. Since the structure and the forming process of the peripheral device 120 are described in detail above, the description thereof is omitted herein.

In step S120, a plurality of memory string structures are formed in a second region of the substrate. As shown in fig. 8B, in some embodiments, this step may further comprise: a stack structure 132 is formed on the second region A2 of the substrate 110. Specifically, the alternately stacked dielectric layers 133 and sacrificial layers (not shown) may be formed using a thin film deposition process such as CVD, PVD, ALD, sputtering, and any combination thereof. The dielectric layer 133 and the sacrificial layer may have different etch selectivity, and the sacrificial layer may be removed and replaced with a conductive material during a subsequent process to form the conductive layer 134. Illustratively, the material of the dielectric layer 133 may include silicon oxide and the material of the sacrificial layer may include silicon nitride. It should be understood that while the present application employs an implementation in which the sacrificial layer is subsequently replaced with a filled conductive material to form the conductive layer, the implementation in which the conductive layer is formed in the present application is not limited thereto, and may also be implemented in a manner such as directly alternating the dielectric layer and the conductive layer.

In some embodiments, a stepped structure may be formed at an edge region of the stacked structure 132 corresponding to the second region A2 by performing a multiple "trim-etch" cyclic process to the plurality of dielectric layers 133 and the plurality of sacrificial layers which are alternately stacked.

In some embodiments, a plurality of memory string structures 131 may be formed within stacked structure 132 using, for example, a dry or wet etching process, and a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, openings extending into substrate 110 may be formed within stacked structure 132 using, for example, a dry or wet etch process. Further, a memory layer 1311 including a barrier layer, a charge trapping layer, and a tunneling layer, and a channel layer 1312 may be sequentially formed within the opening using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Illustratively, the materials of the blocking layer, the charge trapping layer, and the tunneling layer within the memory layer 1311 may include silicon oxide, silicon nitride, and silicon oxide, in that order. The material of the channel layer 1312 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon, and any combination thereof.

In some embodiments, a gate slit extending into the substrate 110 may be formed within the stack structure 132, which may extend in the x-direction of the substrate 110, using, for example, a dry or wet etching process. Further, the entire sacrificial layer may be removed using, for example, a wet etch process to form a plurality of sacrificial gaps using the gate gap formed as a channel for the etchant. Further, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form conductive layer 134 within the sacrificial gap. Alternatively, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to first form an isolation layer within the gate slit and refill a conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide or any combination thereof to form the gate slit structure 137 as a common source electrical connection structure for the plurality of memory string structures 131. Wherein the material of the isolation layer may comprise a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

It is understood that the above-described process steps may be a method of forming the first semiconductor device 100. The second semiconductor device 200 may be formed using any known process method and may be processed in parallel with the first semiconductor device 100 to improve production efficiency. Since the structure of the second semiconductor device 200 is described above, the description is omitted here. The following steps may be a subsequent process for the first semiconductor device 100 after the first semiconductor device 100 and the second semiconductor device 200 are bonded.

In removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures at step S130, a portion of the substrate 110 corresponding to the second region A2 may be removed from a side of the substrate 110 where the memory string structures 131 are not formed, using, for example, a dry or wet etching process, to expose the memory string structures 131 extending into the substrate 110. Further, the same process may be used to remove the memory layer 1311 of the exposed portion of the memory string structure 131 to further expose the functional layer 1312 of the memory string structure 131. Further, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form the semiconductor layer 136 in the second region A2 where the substrate 110 is not removed to cover the memory string structure 131 and to contact the channel layer 1312 of the memory string structure 131 with the semiconductor layer 136. The semiconductor layer 136 may have the same or different semiconductor material as the substrate 110, such as single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. The semiconductor layer 136 may be used to form a body bias for the plurality of memory string structures 131 to perform the auxiliary GIDL and/or P-well erase operations.

In some embodiments, after the formation of the semiconductor layer 136, a CMP process may be used to thin the semiconductor layer 136 and the substrate 110. Alternatively, the substrate 110 and the semiconductor layer 136 may be thinned to the thickness of the well 121. In other words, after the substrate 110 and the semiconductor layer 136 are subjected to the thinning process, the substrate 110 may be made to correspond to the well 121 in the thickness direction.

Alternatively, as shown in fig. 8C, in step S130, during a process of removing a portion of the substrate 110 corresponding to the second region A2 of the substrate 110 'from a side of the substrate 110' where the memory string structure 131 is not formed to expose the memory string structure 131 extending into the substrate 110, a portion of the substrate 110 corresponding to the first region A1 may be removed using the same process to expose the well 121. In other words, the process of removing a portion of the substrate 110 corresponding to the first region A1 may make the thickness of the portion of the substrate 110 corresponding to the first region A1 the same as the thickness of the well 121. Further, as shown in fig. 8D, in a process of forming the semiconductor layer 136 in the second region A2 where the substrate 110 is not removed to cover the memory string structure 131 and bringing the channel layer 1312 of the memory string structure 131 into contact with the semiconductor layer 136, the thickness of the semiconductor layer 136 and the well 121 may be made the same, i.e., the thickness of the remaining portion of the substrate 110 corresponding to the first region A1, by the process parameters.

Forming a deep trench isolation structure at step S140, wherein the deep trench isolation structure comprises: a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; a second portion, disposed through the substrate and around the well to electrically isolate the peripheral devices, as shown in fig. 8E, may, in some embodiments, comprise: the back-end-of-line interconnect layer 160 is formed. Specifically, the semiconductor structure formed after the above process may be flipped over to perform a subsequent process on the back of the substrate 110. A thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a dielectric fill layer on the second side of the substrate 110, and the material of the dielectric fill layer may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Further, photolithography and etching processes as well as thin film deposition processes may be employed to form through contacts that electrically connect with at least a portion of peripheral device 120 and/or plurality of memory string structures 131. The material of the through contact may include a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof.

Further, the same process may be used to form deep trench isolation structures 140 extending from a second side of the substrate 110 to an opposite first side and sequentially through the back-end-of-line interconnect layer 160 and the substrate 110 and/or semiconductor layer 136, while forming the through contacts. Since the deep trench isolation structure 140 is formed extending from the backside (second side) of the substrate 110 toward the first side, the deep trench isolation structure may be referred to as a "backside deep trench isolation structure". Specifically, the deep trench isolation structure 140 may penetrate the dielectric isolation in the back-end-of-line interconnect layer 160 from the second side of the substrate 110 and be formed simultaneously with the penetrating contacts, thereby making the fabrication process of the deep trench isolation structure 140 compatible with the fabrication process of the back-end-of-line interconnect layer 160. In addition, the critical dimension of the deep trench isolation structure 140 at the first surface 101 may be smaller than the critical dimension at the second surface 102, so that the spacing distance between adjacent peripheral devices can be reduced on the premise of achieving complete isolation of the adjacent peripheral devices, thereby increasing the integration level of the peripheral devices and facilitating miniaturization of the three-dimensional memory. According to the preparation method of the three-dimensional memory, the deep trench isolation structure is used for providing electrical isolation for a plurality of peripheral devices and between the peripheral devices and the memory string structure, the formation of deep N-well, high-doping concentration area and other structures can be avoided, the isolation structure and the preparation process thereof can be simplified, and the manufacturing cost is reduced. Meanwhile, the substrate depth required by the peripheral device can be reduced, so that the performance of the peripheral device is improved. The deep groove isolation structure divides each peripheral device into relatively independent devices, so that the problem of punch-through between the peripheral devices can be avoided. In addition, since the deep trench isolation structure has a relatively good isolation effect, the interaction between the peripheral device and the memory string structure is weakened or even avoided.

The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.

Claims

1. A three-dimensional memory, comprising:

a first semiconductor device comprising:

a substrate;

a plurality of peripheral devices, a portion of the peripheral devices being located in a well of the substrate;

a semiconductor layer disposed adjacent to the substrate;

a plurality of memory string structures located on and electrically coupled with the semiconductor layer; and

a deep trench isolation structure comprising:

a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate;

a second portion penetrating the substrate and disposed around the well to electrically isolate the peripheral devices from each other;

Shallow trench isolation structures located between the well and the deep trench isolation structures extending in and through a portion of the substrate.

2. The three-dimensional memory of claim 1, wherein the peripheral devices comprise high voltage MOS devices.

3. The three-dimensional memory of claim 1, wherein the substrate comprises a first side formed with the plurality of peripheral devices and a second side opposite the first side, wherein the deep trench isolation structure extends from the second side through the substrate and/or the semiconductor layer.

4. The three-dimensional memory of claim 3, further comprising:

and the deep trench isolation structure sequentially penetrates through the back-end-of-line interconnection layer, the substrate and/or the semiconductor layer from the second side.

5. The three-dimensional memory of claim 1, wherein the substrate comprises a first side on which the plurality of peripheral devices are formed, and a second side opposite the first side, the shallow trench isolation structure extending from the first side to the second side and through a portion of the substrate.

6. The three-dimensional memory of claim 1, wherein the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

7. The three-dimensional memory of claim 1, wherein a critical dimension of the shallow trench isolation structure is smaller than a critical dimension of the deep trench isolation structure.

8. The three-dimensional memory of claim 1, further comprising:

and the second semiconductor device is positioned on one side far away from the substrate and is connected with the first semiconductor device in a bonding way, wherein the second semiconductor device comprises a plurality of low-voltage MOS devices and/or ultra-low-voltage MOS devices.

9. A method for manufacturing a three-dimensional memory, comprising:

forming a plurality of peripheral devices within a first region of a substrate, a portion of the peripheral devices being located in a well of the substrate;

forming a plurality of memory string structures in a second region of the substrate;

removing a portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures; and

forming a deep trench isolation structure, wherein the deep trench isolation structure comprises: a first portion penetrating the substrate and/or the semiconductor layer to electrically isolate the semiconductor layer from the substrate; and a second portion penetrating the substrate and disposed around the well to electrically isolate the peripheral devices from each other; and

A shallow trench isolation structure is formed, wherein the shallow trench isolation structure is located between the well and the deep trench isolation structure, extends in and through a portion of the substrate.

10. The method of manufacturing of claim 9, wherein removing the portion of the substrate corresponding to the second region and forming a semiconductor layer electrically coupled to the plurality of memory string structures comprises: and removing a portion of the substrate corresponding to the first region to expose the well, wherein the thickness of the semiconductor layer is the same as the thickness of the well.

11. The method of manufacturing according to claim 9, wherein the peripheral device comprises a high voltage MOS device.

12. The method of preparing of claim 9, wherein the substrate comprises a first side formed with the plurality of peripheral devices, and a second side opposite the first side, wherein forming the deep trench isolation structure comprises:

forming a first trench penetrating the substrate and/or the semiconductor layer from the second side; and

and filling dielectric materials in the first trenches to form the deep trench isolation structures.

13. The method of manufacturing according to claim 12, wherein the step of forming a first trench penetrating the substrate and/or the semiconductor layer from the second side comprises:

forming a back-end-of-line interconnect layer on a second side of the substrate; and

the first trench is formed sequentially penetrating the back-end-of-line interconnect layer and the substrate and/or the semiconductor layer from the second side.

14. The method of manufacturing of claim 9, wherein the substrate includes a first side on which the plurality of peripheral devices are formed, and a second side opposite the first side, wherein the step of forming the shallow trench isolation structure includes:

forming a second trench extending from the first side to the second side and through a portion of the substrate; and

and filling dielectric materials in the second grooves to form the shallow groove isolation structures.

15. The method of manufacturing of claim 9, wherein the memory string structure includes an outside-in memory layer and a channel layer outer wall structure and extends into the substrate, wherein removing portions of the substrate corresponding to the second regions and forming a semiconductor layer electrically coupled to the plurality of memory string structures includes:

Removing a portion of the memory layer of the memory string structure extending into the substrate to expose the channel layer; and

the semiconductor layer is formed to cover the channel layer.

16. The method of claim 9, wherein the shallow trench isolation structure and the deep trench isolation structure have a predetermined distance therebetween.

17. The method of claim 9, wherein a critical dimension of the shallow trench isolation structure is smaller than a critical dimension of the deep trench isolation structure.