CN114823705A

CN114823705A - Three-dimensional memory, preparation method thereof and memory system

Info

Publication number: CN114823705A
Application number: CN202210357216.8A
Authority: CN
Inventors: 郑阿曼; 伍术
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2022-07-29

Abstract

An embodiment of the present application provides a three-dimensional memory and a method for manufacturing the same, the three-dimensional memory including: the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a memory cell array positioned on a first side of the first substrate; a second semiconductor structure including a second substrate and a first peripheral circuit on a second side of the second substrate, the first peripheral circuit including a plurality of first transistors in contact with the second substrate; and a second peripheral circuit located on a third side of the first substrate opposite the first side, the second peripheral circuit including a plurality of second transistors in contact with the first substrate; the first semiconductor structure and the second semiconductor structure are connected, and the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate.

Description

Three-dimensional memory, preparation method thereof and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory, a method for manufacturing the same, and a memory system.

Background

In some three-dimensional memories (e.g., 3D NAND), peripheral circuits responsible for data I/O and memory cell operations are formed on the same substrate, while an array of memory cells is formed on another substrate. After the two semiconductor structures are separately fabricated, the memory cell array and the peripheral circuits are electrically connected by connecting the two semiconductor structures.

However, as the number of stacked layers in a three-dimensional memory increases, the size of a semiconductor structure used to form a memory cell array is reduced while achieving the same memory capacity. Accordingly, the semiconductor structure having peripheral circuits connected to the semiconductor structure having the memory cell array is also required to be reduced. To implement the operation of more memory cells, more peripheral circuits are required. The ever-increasing area required for peripheral circuits makes it a bottleneck for the overall size reduction of three-dimensional memories.

Disclosure of Invention

Embodiments of the present application provide a three-dimensional memory, including: the method comprises the following steps: the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a memory cell array positioned on a first side of the first substrate; a second semiconductor structure including a second substrate and a first peripheral circuit located at a second side of the second substrate, the first peripheral circuit including a plurality of first transistors in contact with the second substrate; and a second peripheral circuit located on a third side of the first substrate opposite the first side, the second peripheral circuit including a plurality of second transistors in contact with the first substrate; the first semiconductor structure and the second semiconductor structure are connected, and the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate.

In some embodiments, the first transistor and the second transistor are both MOSFETs, and the first transistor and the second transistor have different operating voltages.

In some embodiments, the second transistor is a MOSFET comprising: an active region in the first substrate; a gate oxide layer contacting a portion of the active region; the gate layer is positioned on the surface of the gate oxide layer, which is far away from the active region; wherein the active region comprises a source electrode and a drain electrode which are positioned at two sides of the gate oxide layer and the grid layer. In some embodiments, the three-dimensional memory may further include a through silicon contact penetrating the first substrate from the third side, and the second peripheral circuit is electrically connected with the memory cell array and/or the first peripheral circuit through the through silicon contact.

In some embodiments, the first substrate has a thickness greater than a depth of an active region of the MOSFET.

In some embodiments, the second peripheral circuitry may further comprise an interconnect layer located on a side of the plurality of second transistors remote from the first substrate, the interconnect layer being connected with the plurality of second transistors and the through silicon contact.

In some embodiments, the first semiconductor structure may further include: and the first end of the conductive contact is connected with the first peripheral circuit, and the second end of the conductive contact structure is connected with the through silicon contact.

The embodiment of the application also provides a memory system. The memory system includes: at least one three-dimensional memory as described in any of the embodiments above; and a controller electrically connected with the at least one three-dimensional memory and configured to control the at least one three-dimensional memory.

The embodiment of the application also provides a preparation method of the three-dimensional memory, which comprises the following steps: forming a first semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a memory cell array positioned on a first side of the first substrate; forming a second semiconductor structure including a second substrate and a first peripheral circuit located at a second side of the second substrate, the first peripheral circuit including a plurality of first transistors in contact with the second substrate; connecting the first semiconductor structure and the second semiconductor structure such that the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate; and forming a second peripheral circuit on a third side of the first substrate opposite the first side, the second peripheral circuit including a plurality of second transistors in contact with the first substrate.

In some embodiments, the second transistor is a MOSFET, and forming the second peripheral circuit may include: forming a gate oxide layer of the MOSFET on the surface of the first substrate; converting a part of the first substrate corresponding to the gate oxide layer into an active region; forming a grid layer on the surface of the gate oxide layer far away from the active region; wherein the active region comprises a source electrode and a drain electrode on both sides of the gate oxide layer and the gate layer

In some embodiments, before forming the second peripheral circuit on a third side of the first substrate opposite to the first side, the method for preparing may further include: and thinning the first substrate to enable the thickness of the thinned first substrate to be larger than the depth of the active region of the MOSFET.

In some embodiments, after forming the second peripheral circuit, the method of manufacturing may further include: through silicon contacts are formed through the first substrate from the third side, and the second peripheral circuit is electrically connected to the memory cell array and/or the first peripheral circuit through the through silicon contacts.

In some embodiments, forming the first semiconductor structure may further include: and forming a conductive contact, wherein a first end of the conductive contact is connected with the first peripheral circuit, and a second end of the conductive contact structure is connected with the through silicon contact.

According to the three-dimensional memory and the manufacturing method thereof provided by some embodiments of the present application, a part of transistors in the peripheral circuits of the memory cell array are arranged on the side of the first substrate where the memory cell array is not formed, that is, the first peripheral circuits and the second peripheral circuits of the memory cell array are vertically integrated by using the first substrate, which is beneficial to cope with the problem of increased planar area requirement of the peripheral circuits due to the increase of unit storage density of the memory cell array. Meanwhile, the layout form of the peripheral circuit and the memory cell array is optimized, and the electrical transmission performance of the peripheral circuit and the memory cell array is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a three-dimensional memory according to an embodiment of the present application;

FIG. 2 is a cross-sectional schematic view of the three-dimensional memory shown in FIG. 1, according to an embodiment of the present application;

FIG. 3 is a flow chart of a method of fabricating the three-dimensional memory shown in FIG. 1 according to an embodiment of the present application;

fig. 4A to 4E are schematic process cross-sectional views illustrating a method of manufacturing the three-dimensional memory shown in fig. 3 according to an embodiment of the present disclosure; and

fig. 5A and 5B are schematic diagrams of a memory system according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function and deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

Fig. 1 is a block diagram of a three-dimensional memory 100 according to an embodiment of the present application. As shown in fig. 1, the three-dimensional memory 100 includes: a first semiconductor structure 10, a second semiconductor structure 20, and a second peripheral circuit 31. The first semiconductor structure 10 includes a first substrate 11 and a memory cell array 12 located on a first side of the first substrate 11. The second semiconductor structure 20 includes a second substrate 21 and a first peripheral circuit 22 located at a second side of the second substrate 21. The first semiconductor structure 10 and the second semiconductor structure 20 are connected, and the memory cell array 12 and the first peripheral circuit 22 are located between the first substrate 11 and the second substrate 21. The second peripheral circuit 31 is located on a third side of the first substrate 110 opposite to the first side.

In some embodiments, the first peripheral circuit 22 and the second peripheral circuit 31 may, for example, include a plurality of digital, analog, and/or mixed digital-analog circuit blocks to support the memory cell array 12 to perform various functions. Illustratively, the circuit module may include a page buffer, an address decoder, a read amplifier, and the like. Illustratively, each circuit module in the first peripheral circuit 22 or the second peripheral circuit 31 may include a plurality of transistors such as metal oxide field effect transistors (MOSFETs), diodes, fin field effect transistors (finfets), or any combination thereof. Specifically, the first peripheral circuit 22 includes a plurality of first transistors in contact with the second substrate 21, and the second peripheral circuit 31 includes a plurality of second transistors in contact with the first substrate 11.

According to the embodiment of the application, a part of the transistors in the peripheral circuit of the memory cell array are arranged on the side of the first substrate where the memory cell array is not formed, namely, the first peripheral circuit and the second peripheral circuit of the memory cell array are vertically integrated by using the first substrate, which is beneficial to solving the problem of the increase of the planar area requirement of the peripheral circuit caused by the improvement of the unit storage density of the memory cell array. Meanwhile, the layout form of the peripheral circuit and the memory cell array is optimized, and the electrical transmission performance of the peripheral circuit and the memory cell array is improved.

Fig. 2 is a cross-sectional schematic view of a three-dimensional memory 100 according to an embodiment of the present application. The structure of the three-dimensional memory 100 will be further explained in conjunction with fig. 2.

As shown in fig. 2, the stacked structure 110 may be located on a first side of the first substrate 11. The material of the first substrate 11 in the first semiconductor structure 10 may, for example, include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, a III-V compound semiconductor, or any combination thereof. Illustratively, the stacked structure 110 may include a plurality of dielectric layers 111 and a plurality of conductive layers 112 alternately stacked in a direction perpendicular or substantially perpendicular to the first substrate 11. Illustratively, the method of forming the stack structure 110 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The number of stacked layers of the dielectric layers 111 and the conductive layers 112 in the stacked structure 110 may be, for example, 8, 32, 64, 128, or the like. The greater the number of stacked layers of the stacked structure 110, the higher the integration level, and the greater the number of memory cells formed therefrom. The number of stacked layers and the stacking height of the stacked structure 110 may be designed according to actual storage requirements, which is not specifically limited in the present application. Alternatively, the material of the dielectric layer 111 may include, for example, silicon oxide, and the material of the conductive layer 112 may include, for example, metal tungsten.

In some embodiments, the first semiconductor structure 10 may include a first oxide layer 113, a first semiconductor layer 114, a second oxide layer 115, and a second semiconductor layer 116, which are sequentially disposed from the first substrate 11 to the stacked structure 110. For example, the material of the first semiconductor layer 114 and the second semiconductor layer 116 are polysilicon.

In some embodiments, a lithographic alignment structure 119 may be formed in the first oxide layer 113, the first semiconductor layer 114, the second oxide layer 115, and the second semiconductor layer 116, and may be used, for example, to provide a reference for lithographic alignment for the channel structures 121, the gate gap structure 122, and the dummy channel structure 123 formed on a side of the above structures away from the first substrate 11.

In some embodiments, the channel structure 121 extends through the stacked structure 110 and into the first semiconductor layer 114 in a direction towards the first substrate 11, for example, a direction perpendicular to the first substrate 11. Illustratively, the channel structure 121 may have a general outline shape of a cylinder, a truncated cone, a prism, or the like, for example, and may include a functional layer (not shown) and a channel layer (not shown) disposed in this order from the outside to the inside. Alternatively, the functional layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer (not shown) disposed in sequence from the outside inward. The materials of the charge blocking layer, the charge trapping layer and the tunneling layer may, in turn, comprise, for example, silicon oxide, silicon nitride and silicon oxide, thereby forming a functional layer having an ONO structure. The material of the channel layer may, for example, include a semiconductor material such as silicon (e.g., amorphous silicon, polycrystalline silicon, single crystal silicon).

In some embodiments, in the case where the first semiconductor structure 10 includes the first oxide layer 113, the first semiconductor layer 114, the second oxide layer 115, and the second semiconductor layer 116, the second semiconductor layer 116 may extend through the channel structure 121 functional layer in a direction perpendicular or substantially perpendicular to the channel structure 121 (e.g., a lateral direction in fig. 2) and contact a portion of the channel layer in the channel structure 121, such that the second semiconductor layer 116 is electrically connected with the channel layer. It should be noted that the channel structure 121 may also extend into the first substrate 11. Alternatively, the first oxide layer 113, the first semiconductor layer 114, and the second oxide layer 115 may not be provided between the first substrate 11 and the stacked-layer structure 110.

In some embodiments, a portion of the channel structure 121 and one conductive layer 112 may collectively form a memory cell, wherein the portion of the channel structure 121 is a portion of the functional layer and the channel layer corresponding to the conductive layer 112. Illustratively, the conductive layer 112 may correspond to a gate of a memory cell. In some embodiments, a plurality of memory cells arranged along the extending direction of the channel structure 121 are connected in series in a direction substantially perpendicular to the first substrate 11 and share a channel layer. The memory cell is in a programmed state or an erased state (non-programmed state) by passing carriers in the channel layer into the charge trapping layer in the functional layer or passing carriers in the charge trapping layer in the functional layer back into the channel layer under the voltage control of the conductive layer 112.

In some embodiments, the plurality of channel structures 121 may be two-dimensionally arrayed in a plane parallel or substantially parallel to the first substrate 11, such that the memory cells form a distribution in a three-dimensional array with respect to the first substrate 11. As described above, the plurality of channel structures 121 and the stacked-layer structure 110 may be referred to as a "memory cell array 12". The memory cell array 12 may be located on a first side of the first substrate 11.

In some embodiments, the gate gap structure 122 may extend through the stacked structure 110 and extend to the second semiconductor layer 116 in a direction toward the first substrate 11, for example, in a direction perpendicular to the first substrate 11. Illustratively, the gate slit structure 116 may extend in a direction parallel to the first substrate 11 (e.g., perpendicular to the direction of fig. 5). Illustratively, the gate gap structure 122 may include a conductive core (not shown) and an insulating layer (not shown) on the sidewalls of the conductive core. Optionally, the conductive core may be in contact with the second semiconductor layer 116 to achieve electrical connection. In the case where the channel layers of the plurality of channel structures 121 are electrically connected to the second semiconductor layer 116, the conductive core of the gate gap structure 122 may be electrically connected to the channel layer of the plurality of channel structures 120. The gate gap structure 122 may be used, for example, as a front side source lead-out structure of the memory cell array 12.

In other embodiments, the channel structure 121 may include an epitaxial layer (not shown) located near an end of the first substrate 11 and in contact with the first semiconductor layer 114. A portion of the channel layer proximate the epitaxial layer passes through the functional layer and contacts the epitaxial layer such that the first semiconductor layer 114 is electrically connected to the channel layer through the epitaxial layer. It should be noted that the channel structure 121 may also extend into the first substrate 11. Alternatively, the first oxide layer 113, the first semiconductor layer 114, the second oxide layer 115, and the second semiconductor layer 116 may not be disposed between the first substrate 11 and the stacked-layer structure 110. Optionally, the conductive core portion in the gate slit structure 122 may extend to, for example, the first semiconductor layer 114 or the first substrate 11 to achieve electrical connection with the plurality of channel structures 121.

In some embodiments, the step structure 117 may be formed at an edge of the stacked structure 110, for example. Illustratively, in a direction perpendicular to the first substrate 11, the pair of dielectric layers 111 and conductive layers 112 far from the first substrate 11 partially covers the pair of dielectric layers 111 and conductive layers 112 adjacent and closer to the first substrate 11, so that the conductive layer 112 of the pair of dielectric layers 111 and conductive layers 112 close to the first substrate 11 has an area exposed to the pair of dielectric layers 111 and conductive layers 112 adjacent and far from the first substrate 11. The exposed areas of conductive layer 112 may serve as electrical connection areas for word line contacts 131. Optionally, a side of the step structure 117 facing away from the first substrate 11 may be filled with at least one insulating material 118, such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

In some embodiments, the word line contact 131 may extend to an electrical connection region of the conductive layer 112 in a direction intersecting the conductive layer 112, e.g., perpendicular or substantially perpendicular to the conductive layer 112, such that one end of the word line contact 131 is electrically connected with the conductive layer 112. The material of the word line contacts 131 may include materials such as tungsten, cobalt, copper, aluminum, or any combination thereof, for example.

In some embodiments, the dummy channel structure 123 may extend through at least a portion of the stack structure 110 in an area corresponding to the step structure 117 and extend into, for example, the first substrate 11 in a direction toward the first substrate 11, for example, a direction perpendicular to the first substrate 11. Illustratively, the dummy channel structure 123 may have a similar outline shape and an internal structure as the channel structure 121. Alternatively, the dummy channel structure 123 may be directly filled with at least one insulating material, such as silicon oxide. The role of the dummy channel structure 123 includes, but is not limited to, providing mechanical support or load balancing.

In some embodiments, the insulating material 118 may also be filled on a first side of the first substrate 11, for example, a side of the first semiconductor layer 114 away from the first substrate 11. Alternatively, the insulating material 118 may be directly coated on the surface of the first substrate 11. Illustratively, one or more conductive contacts (e.g., 132) may extend into, for example, the first semiconductor layer 114 in a direction toward the first substrate 11, for example, a direction perpendicular to the first substrate 11. Illustratively, the conductive contact 132 may be used to pass electrical signals between the first semiconductor structure 10 or the second semiconductor structure 20 and the second peripheral circuit 31. Alternatively, the material of the conductive contact 132 may include, for example, a material such as tungsten, cobalt, copper, aluminum, doped polysilicon, or any combination thereof.

In some embodiments, an interconnect layer (e.g., the first interconnect layer 140) may be formed on a side of the stacked structure 110 away from the first substrate 11, and may be used, for example, to pass electrical signals to and from the second semiconductor structure 20. Illustratively, the first interconnect layer 140 may include a plurality of interconnect lines 141 extending in a direction substantially parallel to the first substrate 11 and a plurality of interconnect channels 142 extending in a direction toward the first substrate 11, e.g., perpendicular or substantially perpendicular to the first substrate 11. Alternatively, the first interconnect layer 140 may include a plurality of interlayer dielectric layers 143, and the interconnect lines 141 and the interconnect channels 142 may be formed in the interlayer dielectric layers 143. In other words, the first interconnect layer 140 may include interconnect lines 141 and interconnect channels 142 in the interlayer dielectric layer 143. Alternatively, the material of the interconnect lines 141 and the interconnect channels 142 may include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the interlayer dielectric layer 143 may, for example, include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, or any combination thereof. It is noted that the interconnect line 141 or the interconnect channel 142 in the first interconnect layer 140 may be electrically connected to at least one of the other ends of the word line contact 131 and the other end of the conductive contact 132, such that the first interconnect layer 140 is electrically connected to the conductive layer 112 through at least one of the word line contacts 131 and the second semiconductor structure 20 through the conductive contact 132.

The material of the second substrate 21 in the second semiconductor structure 20 may be, for example, the same as the first substrate 11. The first peripheral circuit 22 may be located on the second side of the second substrate 21, and may include, for example, a part of a plurality of circuit blocks for supporting the memory cell array to implement various functions. The first peripheral circuit 22 may comprise a plurality of first transistors (e.g., 211), such as a plurality of high voltage MOSFETs, or a plurality of low voltage and/or ultra low voltage MOSFETs, in contact with said second substrate 21. Among them, the structure of the MOSFET will be described in detail below.

In some embodiments, the second semiconductor structure 20 may include an interconnect layer (e.g., the second interconnect layer 220) on a side of the second peripheral circuitry 22 remote from the second substrate 21. The second interconnect layer 220 may have a similar structure to the first interconnect layer 140, and is not described herein.

The first semiconductor structure 10 and the second semiconductor structure 20 may be connected (e.g., bonded) such that the memory cell array 21 and the first peripheral circuit 22 are located between the first substrate 11 and the second substrate 21. It should be noted that the bonding connection referred to herein may be any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding. Exemplarily, the first semiconductor structure 10 may have a first bonding face 101 remote from the first substrate 11. The interconnect lines 141 and/or the interconnect vias 142 in the first interconnect layer 140 may be exposed to the first bonding surface 101 and may serve as first bonding contacts for the first semiconductor structure 10. Similarly, the second semiconductor structure 20 may have a second bonding surface 201. The interconnect lines and/or interconnect vias in the second interconnect layer 220 may be exposed to the second bonding surface 201 and may serve as second bonding contacts for the second semiconductor structure 200. The first semiconductor structure 10 may be positioned on the second semiconductor structure 20, for example, by aligning the first and second bonding contacts, such that the first and second bonding contacts are electrically connected at the aligned locations, and the channel structure 121, the wordline contact 131, and the conductive contact 132 in the first semiconductor structure 10 are electrically connected with the first peripheral circuit 22 in the second semiconductor structure 20.

The second peripheral circuit 31 may be located on the other side of the first substrate 11 opposite to the first side, and may for example include another portion of the plurality of circuit blocks for supporting the memory cell array 12 to implement various functions. The second peripheral circuit 31 may, for example, include a plurality of second transistors (e.g., 311) in contact with the first substrate 11. Alternatively, where the first transistor (e.g., 211) is a high voltage MOSFET, the second transistor (e.g., 311) may be a low voltage and/or ultra low voltage MOSFET; where the first transistor (e.g., 211) is a low voltage and/or ultra low voltage MOSFET, the second transistor (e.g., 311) is a high voltage MOSFET. It should be noted that due to the difference in the physical structures (e.g., active area depth, gate oxide thickness) of the high-voltage MOSFET and the low-voltage (including ultra low voltage) MOSFET, the arrangement of the high-voltage MOSFET and the low-voltage (including ultra low voltage) MOSFET in the first peripheral circuit 22 and the second peripheral circuit 31, respectively, is beneficial to obtain good process compatibility in the process of manufacturing the first peripheral circuit 22 and the second peripheral circuit 31. Further, the MOSFETs are called a high voltage MOSFET, a low voltage MOSFET, and an ultra low voltage MOSFET according to an operating voltage. For example, the operating voltages of the high voltage MOSFET, the low voltage MOSFET, and the ultra low voltage MOSFET decrease in sequence. In other words, the operating voltages of the first transistor (e.g., 211) and the second transistor (e.g., 311) are not the same.

The structure and the formation method of the second transistor 311 will be further described below by taking the MOSFET as an example.

In some embodiments, the second transistor 311 may be a P-type MOSFET or an N-type MOSFET, and its N-doped and/or P-doped active region 312 may be located in the first substrate 11. The dopant profile and concentration and depth of the active region 312 affect the device characteristics of the second transistor 311. For example, the dopant profile and concentration and depth of the active region 312 may be different for high voltage MOSFETs or low voltage (including ultra low voltage) MOSFETs. Specifically, the active region depth of the high voltage MOSFET is greater than the active region depth of the low voltage (including ultra low voltage) MOSFET.

Illustratively, an N-type active region 312 (also referred to As an N-well) may be formed in the first substrate 11 using an N-type dopant such As phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof, or a P-type active region (also referred to As a P-well) may be formed in the first substrate 11 using a P-type dopant such As boron (B). Alternatively, the dopant incorporation may be achieved by processes such as ion implantation and laser annealing. In other words, the active region 312 of the MOSFET 311 may be located in the first substrate 11 and have a surface that is remote from and exposed by the second semiconductor structure 20.

In some embodiments, the MOSFET 311 may further include a gate oxide layer 313 and a gate layer 314 located on a surface of the gate oxide layer 313 remote from the active region 312. The gate oxide 313 may be partially in contact with the active region 312. Illustratively, the material of the gate oxide layer 313 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or high dielectric constant materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, and lanthanum oxide. The material of the gate layer 314 may include, for example, polysilicon, aluminum, copper, tungsten, or any combination thereof.

In some embodiments, MOSFET 311 may further include source/drains 315-1 and 315-2 located in active region 312 and on both sides of the stack formed by gate layer 314 and gate oxide 313. Illustratively, the source/drain 315-1/315-2 is doped with a high concentration of dopants. For an N-type MOSFET, the dopant of the source/drain 315-1/315-2 can include an N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof. For a P-type MOSFET, the dopant of the source/drain 315-1/315-2 can include a P-type dopant such as boron. Illustratively, the dopant incorporation can be achieved by processes such as ion implantation and activation annealing. The source/drain 315-1/315-2 of the MOSFET 311 may be the same material as the first substrate 11. Alternatively, the source/drain 315-1/315-2 of the MOSFET 311 may be of a different material than the first substrate 11.

In some embodiments, the active regions 312 of the second transistors 311 may be surrounded by Shallow Trench Isolation (STI)316, for example, to achieve electrical isolation between adjacent second transistors 311. The shallow trench isolation 316 may be formed by patterning the first substrate 11, for example, by photolithography and etching processes, and filling and polishing the insulating material. The insulating material may, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, Low Temperature Oxide (LTO), High Temperature Oxide (HTO), or any combination thereof. Alternatively, processes such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof may be employed to fill the insulating material.

In some embodiments, the metal silicides 317-1 and 317-2 may be located on the surface of the source/drain 315-1/315-2. Illustratively, the metal silicides 317-1 and 317-2 may be formed by, for example, first forming a metal material such as titanium (Ti), cobalt (Co), nickel alloy (NiPt), or any combination thereof on the surface of the source/drain 315-1/315-2 by a PVD process, and then forming a metal material such as TiSi on the surface of the source/drain 315-1/315-2 by, for example, two rapid thermal annealing processes ₂ 、CoSi ₂ Metallic silicides 317-1 and 317-2 of NiPtSi. Alternatively, in the case that the material of the gate layer 314 is polysilicon, the metal silicide 317-3 may be formed on the surface of the gate layer 314 away from the gate oxide layer 313.

In some embodiments, the thickness (e.g., maximum thickness) of the first substrate 11 may be greater than the depth of the active region 312 of the second transistor 311 to meet the depth requirement of the active region 312 of the second transistor 311 (e.g., MOSFET). Alternatively, the first substrate 11 may be thinned by, for example, a CMP process, so that the thickness of the thinned first substrate 11 is greater than the required depth of the active region 312 of the second transistor 311.

It should be understood that the second transistor 311 is not limited to a MOSFET, and the structure of other types of transistors (such as BJT, diode, FinFET, etc.) may be simultaneously formed through different mask designs and layouts during the process of fabricating a MOSFET.

In some embodiments, the second peripheral circuit 31 may include an interconnect layer, such as the third interconnect layer 320, on a side of the plurality of second transistors (e.g., 311) away from the first substrate 11. Illustratively, the third interconnect layer 320 may include a plurality of interconnect lines (e.g., 321) and a plurality of interconnect channels (e.g., 331). The third interconnect layer 320 is similar to the first interconnect layer 140 in structure and formation process, and is not described herein again. Illustratively, one end of the interconnection 331 may be in contact with the silicide 317-1 to 317-3 on the source/drain 315-1/315-2 and the gate layer 314 of the second transistor 311 (e.g., MOSFET), and the other end of the interconnection 331 may be in contact with the interconnection line 321. Illustratively, several second transistors (e.g., 311) may be made to form a circuit block for implementing a corresponding function through the third interconnect layer 320.

In some implementations, the three-dimensional memory 100 can also include one or more through silicon contacts (e.g., 332). The through silicon contact 332 passes through, for example, the first substrate 11, the first oxide layer 113, and the first semiconductor layer 114, and is connected to the conductive contact 132. The end of the through-silicon contact 332 not connected to the conductive contact 132 may be connected to a third interconnect layer 320, such as an interconnect line 321, so that the second peripheral circuit 31 is electrically connected to the first peripheral circuit 22 through, for example, the through-silicon contact 332, the conductive contact 132, the first interconnect layer 140. As described above, the first peripheral circuit 22 and the second peripheral circuit 31 are electrically connected and may together constitute a complete peripheral circuit for supporting the memory cell array 12 to implement various circuit functions.

According to the three-dimensional memory provided by some embodiments of the present application, a part of the transistors in the peripheral circuit are arranged on the side of the first substrate where the memory cell array is not formed, that is, the first peripheral circuit and the second peripheral circuit of the memory cell array are vertically integrated by using the first substrate, which is beneficial to cope with the problem of increased planar area requirement of the peripheral circuit due to the increase of the unit storage density of the memory cell array. Meanwhile, the layout form of the peripheral circuit and the memory cell array is optimized, and the electrical transmission performance of the peripheral circuit and the memory cell array is improved.

The application also provides a preparation method 1000 of the three-dimensional memory. Fig. 3 is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application. As shown in fig. 3, the method 1000 for manufacturing a three-dimensional memory may include the following steps:

s100, forming a first semiconductor structure, where the first semiconductor structure includes a first substrate and a memory cell array located on a first side of the first substrate, and a first peripheral circuit includes a plurality of first transistors in contact with a second substrate;

s200, forming a second semiconductor structure, wherein the second semiconductor structure comprises a second substrate and a first peripheral circuit positioned on the second side of the second substrate, and the second peripheral circuit comprises a plurality of second transistors contacted with the first substrate;

s300, connecting the first semiconductor structure and the second semiconductor structure so that the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate;

and S400, forming a second peripheral circuit on a third side of the first substrate opposite to the first side.

It should be understood that the steps shown in the preparation method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in a different order than shown in fig. 1. Illustratively, steps S100 and S200 may be performed simultaneously, i.e., the first semiconductor structure 10 and the second semiconductor structure 20 are processed in parallel, to improve production efficiency.

Fig. 4A to 4E are schematic process cross-sectional views illustrating a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. The above steps S100 to S400 are further described below with reference to fig. 4A to 4E. Since the internal structures of the first and

second semiconductor structures

10 and 20 and the process method thereof are described in detail above, the description of steps S100 to S300 is omitted herein for the sake of brevity. Like reference numerals in fig. 4A to 4E refer to like structures as compared to fig. 1.

As shown in fig. 4B, the method 1000 of manufacturing a three-dimensional memory proceeds to step S400. In some embodiments of step S400, after the first semiconductor structure 10 and the second semiconductor structure 20 are connected, the first substrate 11 may be thinned using, for example, a mechanical chemical polishing (CMP) process, so that the thickness of the thinned first substrate 11 is greater than the depth required for the active region 312 (refer to fig. 4E) of the subsequently formed second transistor 311. In some embodiments, as shown in fig. 4C, a gate oxide layer 313 may be formed on the surface of the first substrate 11. Alternatively, the material of the gate oxide layer 313 may include, for example, silicon oxide. In the case where the material of the gate oxide layer 313 is silicon oxide, the method of forming the gate oxide layer 313 may include, but is not limited to, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. It can be understood that the PECVD process utilizes glow discharge to ionize the thin gas under a high frequency electric field to generate plasmas, which are accelerated in the electric field to obtain energy, thereby obtaining the gate oxide layer 313 with higher film quality at a lower temperature, which is beneficial to reducing the influence of temperature on the connection interface of the first semiconductor structure 10 and the second semiconductor structure 20 during the process of forming the gate oxide layer 313.

In some embodiments, as shown in fig. 4D, the gate oxide layer 313 may be patterned, for example, by photolithography and etching (e.g., a dry or wet etching process), for example, to remove a portion of the gate oxide layer 313, so that a remaining portion of the gate oxide layer 313 may serve as the gate oxide layer 313 for each second transistor 311 (see fig. 4E).

In some embodiments, the portions of the first substrate 11 corresponding to the gate oxide layer 313 may be converted into the active regions 312 and the source/drain electrodes 315-1/315-2 using, for example, ion implantation and a laser annealing process. It can be appreciated that, since the laser annealing process can achieve the annealing purpose in a very short time, it is beneficial to reduce the influence of the annealing process on the connection interface of the first semiconductor structure 10 and the second semiconductor structure 20.

In some embodiments, as shown in fig. 4E, a plurality of second transistors 311 may be formed by the above-mentioned process, which is not described herein again. After forming the plurality of second transistors 311, a dielectric material layer 333, such as silicon oxide, may be used to cover a side of the plurality of second transistors 311 away from the first substrate 11 to form an electrical isolation.

In some embodiments, the interconnect vias 331 may be formed through the dielectric material layer 333 and extend in a direction perpendicular or substantially perpendicular to the first substrate 11 using, for example, photolithography and etching processes (e.g., dry or wet etching processes). The interconnect 331 may be in contact with the metal silicides 317-1 through 317-3, for example. Similarly, through silicon contact 332 may be formed through dielectric material layer 333 and extending in a direction perpendicular or substantially perpendicular to first substrate 11 using, for example, a photolithography and etching process (e.g., a dry or wet etching process). Through silicon contact 332 may, for example, be in contact with conductive contact 132.

In some embodiments, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the interlevel dielectric layer 322 on the side of the dielectric material layer 333 away from the first substrate 11. Interconnect lines 321 are then formed in contact with the through silicon contacts 332 and the interconnect vias 331 using, for example, photolithography and etching processes (e.g., dry or wet etching processes) and thin film deposition processes. It should be noted that the interlevel dielectric layer 322 and the interconnect line 321 shown in fig. 4E are only exemplary, and a similar process may be used to form a plurality of interconnect lines 321 at different heights.

According to the method for manufacturing the three-dimensional memory provided by some embodiments of the present application, a portion of the transistors in the peripheral circuit is disposed on the side of the first substrate where the memory cell array is not formed, that is, the first peripheral circuit and the second peripheral circuit of the memory cell array are vertically integrated by using the first substrate, which is beneficial to cope with the problem of increased planar area requirement of the peripheral circuit due to the increase of the unit storage density of the memory cell array. Meanwhile, the layout form of the peripheral circuit and the memory cell array is optimized, and the electrical transmission performance of the peripheral circuit and the memory cell array is improved.

Fig. 5A and 5B are schematic diagrams of memory systems 2000a and 2000B according to an embodiment of the present application. As shown in fig. 5A and 5B, the memory system 2000a or 2000B includes at least one three-dimensional memory 2100 and a controller 2200.

The three-dimensional memory 2100 may include the structure described in any of the above embodiments, which is not described in detail herein. The controller 2200 may control the three-dimensional memory 2100 through, for example, a channel (not shown), and the three-dimensional memory 2100 may perform operations based on the control of the controller 2200. Illustratively, the three-dimensional memory 2100 may receive commands and addresses from the controller 2200, e.g., via channels, and access regions of the storage array structure responsive to the addresses. In other words, the three-dimensional memory 2100 may perform an internal operation corresponding to a command on a region selected by an address.

In some examples, the controller 2200 and the one or more three-dimensional memories 2100 may be integrated into various types of storage devices, in other words, the

memory systems

2000a, 2000b may be implemented and packaged into different types of final electronic products. In one example as shown in fig. 5A, the controller 2200 and the single three-dimensional memory 2100 may be integrated into a memory system 2200a in the form of a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. The memory system 2200a in the form of a memory card may also include a memory card connector 2300a that couples it with a host (not shown).

In another example as shown in fig. 5B, the controller 2200 and the plurality of three-dimensional memories 2100 may be integrated into a memory system 2000B formed of a Solid State Disk (SSD). The Solid State Disk (SSD) may also include an SSD connector 2300b coupling it with the host. In some embodiments, the storage capacity and/or operating speed of a Solid State Disk (SSD) may be higher than that of a memory card.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A three-dimensional memory, comprising:

the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a memory cell array positioned on a first side of the first substrate;

a second semiconductor structure comprising a second substrate and a first peripheral circuit located at a second side of the second substrate, the first peripheral circuit comprising a plurality of first transistors in contact with the second substrate; and

a second peripheral circuit on a third side of the first substrate opposite the first side, the second peripheral circuit including a plurality of second transistors in contact with the first substrate;

wherein the first semiconductor structure and the second semiconductor structure are connected, and the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate.

2. The three-dimensional memory according to claim 1, wherein the first transistor and the second transistor are both MOSFETs, and the first transistor and the second transistor have different operating voltages.

3. The three-dimensional memory of claim 1, wherein the second transistor is a MOSFET comprising:

an active region in the first substrate;

a gate oxide layer contacting a portion of the active region; and

the gate layer is positioned on the surface of the gate oxide layer far away from the active region;

the active region comprises a source electrode and a drain electrode which are positioned on two sides of the gate oxide layer and the grid layer.

4. The three-dimensional memory of claim 3, wherein a thickness of the first substrate is greater than a depth of an active region of the MOSFET.

5. The three-dimensional memory according to claim 1, wherein the three-dimensional memory further comprises a through silicon contact penetrating the first substrate from the third side, the second peripheral circuit being electrically connected with the memory cell array and/or the first peripheral circuit through the through silicon contact.

6. The three-dimensional memory of claim 5, wherein the second peripheral circuitry further comprises an interconnect layer on a side of the plurality of second transistors distal from the first substrate, the interconnect layer connecting the plurality of second transistors and the through silicon contacts.

7. The three-dimensional memory of claim 5, wherein the first semiconductor structure further comprises:

a conductive contact having a first end connected to the first peripheral circuit and a second end connected to the through silicon contact.

8. A memory system, comprising:

at least one three-dimensional memory according to any one of claims 1 to 7; and

a controller electrically connected to at least one of the three-dimensional memories and configured to control at least one of the three-dimensional memories.

9. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a first semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a memory cell array positioned on a first side of the first substrate;

forming a second semiconductor structure comprising a second substrate and first peripheral circuitry located at a second side of the second substrate, the first peripheral circuitry comprising a plurality of first transistors in contact with the second substrate;

connecting the first semiconductor structure and the second semiconductor structure such that the memory cell array and the first peripheral circuit are located between the first substrate and the second substrate; and

forming a second peripheral circuit on a third side of the first substrate opposite the first side, the second peripheral circuit including a plurality of second transistors in contact with the first substrate.

10. The manufacturing method according to claim 9, wherein the first transistor and the second transistor are both MOSFETs, and the first transistor and the second transistor have different operating voltages.

11. The manufacturing method according to claim 9, wherein the second transistor is a MOSFET, and forming a second peripheral circuit includes:

forming a gate oxide layer of the MOSFET on the surface of the first substrate;

converting a part of the first substrate corresponding to the gate oxide layer into an active region; and

forming a gate layer on the surface of the gate oxide layer far away from the active region;

12. The manufacturing method according to claim 11, wherein before forming a second peripheral circuit on a third side of the first substrate opposite to the first side, the manufacturing method further comprises:

and thinning the first substrate, and enabling the thickness of the thinned first substrate to be larger than the depth of the active region of the MOSFET.

13. The production method according to claim 9, wherein the production method further comprises:

forming through silicon contacts through the first substrate from the third side, the second peripheral circuitry being electrically connected with the array of memory cells and/or the first peripheral circuitry through the through silicon contacts.

14. The method of claim 13, wherein forming a first semiconductor structure further comprises:

forming a conductive contact, wherein a first end of the conductive contact is connected to the first peripheral circuit and a second end of the conductive contact structure is connected to the through silicon contact.