CN113782538B

CN113782538B - Three-dimensional memory and preparation method thereof

Info

Publication number: CN113782538B
Application number: CN202111041776.4A
Authority: CN
Inventors: 陈亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2023-12-26
Anticipated expiration: 2041-09-07
Also published as: CN113782538A

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory includes: a first semiconductor structure, comprising: a first peripheral circuit and a plurality of memory string structures distributed along a first direction; a second semiconductor structure, comprising: a second substrate and a second peripheral circuit on the second substrate; wherein the first semiconductor structure and the second semiconductor structure are bonded to electrically connect the plurality of memory string structures and/or the first peripheral circuit and the second peripheral circuit. The three-dimensional memory and the preparation method thereof can optimize the arrangement form of the peripheral circuit and the plurality of memory string structures and optimize the electric signal transmission performance of the peripheral circuit and the plurality of memory string structures.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a three-dimensional memory and a method of manufacturing the same.

Background

In a three-dimensional memory (3D NAND) based on the xbonding architecture, peripheral circuits responsible for data I/O and memory cell operation are formed on the same substrate, while a memory cell array is formed on another substrate. After the two semiconductor structures are prepared, the two semiconductor structures are bonded and connected so that the memory cell array and the peripheral circuit are connected.

However, as the number of stacked layers of the 3D NAND technology increases, the size of the semiconductor structure used to form the memory cell array decreases while achieving the same memory capacity. Accordingly, the semiconductor structure having peripheral circuits, which is bonded to the semiconductor structure having the memory cell array, is also required to be reduced, which affects the arrangement formation of the peripheral circuits and thus the circuit-on performance of the peripheral circuits and the memory cell array.

Thus, how to optimize the peripheral circuits and the memory cell arrays formed on different substrates is one of the technical problems to be solved by those skilled in the art.

Disclosure of Invention

The present application provides a three-dimensional memory, the three-dimensional memory comprising: a first semiconductor structure, comprising: a first peripheral circuit and a plurality of memory string structures distributed along a first direction; a second semiconductor structure, comprising: a second substrate; and a second peripheral circuit on the second substrate; wherein the first semiconductor structure and the second semiconductor structure are bonded to electrically connect the plurality of memory string structures and/or the first peripheral circuit and the second peripheral circuit.

In some implementations, the first peripheral circuit includes: and a capacitor layer including a first dielectric layer and a first conductive layer alternately stacked.

In some embodiments, the first peripheral circuit may further include: the semiconductor device comprises a first substrate and a plurality of peripheral devices at least partially positioned on the first substrate, wherein the first substrate, the plurality of peripheral devices and the capacitor layer are sequentially arranged along the second direction.

In some embodiments, the peripheral devices may include high voltage MOS devices.

In some embodiments, the first semiconductor structure further comprises: a dummy memory string structure extending through at least a portion of the alternately stacked first dielectric layers and first conductive layers; and a through contact penetrating the dummy memory string structure and electrically connected with the peripheral device.

In some embodiments, the first conductive layer includes a first portion and a second portion disposed in sequence away from the peripheral device, wherein the first semiconductor structure further includes: and a conductive path in contact with the second portion.

In some embodiments, the first semiconductor structure further comprises: and a second dielectric layer and a second conductive layer alternately stacked, wherein the memory string structure is formed in the second dielectric layer and the second conductive layer alternately stacked, and at least a portion of the second dielectric layer is disposed flush with the corresponding first dielectric layer in the first direction, and at least a portion of the second conductive layer is disposed flush with the corresponding first conductive layer in the first direction.

In some embodiments, the first semiconductor structure further comprises: and a semiconductor layer located on a side of the plurality of memory string structures remote from the second semiconductor structure, wherein the memory string structures are located between the semiconductor layer and the second semiconductor structure.

In some embodiments, the first semiconductor structure further comprises: and a first interconnection layer covering the alternately stacked first dielectric layers and first conductive layers and the alternately stacked second dielectric layers and second conductive layers, and electrically connected to the peripheral device through the through contact, and electrically connected to the conductive via.

In some embodiments, the operating voltage of the device located in the second peripheral circuit is less than the operating voltage of the device located in the first peripheral circuit.

The application also provides a preparation method of the three-dimensional memory. The preparation method comprises the following steps: forming a first semiconductor structure, comprising: forming a first peripheral circuit on a first region of a substrate; forming a plurality of memory string structures on a second region of the substrate; forming a second semiconductor structure, comprising: forming a second peripheral circuit on a second substrate; and bonding the first semiconductor structure and the second semiconductor structure to electrically connect the plurality of memory string structures and/or the first peripheral circuit with the second peripheral circuit.

In some embodiments, the step of forming a first peripheral circuit on a first region of the substrate includes: a capacitor layer including alternately stacked first dielectric layers and first conductive layers is formed on the first region.

In some embodiments, the step of forming a capacitor layer including alternately stacked first dielectric layers and first conductive layers on the first region includes: forming a first dielectric layer and a first sacrificial layer alternately stacked on the first region; forming a gate slit through the alternately stacked first dielectric layers and first sacrificial layers; removing the sacrificial layer through the gate slit to form a sacrificial gap; and forming the first conductive layer within the sacrificial gap to form a capacitor layer.

In some embodiments, before the step of forming a capacitor layer comprising alternately stacked first dielectric layers and first conductive layers on the first region, the method further comprises: a plurality of peripheral devices is formed at least partially over the first region, wherein the plurality of peripheral devices are located between the substrate and the capacitor layer.

In some embodiments, the peripheral devices include high voltage MOS devices.

In some embodiments, after the step of forming a plurality of peripheral devices at least partially located on the first region, the method further comprises: forming a dummy memory string structure through at least partially alternating stacked first dielectric layers and first conductive layers; and forming a through contact penetrating the dummy memory string structure and electrically connected to the peripheral device.

In some embodiments, the first conductive layer includes a first portion and a second portion disposed in sequence away from the peripheral device, wherein while forming a through contact that extends through the dummy memory string structure and is electrically connected to the peripheral device: a conductive via is formed in contact with the first conductive layer.

In some embodiments, the second dielectric layers and the second conductive layers are alternately stacked in the second region while the first dielectric layers and the first conductive layers are formed, wherein the memory string structure is formed in the alternately stacked second dielectric layers and second conductive layers.

In some embodiments, after the step of forming a through contact through the dummy memory string structure and electrically connected to the peripheral device, the method further comprises: a first interconnect layer is formed to cover the alternating stacked first dielectric layers and first conductive layers, wherein the first interconnect layer is electrically connected to the peripheral device through the through contacts and to the conductive vias.

In some embodiments, after the step of bonding the first semiconductor structure and the second semiconductor structure, the method includes: removing a portion of the second region of the substrate to expose the memory string structure; and forming a semiconductor layer covering the memory string structure.

In some embodiments, after the step of forming the semiconductor layer overlying the memory string structure, the method further comprises: a back-end-of-line interconnect layer is formed overlying the semiconductor layer and a portion of the substrate corresponding to the first region.

According to the three-dimensional memory and the preparation method thereof, part of the peripheral circuit and the plurality of memory string structures are arranged in the same semiconductor structure, so that the arrangement form of the peripheral circuit and the plurality of memory string structures is optimized, and the electric signal transmission performance of the peripheral circuit and the plurality of memory string structures is further optimized. Further, by forming the capacitor layer by using alternately stacked dielectric layers and conductive layers for forming the memory string structure, it is possible to provide a high-capacity capacitor device for the peripheral circuit and to simplify the manufacturing cost of the capacitor device.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

FIG. 1 is a block diagram of a three-dimensional memory according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present application;

FIG. 3 is a flow chart of a method of fabricating a three-dimensional memory according to an embodiment of the present application; and

Fig. 4A to 4I are process cross-sectional views schematically illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes," "including," and/or "having," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

The description herein refers to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function and shape and dimensional deviations, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the locations of the components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying structure or superstructure, or can have a range less than the underlying structure or superstructure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically and/or along tapered surfaces. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, and/or thereunder. The layer can comprise a plurality of layers.

Fig. 1 is a block diagram of a three-dimensional memory 10 according to an embodiment of the present application. As shown in fig. 1, the three-dimensional memory 10 includes: a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 includes: a first peripheral circuit 120 and a plurality of memory string structures 130. The plurality of memory string structures 130 may constitute a memory string structure array, and each of the memory string structures may have a channel layer formed therein in which a plurality of memory cells form a circuit path. The word lines of the memory cells may be stacked in a second direction D2 perpendicular to the first direction D1.

In some embodiments, the first semiconductor structure 100 may further include a first substrate (not shown) located at a region corresponding to the plurality of memory string structures 130 and remote from the second semiconductor structure 200. Each memory string structure may extend into the first substrate in the second direction D2, and an epitaxial layer and a channel layer in contact with the epitaxial layer are disposed at a portion of the memory string structure adjacent to the first substrate such that the plurality of memory cells form a circuit path with the first substrate.

In some embodiments, the first semiconductor structure 100 may further include a semiconductor layer (not shown) located at a region corresponding to the plurality of memory string structures 130 and remote from the second semiconductor structure 200. The semiconductor layer may be in contact with the exposed channel layer of each memory string structure, such that the plurality of memory cells form a circuit path with the semiconductor layer.

The second semiconductor structure 200 may include: a second substrate 210 and a second peripheral circuit 220 formed on the second substrate 210. The first peripheral circuit 120 and the second peripheral circuit 220 may include a plurality of digital, analog, and/or digital-analog mixed circuit modules to support the plurality of memory string structures 130 to perform various functions. Illustratively, the circuit module may include a page buffer, an address decoder, and a read amplifier. Each circuit module in the first peripheral circuit 120 and/or the second peripheral circuit 220 may include active and/or passive semiconductor device components such as transistors, diodes, resistors, capacitors, and the like.

The first semiconductor structure 100 and the second semiconductor structure 200 may be bonded and connected face to face in the second direction D2 by direct bonding and/or hybrid bonding, so that the first peripheral circuit 120 and the second peripheral circuit 220 are electrically connected, or the plurality of memory string structures 130 are electrically connected to the first peripheral circuit 120 after being electrically connected to the second peripheral circuit 220.

Fig. 2 is a schematic cross-sectional view of a three-dimensional memory 10 according to an embodiment of the present application. As shown in fig. 2, the first substrate 110 in the first semiconductor structure 100 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, group III-V compound semiconductors, and any other suitable materials.

The first peripheral circuit 120 may include a first device layer 140 on the first region A1 of the first substrate 110. All or part of the peripheral devices 141 in the first device layer 140 are formed in the first substrate 110 and/or on the first substrate 110, and the peripheral devices 141 in the first device layer 140 may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

In some embodiments, peripheral devices 141 may be P-type MOSFETs and/or N-type MOSFETs and are formed in wells 142 having N-type doping and/or P-type doping. Specifically, the well 142 of the peripheral device 141 may include a P-type doped well for an N-type MOSFET and an N-type doped well for a P-type MOSFET, and are referred to as a P-well and an N-well, respectively. The dopant profile and concentration of well 142 affects the device characteristics of peripheral device 141. For MOSFET devices with low threshold voltages (Vth), the well 142 is doped at a lower concentration to form a low voltage P-well or a low voltage N-well. For MOSFET devices with high threshold voltages, the well 142 is doped at a higher concentration to form a high voltage P-well or a high voltage N-well. Alternatively, to achieve complete electrical isolation from the first substrate 110, a deep N-well may be formed under the high voltage P-well for an N-type MOSFET with a high threshold voltage. In the embodiment of the present application, since the manufacturing process of the high voltage device has better compatibility with the manufacturing process of the plurality of memory string structures, a plurality of high voltage devices (for example, high voltage P-type MOSFETs or high voltage N-type MOSFETs) may be disposed on the first device layer 140, so as to simplify the process of forming the plurality of memory string structures and the first device layer 140 on the same first substrate 110.

In some embodiments, an N-type dopant such As phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof may be employed in the first substrate 110 to form an N-well. A P-type dopant, such as boron (B), may be used to form a P-well in the first substrate 110. In addition, the doping of the dopants may be achieved by ion implantation and activation annealing, etc., or by in situ doping during the preparation of the epitaxial layer of the device Active Area (AA).

In some embodiments, the P-type MOSFET and/or the N-type MOSFET may further include a gate stack 143 formed from a gate dielectric and a gate conductor. The material of the gate dielectric may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, and lanthanum oxide. In addition, the process of forming the gate dielectric may include Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), sputtering, thermal oxidation/nitridation, or any combination thereof. The material of the gate conductor may include a metal material such as tungsten (W), cobalt (Co), nickel (Ni), copper (Gu), or aluminum (Al). Alternatively, the gate conductor may also be made of other conductive materials such as titanium nitride (TiN), tantalum nitride (TaN), and the like. Alternatively, the material of the gate conductor may also include a polycrystalline semiconductor, such as polysilicon, poly-germanium-silicon, and any other suitable material. Alternatively, the polycrystalline semiconductor may be combined with any suitable type of dopant, such as boron, phosphorus, arsenic, and the like. The process of forming the gate conductor may include any suitable thin film deposition method, such as sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, or any combination thereof.

In some implementations, peripheral device 141 also includes source/drains 144 located on either side of gate stack 143 and in well 142. The source/drain 144 is doped with a high concentration of dopant. For an N-type MOSFET, the dopant of the source/drain 144 may include an N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof. For a P-type MOSFET, the dopant of the source/drain 144 may include a P-type dopant such as boron. In addition, the doping of the dopants may be achieved by ion implantation, activation annealing, and the like, or by in situ doping during the fabrication of the epitaxial layer of the active region of the device. The source/drain 144 of the peripheral device 141 may be the same material as the first substrate 110. Alternatively, the material of the source/drain electrodes 144 of the peripheral device 141 may be different from that of the first substrate 110 to improve the electrical performance of the peripheral device 141.

In some implementations, the active region of peripheral device 141 may be surrounded by Shallow Trench Isolation (STI) 145 to enable electrical isolation between the plurality of peripheral devices 141. The shallow trench isolation 145 may be formed by patterning the first substrate 110, filling an insulating material, and polishing the insulating material through photolithography and etching processes. The insulating material for the shallow trench isolation 145 may include silicon oxide, silicon nitride, silicon oxynitride, low Temperature Oxide (LTO), high Temperature Oxide (HTO), or any combination thereof. And the insulating material may be filled using a process such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation or any combination thereof.

It should be understood that peripheral device 141 is not limited to MOSFETs and that the structure of other peripheral devices (e.g., BJTs, diodes, resistors, inductors, etc.) may be formed simultaneously during the process of making MOSFETs by different mask designs and layouts.

The first peripheral circuitry 120 may also include a capacitor layer 150 located on the first device layer 140. The capacitor layer 150 may include first dielectric layers 151 and first conductive layers 152 alternately stacked in a direction perpendicular to the first substrate 110 such that the first dielectric layers 151 are disposed between adjacent first conductive layers 152 (e.g., first conductive layers 152a and 152 b). The first dielectric layer 151 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first conductive layer 152 may be made of a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. And the first dielectric layer 151 and the first conductive layer 152 may be formed using a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

In some embodiments, a first conductive layer 152b of two adjacent first conductive layers 152 (e.g., 152a and 152 b) that is distal from the first substrate 110 and a first dielectric layer 151 between the two adjacent first conductive layers 152 partially covers the first conductive layer 152a proximate to the first substrate 110, thereby exposing an edge region of the first conductive layer 152a proximate to the first substrate 110 such that the first conductive via 153 is in contact electrical connection with the exposed edge region. And the first step structure at the edge region may be formed by performing a multiple "trim-etch" cycle process on the plurality of first dielectric layers 151 and the first conductive layers 152 which are alternately stacked. Since the plurality of memory string structures have a similar stacked structure as the capacitor layer 150, the capacitor layer 150 may be simultaneously formed during a process of forming the plurality of memory string structures so as to simplify a manufacturing process of the capacitor layer 150. Among them, a specific structure regarding the memory string structure will be described in detail below.

In some embodiments, the plurality of first conductive channels 153 may include, but are not limited to, cylindrical, conical, rectangular, and conductive structures extending in a direction perpendicular to the first substrate 110. And one end of the first conductive via 153 may be in contact with the first conductive layer 152 exposed in the first stepped structure of the capacitor layer 150, and the other end may be in contact with the first interconnection layer 170 located at a side of the capacitor layer 150 remote from the first substrate 110. Among them, the structure of the first interconnect layer 170 will be described in detail below. The material of the first conductive via 153 may include a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof, and the first conductive via 153 may be formed by photolithography and etching processes and filling the conductive material.

In some embodiments, the plurality of first conductive vias 153 may be disposed on the first conductive layer 151 of the first ladder structure in the capacitor layer 150 parallel to the first substrate 110. Specifically, the arrangement of the plurality of first conductive channels 153 includes, but is not limited to: the odd-numbered first conductive layers 152 in the left side portion of the first ladder structure dispose a first group of first conductive vias 153, the even-numbered first conductive layers 152 in the right side portion of the first ladder structure dispose a second group of first conductive vias 153, and the other ends of the first group of first conductive vias 153 and the second group of first conductive vias 153 are electrically connected to the first interconnect structure 170, respectively. The capacitor layer 150 forms a plurality of capacitive devices that may be equivalent to different circuit structures through different arrangements with the first conductive path 153, and may be implemented to provide a high capacity capacitive device for a plurality of memory string structures.

In some embodiments, in various arrangements of the first conductive via 153, the first conductive via 153 may be in contact connection with a second portion of the first conductive layer 152 remote from the first device layer 140. The first conductive layer 152 may include a first portion and a second portion disposed in sequence away from the first device layer 140, and the first portion may include at least one first conductive layer. The first portion of the first conductive layer 152 may act as a shield between the capacitive devices in the capacitor layer 150 and the peripheral devices 141 in the first device layer 140 to avoid parasitic capacitance from forming with the peripheral devices 141, thereby allowing the capacitive devices and the peripheral devices 141 to interact.

In some embodiments, the plurality of dummy memory string structures 161 may penetrate the first dielectric layers 151 and the first conductive layers 152 which are at least partially alternately stacked, and may be hollow insulating structures such as cylinders, cones, cuboids, etc. extending in a direction perpendicular to the first substrate 110. The material of the dummy memory string structure 161 may include silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, and the dummy memory string structure 161 may be formed through photolithography and etching processes as well as thin film deposition processes. In one aspect, the dummy memory string structure 161 may be used to provide mechanical support. On the other hand, the dummy memory string structure 161 provides a receiving space for the through contact 162, and thus one end of the dummy memory string structure 161 is at least partially aligned with the active region (e.g., source/drain) and the gate (e.g., gate stack) of the peripheral device 141 in the first device layer 140, so that the through contact 162 located inside the dummy memory string structure 161 is in contact with the active region and the gate of the peripheral device 141.

In some embodiments, the through contacts 162 are disposed through the dummy memory string structure 161 and at least partially within the dummy memory string structure 161, and thus the critical dimensions of the through contacts 162 should be less than the critical dimensions of the dummy memory string structure 161. The material of the through contact 162 may include a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof, and may be formed by a photolithographic and etching process as well as filling the conductive material. The other end of the through contact 162 that is in contact with the first device layer 140 may be in contact with the first interconnect layer 170, thereby electrically connecting the peripheral devices 141 in the first device layer 140 with the first interconnect layer. By utilizing the dummy memory string structure to electrically connect peripheral devices in the first device layer with the first interconnect layer, the fabrication process can be simplified, reducing the fabrication area required for the through contact.

In some embodiments, a plurality of first gate slit structures 163 are disposed through the alternately stacked first dielectric layers 151 and first conductive layers 152, which may be used to form the first conductive layers 152 in a compatible "gate replacement" process. In some practical applications, specifically, the capacitor layer 150 may be formed by first forming two dielectric layers with different etching selectivity, which are alternately stacked, and then replacing one of the two dielectrics with the first conductive layer 152 using the first gate slit, and the other one being the first dielectric layer 151. The material of the first gate slit structure 163 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, and may be formed through photolithography and etching processes and filling the dielectric material.

The first semiconductor structure 100 may include second dielectric layers 132 and second conductive layers 133 alternately stacked in a direction perpendicular to the first substrate 110 at one side of the second region A2 of the first substrate 110. The second dielectric layer 132 and the second conductive layer 133 may be formed simultaneously with the first dielectric layer 151 and the first conductive layer 152 in the capacitor layer 150, and thus the first dielectric layer 151 and the second dielectric layer 132 may be made of the same dielectric material, and the first conductive layer 152 and the second conductive layer 133 may be made of the same conductive material. Likewise, the method of preparing the second dielectric layer 132 and the second conductive layer 133 may include a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The number of stacked layers of the second dielectric layer 132 and the second conductive layer 133 may be 8, 32, 64, 128, etc., and the greater the number of stacked layers of the second dielectric layer 132 and the second conductive layer 133, the higher the integration of the memory cell. The second conductive layer 133 may serve as a word line for memory cells in the memory string structure 131.

In some embodiments, each of the memory string structures 131 is disposed through the second dielectric layers 132 and the second conductive layers 133 alternately stacked and extends in the direction of the first substrate 110, and thus the memory string structures 131 may be formed in the second dielectric layers 132 and the second conductive layers 133. The memory string structure 131 may have an approximate shape of a cylinder, a cone, a cuboid, and may include a memory layer 1311 and a channel layer 1312 disposed sequentially from outside to inside in a radial direction thereof. In some embodiments, the memory layer 1311 may be a composite layer structure of a tunneling layer, a charge trapping layer, and a blocking layer. The materials of the tunneling layer, the charge trapping layer, and the blocking layer may be silicon oxide, silicon nitride, and silicon oxide in this order, thereby forming the memory layer 1311 having an ONO structure. The material of the channel layer 1312 may be a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon. The memory string structure 131 may be formed in synchronization with the dummy memory string structure 161 through photolithography and etching processes and a thin film deposition process.

It will be appreciated that the portion of the memory layer 1311 and the channel layer 1312 corresponding to each of the second conductive layers 133 in the memory string structure 131 and the second conductive layers 133 together form a memory cell. The second conductive layer may correspond to a control terminal of the memory cell. The plurality of memory cells in the memory string structure 131 are arranged in series in a direction perpendicular to the first substrate 110 and share the channel layer 1312.

In some embodiments, the memory string structure 131 may further include a channel plug 134 at an end of the memory string structure 131 remote from the first substrate 110. The channel plug 134 may be made of the same semiconductor material as the channel layer 1312 and is in contact with the channel layer 1312. The channel plug 134 may function as a drain of the memory string structure 131.

In some embodiments, the second stepped structure at the edge regions of the alternately stacked second dielectric layers 132 and second conductive layers 133 may have a similar structure and formation method to the first stepped structure. Wherein the exposed area of the second conductive layer 132 of the second stepped structure parallel to the first substrate 110 may be used for a contact area of the second conductive via 136 formed in a vertical direction. Since the second conductive layer 133 serves as a word line of the memory cells in the memory string structure 131, the memory cells can be controlled to realize functions of storing and reading data by the second conductive layer 133.

In some embodiments, the first semiconductor structure 100 may further include a semiconductor layer 135 located at a side of the plurality of memory string structures remote from the second semiconductor structure 200, and at least a portion of the memory string structure 131 is located between the semiconductor layer 135 and the second semiconductor structure 200. For example, the semiconductor layer 135 may include a semiconductor material having an N-type dopant with a uniform doping concentration, such as single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. The N-type dopant may include, for example, phosphorus, arsenic, antimony, or any combination thereof, and the doping of the dopant may be accomplished using ion implantation and activation annealing processes. The channel layer 1312 of the memory string structure 131 may extend into the semiconductor layer 135, and a portion of the channel layer 1312 extending into the semiconductor layer 135 is surrounded by the N-type high doping concentration region of the semiconductor layer 135. The N-type semiconductor layer 135 can be used to implement the GIDL-erase operation for the three-dimensional memory 10. It should be appreciated that semiconductor layer 135 may also include a semiconductor material having a P-type dopant of uniform doping concentration such that the portion of channel layer 1312 extending to semiconductor layer 135 is surrounded by the P-type high doping concentration region of semiconductor layer 135. The P-type semiconductor layer 135 can be used to implement a P-well bulk erase operation for the three-dimensional memory 10. In other words. The semiconductor layer may enable a three-dimensional memory formed using the multiple memory string structures and peripheral circuit arrangements described above, compatible with GIDL and/or P-well bulk erase operations.

In some embodiments, a surface of semiconductor layer 135 proximate to the plurality of memory string structures is flush with an upper surface of first device layer 140 distal from first substrate 110. For example, mechanochemical polishing (CMP) may be used to level the upper surfaces of both. Since the alternately stacked first dielectric layers 151 and first conductive layers 152 and the alternately stacked second dielectric layers 132 and second conductive layers 133 may be simultaneously formed, in the case where the surface of the semiconductor layer 135 adjacent to the plurality of memory string structures is flush with the upper surface of the first device layer 140 remote from the first substrate 110, bending at the interface of the alternately stacked first dielectric layers 151 and first conductive layers 152 and the alternately stacked second dielectric layers 132 and second conductive layers 133 may be avoided, thereby affecting the performance of the related devices formed later. In other words, the second dielectric layer 132 may be made flush with the corresponding first dielectric layer 151 along the first direction, and the second conductive layer 133 may be made flush with the corresponding first conductive layer 152 along the first direction. It will be appreciated that the first dielectric layers 151 and the first conductive layers 152 that are alternately stacked and the second dielectric layers 132 and the second conductive layers 133 that are alternately stacked may be formed using a stepwise process, and the present application does not specifically limit that the second dielectric layers 132 are flush with the corresponding first dielectric layers 151 in the first direction and the second conductive layers 133 are flush with the corresponding first conductive layers 152 in the first direction.

In some embodiments, a plurality of second gate slit structures 137 are disposed through the second dielectric layers 132 and the second conductive layers 133 alternately stacked and extend to the semiconductor layer 135. The second gate slit structure 137 is similar to the structure and fabrication process of the first gate slit structure 163 for forming the second conductive layer 133 compatible with a "gate replacement" process. In addition, the second gate slit structure 137 may also be used to divide a plurality of memory string structures into a plurality of memory blocks (blocks) to improve the efficiency of the three-dimensional memory 10 to perform an erase operation. On the other hand, in the case where the material of the second gate slit structure 137 includes a conductive material such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof, the second gate slit structure 137 may serve as a common source of a plurality of memory string structures and may be electrically connected with the first interconnection layer 170.

In some embodiments, the first semiconductor structure 100 in the three-dimensional memory 10 may further include a first interconnect layer 170 to pass electrical signals to and from the second peripheral circuit 220. The first interconnect layer 170 is located at a side of the alternately stacked first/second dielectrics 151/132 and first/second conductive layers 152/133 remote from the first substrate 110, and may include a plurality of interconnect structures 171 extending laterally in parallel with the first substrate 110 and a plurality of contact vias 172 extending in a vertical direction of the first substrate 110. The first interconnect layer 170 may further include one or more inter-layer dielectric (ILD) layers in which the interconnect structure 171 and the contact via 172 may be formed. In other words, the first interconnect layer 170 may include the interconnect structure 171 and the contact via 172 in a plurality of interlayer dielectric layers. The material of the interconnection structure 171 and the contact via 172 may include a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof, among others. The material of the interlayer dielectric layer may comprise a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be appreciated that the interconnect structures 171 and/or contact vias 172 in the first interconnect layer 170 may be electrically connected to the second electrical layer 133 through the second conductive vias 136, to the first conductive layer 152 through the first conductive vias 153, and to the peripheral devices 141 in the first device layer 140 through the through contacts 162.

The second semiconductor structure 200 in the three-dimensional memory 10 may include a second peripheral circuit 220 on the second substrate 210, which cooperates with the first peripheral circuit 120 in the first semiconductor structure 100 as a complete peripheral circuit. Wherein all or part of the peripheral devices in the second peripheral circuit 220 are formed in the second substrate 210 and/or on the second substrate 210, and the peripheral devices in the second peripheral circuit 220 may include any suitable semiconductor devices such as MOSFETs, BJTs, diodes, resistors, capacitors, and inductors. Since the structure and the preparation method of the peripheral device are exemplarily described above, the description is omitted herein.

In some embodiments, the peripheral devices in the first peripheral circuit 120 may include high voltage MOS devices and the peripheral devices in the second peripheral circuit 220 may include low voltage MOS devices and/or ultra-low voltage MOS devices. In other words, the operating voltage of the devices located in the second peripheral circuit 220 may be less than the operating voltage of the devices located in the first peripheral circuit 120. It should be appreciated that, since the peripheral devices in the first peripheral circuit 120 are formed on the same substrate as the plurality of memory string structures, and the high voltage MOS devices have a greater requirement for the thickness of the substrate, the matching of the requirement for the thickness of the substrate for the memory string structures can be better. In addition, the high-voltage MOS device can resist high temperature and has good compatibility with the preparation process of the memory string structure under the high-temperature condition. By reasonably distributing the types of devices in the first peripheral circuit and the second peripheral circuit, the manufacturing process of the peripheral devices and the memory string structure can be optimized.

In some embodiments, the second semiconductor structure 200 in the three-dimensional memory 10 may further include a second interconnect layer 230 to pass electrical signals to and from the plurality of memory string structures and/or the first peripheral circuit 120. Since the structure and the preparation method in the second interconnect layer 230 are similar to those of the first interconnect layer 170, and the structure and the preparation method of the first interconnect layer 170 are described in detail above, the description thereof will not be repeated here. It should be appreciated that the interconnect structures and/or contact vias in the second interconnect layer 230 may be electrically connected to peripheral devices in the second peripheral circuit 220.

In some embodiments, the first interconnect layer 170 in the first semiconductor structure 100 may have a first bonding surface 182 exposing the plurality of first bonding contacts 181 and the second interconnect layer 230 in the second semiconductor structure 200 may have a second bonding surface 184 exposing the plurality of second bonding contacts 183. Wherein the plurality of first bonding contacts 181 may have a dielectric therebetween that electrically isolates the first bonding contacts 181, and similarly the plurality of second bonding contacts 183 may have a dielectric therebetween that electrically isolates the second bonding contacts 183. The material of the first/second bonding contacts 181/183 may include a conductive material such as tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The material of the dielectric between the first/second bond contacts 181/183 for electrical isolation may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The first/second bond contacts 181/183 and the surrounding dielectric may be used to achieve a hybrid bond connection, i.e. the first/second bond contacts 181/183 and the surrounding dielectric contact at the first/second bond faces 182/184, thereby electrically connecting the first bond contacts 181 and the corresponding second bond contacts 183. It should be appreciated that after the first semiconductor structure 100 and the second semiconductor structure 200 are bonded together, the first bonding interface 182 and the second bonding interface 183 overlap.

The three-dimensional memory provided by the application optimizes the arrangement form of the peripheral circuit and the plurality of memory string structures by arranging a part of the peripheral circuit and the plurality of memory string structures in the same semiconductor structure, thereby optimizing the electric signal transmission performance of the peripheral circuit and the memory string structures, and in addition, by forming the capacitor layer by using the dielectric layers and the conductive layers which are alternately stacked for forming the memory string structures, the high-capacity capacitor device can be provided for the peripheral circuit, and the manufacturing cost of the capacitor device is simplified.

The application also provides a method 1000 for manufacturing the three-dimensional memory. Fig. 3 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application. Fig. 4A to 4I are schematic process cross-sectional views of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application. It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in a different order than shown in fig. 3. The above-described steps S100 to S300 are further described below in conjunction with fig. 4A to 4I.

In forming the first semiconductor structure in step S100, it includes: step S110 forms a first peripheral circuit on a first region of the substrate and step S120 forms a plurality of memory string structures on a second region of the substrate.

In step S100, as shown in fig. 4A, the substrate 110 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, gallium nitride, silicon carbide, glass, III-V compound semiconductors, or any combination thereof.

In some embodiments, the first device layer 140 may be formed on the first region A1 of the substrate 110, and the semiconductor layer 135 may be formed on the second region A2 of the substrate 110. In the step of forming the first device layer 140, a process thereof is described in detail taking the formation of a P-type and/or N-type MOSFET as an example. An N-type dopant such as phosphorus, arsenic, antimony, or any combination thereof may be doped to form an N-well 142 in the substrate 110 and/or a P-type dopant such as boron may be doped to form a P-well 142 in the substrate 110 using ion implantation and activation annealing. Further, gate stacks 143 may be formed within the regions of N-well and/or P-well 142 using techniques such as CVD, PVD, ALD, sputtering, thermal oxidation/nitridation, or any combination thereof. The gate stack 143 may include a gate dielectric and a gate conductor, and the material of the gate dielectric may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide. The material of the gate conductor may include a metallic material such as tungsten, cobalt, nickel, copper, aluminum, etc., and any other suitable conductive material such as polysilicon, poly-germanium-silicon, titanium nitride, tantalum nitride, etc. Alternatively, the step of forming the semiconductor layer 135 may be omitted, and a portion corresponding to the second region A2 of the substrate 110 is removed in a subsequent process, and the semiconductor layer 135 is formed at the portion.

Further, the substrate 110 may also be patterned, filled with an insulating material, and polished using photolithography and etching processes to form shallow trench isolation 145 on the substrate 110 surrounding the active area of the peripheral device 141. The material of the shallow trench isolation 145 may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, low temperature oxide, high temperature oxide, and any combination thereof.

It should be understood that peripheral device 141 is not limited to MOSFETs. The structure of other peripheral devices (e.g., diodes, resistors, inductors, BJTs, etc.) may be formed simultaneously during the process of fabricating the MOSFET by different mask designs and layouts.

In some embodiments, during the process of forming the first device layer 140 on the substrate 110, the method 1000 of fabricating a three-dimensional memory may further include: a semiconductor layer 135 is formed on the second region A2. In this step, a thin film deposition process such as CVD, PVD, ALD, sputtering, and any combination thereof, and/or an epitaxial growth process may be used to form the semiconductor layer 135 on the second region A2 of the substrate 110. The semiconductor layer 135 may have the same or different semiconductor material as the substrate 110, such as single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. And may be used to form a plurality of memory string structures to perform the auxiliary body bias of the GIDL and/or P-well erase operations during subsequent processing.

In some embodiments, the upper surface of semiconductor layer 135 remote from substrate 110 may be flush with the upper surface of first device layer 140 remote from substrate 110, for example, using a CMP process, which may prevent the formation of alternating stacked dielectric and conductive layers during subsequent processing from bending at the interface of semiconductor layer 135 and first device layer 140, thereby affecting the fabrication process and performance of the subsequently formed related devices. It should be appreciated that after forming the plurality of peripheral devices 141 on the first region A1 of the substrate 110, a thin film deposition process such as PVD, CVD, ALD and any combination thereof may be used to cover the peripheral devices 141 with a dielectric material, and a CMP process may be used to level the upper surfaces of the semiconductor layer 135 and the first device layer 140.

In some embodiments, after the step of forming the first device layer 140 and the semiconductor layer 135, the method 1000 further includes the step of forming dielectric layers 151/132 and the sacrificial layer 191 of alternating dielectric on a side of the first device layer 140 and the semiconductor layer 135 remote from the substrate 110 to form a first dielectric layer 151 and a first conductive layer 152 for forming a capacitor layer corresponding to the first region A1 and a second dielectric layer 132 and a second conductive layer for forming a memory string structure corresponding to the second region A2 of the substrate 110 during a subsequent process. Wherein dielectric layers 151/132 and sacrificial layer 191 may have different etch selectivity, sacrificial layer 191 may be removed and replaced with a conductive material during a subsequent process to form a conductive layer. Illustratively, the material of dielectric layers 151/132 may include silicon oxide and the material of sacrificial layer 191 may include silicon nitride. It should be understood that while the present application employs an implementation in which the sacrificial layer is subsequently replaced with a filled conductive material to form the conductive layer, the implementation in which the conductive layer is formed in the present application is not limited thereto, and may also be implemented in a manner such as directly alternating the dielectric layer and the conductive layer.

In some embodiments, as shown in fig. 4B, the alternately stacked dielectric layers 151/132 and the sacrificial layers 191 may be formed to have a first step structure at an edge region corresponding to the first region A1 and a second step structure at an edge region corresponding to the second region A2 by performing a plurality of "trim-etch" cyclic processes to the alternately stacked dielectric layers 151/132 and the sacrificial layers 191.

In some embodiments, a plurality of memory string structures 131 may be formed within the alternately stacked dielectric layers 132 and sacrificial layers 191 corresponding to the second regions A2 using, for example, a dry or wet etching process and a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Specifically, openings extending to the semiconductor layer 135 may be formed in the dielectric layers 132 and the sacrificial layers 191 alternately stacked corresponding to the second region A2 using, for example, a dry or wet etching process. Further, a memory layer 1311 including a barrier layer, a charge trapping layer, and a tunneling layer, and a channel layer 1312 may be sequentially formed within the opening using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Illustratively, the materials of the tunneling layer, charge trapping layer, and blocking layer within the memory layer 1311 may include silicon oxide, silicon nitride, and silicon oxide, in that order. The material of the channel layer 1312 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon, and any combination thereof. Alternatively, in this step, the memory string structure 131 may be extended into a portion corresponding to the second region A2 of the substrate 110 without forming the semiconductor layer 135 in advance.

In some embodiments, a plurality of dummy memory string structures 161 may be formed within the alternately stacked dielectric layers 151 and sacrificial layers 191 corresponding to the first region A1 using, for example, a dry or wet etching process and a thin film deposition process such as CVD, PVD, ALD or any combination thereof. In one aspect, the dummy memory string structure 161 may be used to provide mechanical support, and the dummy memory string structure 161 may not have a memory function, so that a dielectric material may be filled in the formed opening to form the dummy memory string structure 161. On the other hand, the dummy memory string structure 161 may provide a receiving space for the through-contact formed in the subsequent process, so that one end of the dummy memory string structure 161 extending toward the first device layer 140 is at least partially aligned with the active region (e.g., source/drain) and the gate (e.g., gate stack) of the peripheral device 141 in the first device layer 140, thereby enabling the through-contact located inside the dummy memory string structure 161 to contact the active region and the gate of the peripheral device 141.

In some embodiments, the method 1000 may include a step of replacing the sacrificial layer 191 with the first conductive layer 152 using the gate slit structure, and this step may be compatible with the step of forming the capacitor layer 150. Specifically, a first gate slit extending toward the substrate 110 in the dielectric layer 151 and the sacrificial layer 191 alternately stacked corresponding to the first region A1 may be formed using, for example, a dry or wet etching process, and the first gate slit may extend in the x-direction of the substrate 110. Further, all of the sacrificial layer 191 corresponding to the first region A1 may be removed using, for example, a wet etching process using the formed first gate slit as a passage for an etchant, to form a plurality of sacrificial gaps. Further, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form the first conductive layer 152 within the sacrificial gap. The first conductive layer 152 may be made of a conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, silicide, or any combination thereof. After the above process, the capacitor layer 150 including the first dielectric layers 151 and the first conductive layers 152 alternately stacked corresponding to the first region A1 may be formed, and two adjacent first conductive layers 152 may serve as two poles of the capacitor device. Alternatively, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the first gate slit with a dielectric material to form the first gate slit structure 163.

In some embodiments, a similar process may be used to replace the sacrificial layer 191 corresponding to the second region A2 with the second conductive layer 133 by using the second gate slit structure 137, which is not described herein. The second conductive layer 133 may serve as a word line of the memory string structure 131. Alternatively, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to first form an isolation layer within the second gate slit and refill a conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide, or any combination thereof, to form the second gate slit structure 137 and act as a common source for the plurality of memory string structures. Wherein the material of the isolation layer may comprise a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

It should be understood that after the step of forming the first and second stepped structures, the alternately stacked dielectric layers 151/132 and the sacrificial layer 191 are separated in the region corresponding to the boundary of the first and second regions A1 and A2, and thus a plurality of gate slits are formed in the dielectric layers 151/132 and the sacrificial layer 191 corresponding to the first and second regions A1 and A2, respectively, to replace the sacrificial layer with a conductive layer.

In some embodiments, after the step of forming the memory string structure 131, the dummy memory string structure 161, and the first/second gate slit structures 163/137, an insulating capping layer may be formed on the side of the substrate 110 where the above structures are formed using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The material of the insulating cap layer may include silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, the method 1000 may include the step of forming a plurality of first conductive vias, a plurality of second conductive vias. The formation process thereof will be described in detail taking the formation of the first conductive path as an example. As shown in fig. 4C, an opening extending to the exposed first conductive layer 152 of the first stepped structure may be formed in the insulating cover layer corresponding to the first region A1 using, for example, a dry or wet etching process. Further, the opening may be filled with a conductive material using a thin film deposition process such as ALD, CVD, PVD or any combination thereof to form the first conductive via 153. Since the process steps for forming the second conductive via 136 are similar to those for forming the first conductive via 153, the description thereof will not be repeated here. It should be noted that the plurality of first conductive vias 153 may contact a portion of the first conductive layer 152 of the first ladder structure, so that the capacitor layer 150 may be equivalent to a capacitor device of a different circuit structure according to the arrangement of the first conductive vias 153. And in various arrangements of the first conductive via 153, the first conductive via 153 may be in contact connection with a second portion of the first conductive layer 152 remote from the first device layer 140. The first conductive layer 152 may include a first portion and a second portion disposed in sequence away from the first device layer 140, and the first portion may include at least one first conductive layer. The first portion of the first conductive layer 152 may act as a shield between the capacitive devices in the capacitor layer 150 and the peripheral devices 141 in the first device layer 140 to avoid parasitic capacitance from forming with the peripheral devices 141, thereby allowing the capacitive devices and the peripheral devices 141 to interact.

In some embodiments, the method 1000 may include the step of forming a plurality of through contacts 162. The through contact 162 penetrating the dummy memory string structure 161 may be formed using, for example, a dry or wet etching process and a thin film deposition process. The through contact 162 may be made of a conductive material such as tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide, as well as any combination thereof.

In some embodiments, step S100 further includes a step of forming the first interconnect layer 170. As shown in fig. 4D, the first interconnect layer 170 includes a plurality of interconnect structures 171 extending laterally parallel to the direction of the substrate 110 and a plurality of contact vias 172 extending perpendicular to the direction of the substrate 110. In this step, a thin film deposition process such as CVD, PVD, ALD, sputtering, spin coating, or any combination thereof may be used to first form the dielectric fill layer. The material of the dielectric fill layer may comprise any suitable material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric, among others. Further, a plurality of first openings extending through the dielectric fill layer and exposing at least a portion of the memory string structure 131, the first/second conductive vias 153/136, and the through contacts 162 in a direction perpendicular to the substrate 110 are formed. Further, a thin film deposition process of CVD, PVD, ALD or any combination thereof may be used to fill the first opening with a conductive material such as tungsten, cobalt, copper, aluminum, titanium nitride, tantalum nitride, doped silicon, silicide or any combination thereof to form the contact via 172. Further, the same process may be used to form a dielectric fill layer, then a laterally extending second opening through the dielectric fill layer exposing at least a portion of the contact via 172, and then a conductive material is filled into the second opening to form the interconnect structure 171. Further, the above process may be repeated to sequentially form the contact via layer and the interconnect structure layer at different levels until the first peripheral circuit 120 and/or the plurality of memory string structures to be in contact electrical connection with the first interconnect layer 170 are brought into a predetermined functional circuit connection relationship. The dielectric filling layer treated by the process can form discrete layer structures at different levels, and can be further called an interlayer dielectric layer. In other words, the first interconnect layer 170 may include the interconnect structure 171 and the contact via 172 in a plurality of interlayer dielectric layers.

It should be appreciated that the interconnect structures 171 and/or contact vias 172 in the first interconnect layer 170 may be electrically connected to the first conductive layer 152 through the first conductive vias 153, to the second conductive layer 133 through the second conductive vias 136, and to the peripheral devices 141 in the first device layer 140 through the through contacts 162.

In forming the second semiconductor structure at step S200, it includes: step S210 forms a second peripheral circuit on a second substrate. In this step, as shown in fig. 4E, all or part of the peripheral devices in the second peripheral circuit 220 are formed in the second substrate 210 and/or on the second substrate 210, and the peripheral devices in the second peripheral circuit may include any suitable semiconductor devices such as MOSFETs, BJTs, diodes, resistors, capacitors, and inductors. Since the structure and the preparation method of the peripheral device are exemplarily described above, the description is omitted herein.

In some embodiments, as shown in fig. 4F, step S200 further includes a step of forming a second interconnect layer 230. Since the structure and the preparation method in the second interconnect layer 230 are similar to those of the first interconnect layer 170, and the structure and the preparation method of the first interconnect layer 170 are described in detail above, the description thereof will not be repeated here. It should be appreciated that the interconnect structures and/or contact vias in the second interconnect layer 230 may be electrically connected to peripheral devices in the second peripheral circuit 220.

In bonding the first semiconductor structure and the second semiconductor structure in step S300, as shown in fig. 4G, the first semiconductor structure 100 and the second semiconductor structure 200 may be electrically connected by a bonding connection manner, so that the first peripheral circuit 120 and/or the plurality of memory string structures are electrically connected with the second peripheral circuit 220.

In some embodiments, after the above-described processing, the interconnect structures 171 and/or the contact vias 172 in the first interconnect layer 170 may be exposed to a surface of the first interconnect layer 170 remote from the substrate 110 and may serve as the first bonding contacts 181 of the first semiconductor structure 100. Meanwhile, the plurality of first bonding contacts 181 may have a dielectric therebetween to electrically isolate them. Similarly, the interconnect structures and/or contact vias in the second interconnect layer 230 may be exposed to a surface of the second interconnect layer 230 remote from the second substrate 210 and may serve as the second bonding contacts 183 of the second semiconductor structure 200. Meanwhile, the plurality of second bonding contacts 183 may have a dielectric therebetween to electrically isolate them. Further, the first semiconductor structure 100 may be positioned on the second semiconductor structure 200 by aligning the first bonding contact 181 and the second bonding contact 183 such that the aligned positions of the first bonding contact 181 and the second bonding contact 183 are electrically connected, thereby electrically connecting the first semiconductor structure 100 and the second semiconductor structure 200.

The first peripheral circuit 120 and the second peripheral circuit 220 may collectively serve as peripheral circuits for a plurality of memory string structures, supporting the plurality of memory string structures to perform various functions. The external electrical circuit may comprise a plurality of digital, analog and/or digital-analog mixed partial circuit modules. The circuit module may include, for example, a page buffer, an address decoder, a read amplifier, and the like.

According to the preparation method of the three-dimensional memory, part of the peripheral circuit and the memory string structures are arranged on the same substrate, so that the arrangement form of the peripheral circuit and the memory string structures is optimized, and the electric signal transmission performance of the peripheral circuit and the memory string structures is further optimized. Further, by forming the capacitor layer by using alternately stacked dielectric layers and conductive layers for forming a plurality of memory string structures, it is possible to provide a high-capacity capacitor device for a peripheral circuit and to simplify the manufacturing cost of the capacitor device.

In some embodiments, the method 1000 of fabricating a three-dimensional memory further includes the steps described below. As shown in fig. 4H, the side of the substrate 110 where the memory string structure 131 and/or the first peripheral circuit 120 are not formed may be thinned using, for example, a dry/wet etching process or a mechanochemical polishing process. Further, portions of the second region of the substrate 110 may be removed using the same process to expose the semiconductor layer 135. Further, as shown in fig. 4I, an opening may be formed at a portion of the semiconductor layer 135 corresponding to the memory string structure 131 using, for example, a dry/wet etching process to expose a portion of the memory string structure 131 extending to the semiconductor layer 135. Further, the memory layer 1311 in the portion of the memory string structure 131 extending into the semiconductor layer 135 may be removed using, for example, a dry/wet etching process to expose the channel layer 1312. Further, the opening may be filled using a thin film deposition process such as CVD, PVD, ALD, sputtering, spin coating, or any combination thereof, and the highly doped region corresponding to the filling location may be formed using a process such as ion implantation and laser annealing, such that the portion of the channel layer 1312 exposed to the semiconductor layer 135 is surrounded by the highly doped region of the semiconductor layer 135. Alternatively, in this step, without forming the semiconductor layer in advance, a portion corresponding to the second region of the substrate may be removed using, for example, a dry/wet etching process to expose the memory string structure extending into the memory string structure in the portion corresponding to the second region of the substrate. Further, the same process may be used to remove the memory layer in the portion of the memory string structure corresponding to the second region of the substrate to expose the channel layer. Further, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a semiconductor layer overlying the memory string structure.

It should be understood that after the above-described process, the portion corresponding to the second region A2 of the base 110 is removed, and the portion corresponding to the first region A1 of the base 110 is left, and hereinafter, this portion is referred to as "first substrate 110".

In some embodiments, as shown in fig. 4I, in the step of forming the back-end-of-line interconnect layer, a thin film deposition process such as CVD, PVD, ALD, sputtering, spin-coating, or any combination thereof may be employed to form the first insulating layer 193 to cover the semiconductor layer 135 and the first substrate 110. The material of the first insulating layer 193 may include a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Alternatively, a through contact 192 may be formed sequentially through the first insulating layer 193, the semiconductor layer 135 using, for example, a dry or wet etching process, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Wherein the material of the through contact 192 may comprise a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof, for forming an electrical connection channel with the second peripheral circuit 220 located in the second semiconductor structure 200. During the process of forming the through contacts 192, a plurality of through contacts (not shown) electrically connected to at least a portion of the first device layer 140 and the plurality of memory string structures 131 may be formed in the first insulating layer 193 using the same process.

Further, a re-wiring layer 194 is formed on a side of the first insulating layer 193 away from the first substrate 110 or the semiconductor layer 135. Specifically, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a second insulating layer on a side of the first insulating layer 193 remote from the first substrate 110 or the semiconductor layer 135. The material of the second insulating layer may be the same as that of the first insulating layer 193. Further, photolithography and etching processes, as well as thin film deposition processes, may be employed to form pads that are electrically connected to at least a portion of the through contacts (e.g., through contacts 192). The material of the pads may include a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof for extracting the first peripheral circuit 120, the second peripheral circuit 220, and/or the plurality of memory string structures. After the above process, the first insulating layer 193 and the re-wiring layer 194 may be referred to as a back-end-of-line interconnect layer 195.

The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.

Claims

1. A three-dimensional memory, comprising:

a first semiconductor structure, comprising: a first peripheral circuit and a plurality of memory string structures distributed along a first direction;

a second semiconductor structure, comprising: a second substrate and a second peripheral circuit on the second substrate;

wherein the first semiconductor structure and the second semiconductor structure are bonded in a second direction perpendicular to the first direction to electrically connect the plurality of memory string structures and/or the first peripheral circuit with the second peripheral circuit;

the first peripheral circuit includes a capacitor layer including a first dielectric layer and a first conductive layer alternately stacked;

the first semiconductor structure further includes: and a second dielectric layer and a second conductive layer alternately stacked, wherein the memory string structure is formed in the second dielectric layer and the second conductive layer alternately stacked, and at least a part of the second dielectric layer is disposed flush with the corresponding first dielectric layer along the first direction, and at least a part of the second conductive layer is disposed flush with the corresponding first conductive layer along the first direction.

2. The three-dimensional memory of claim 1, wherein the first peripheral circuit further comprises: the semiconductor device comprises a first substrate and a plurality of peripheral devices at least partially positioned on the first substrate, wherein the first substrate, the plurality of peripheral devices and the capacitor layer are sequentially arranged along the second direction.

3. The three-dimensional memory of claim 2, wherein the peripheral devices comprise high voltage MOS devices.

4. The three-dimensional memory of claim 2, wherein the first semiconductor structure further comprises:

a dummy memory string structure extending through at least a portion of the alternately stacked first dielectric layers and first conductive layers; and

and a through contact penetrating through the dummy memory string structure and electrically connected with the peripheral device.

5. The three-dimensional memory of claim 4, wherein the first conductive layer comprises a first portion and a second portion disposed in sequence away from the peripheral device, wherein the first semiconductor structure further comprises: and a conductive path in contact with the second portion.

6. The three-dimensional memory of claim 1, wherein the first semiconductor structure further comprises a semiconductor layer on a side of the plurality of memory string structures remote from the second semiconductor structure, wherein the memory string structures are located between the semiconductor layer and the second semiconductor structure.

7. The three-dimensional memory of claim 5, wherein the first semiconductor structure further comprises:

A first interconnect layer covering the alternating stacked first dielectric and first conductive layer and the alternating stacked second dielectric and second conductive layer and electrically connected to the peripheral device and to the conductive via through the through contact.

8. The three-dimensional memory of claim 3, wherein an operating voltage of a device located in the second peripheral circuit is less than an operating voltage of a device located in the first peripheral circuit.

9. A method for manufacturing a three-dimensional memory, comprising:

forming a first semiconductor structure, comprising:

forming a first peripheral circuit on a first region of a substrate;

forming a plurality of memory string structures on a second region of the substrate;

forming a second semiconductor structure, comprising:

forming a second peripheral circuit on a second substrate; and

bonding the first semiconductor structure and the second semiconductor structure to electrically connect the memory string structure and/or the first peripheral circuit with the second peripheral circuit;

wherein forming the first peripheral circuit on the first region of the substrate comprises:

forming a capacitor layer including alternately stacked first dielectric layers and first conductive layers on the first region;

Wherein, while forming the first dielectric layer and the first conductive layer, forming alternately stacked second dielectric layers and second conductive layers in the second region, wherein the plurality of memory string structures are formed in the alternately stacked second dielectric layers and second conductive layers.

10. The method of manufacturing according to claim 9, wherein the step of forming a capacitor layer including alternately stacked first dielectric layers and first conductive layers on the first region includes:

forming the first dielectric layers and first sacrificial layers alternately stacked on the first region;

forming a gate slit through the alternately stacked first dielectric layers and first sacrificial layers;

removing the sacrificial layer through the gate slit to form a sacrificial gap; and

the first conductive layer is formed within the sacrificial gap to form a capacitor layer.

11. The method of manufacturing of claim 9, wherein prior to the step of forming a capacitor layer comprising alternating stacked first dielectric layers and first conductive layers on the first region, the method further comprises:

a plurality of peripheral devices is formed at least partially over the first region, wherein the plurality of peripheral devices are located between the substrate and the capacitor layer.

12. The method of manufacturing according to claim 11, wherein the peripheral device comprises a high voltage MOS device.

13. The method of manufacturing of claim 11, wherein after the step of forming a plurality of peripheral devices at least partially on the first region, the method further comprises:

forming a dummy memory string structure extending through at least a portion of the alternately stacked first dielectric layers and first conductive layers; and

a through contact is formed through the dummy memory string structure and electrically connected to the peripheral device.

14. The method of manufacturing as claimed in claim 13, wherein the first conductive layer comprises a first portion and a second portion disposed in sequence away from the peripheral device, wherein,

conductive vias are formed in contact with the second portion while forming through contacts extending through the dummy memory string structure and electrically connected to the peripheral device.

15. The method of manufacturing of claim 14, wherein after the step of forming a through contact through the dummy memory string structure and electrically connected to the peripheral device, the method further comprises:

and forming a first interconnection layer to cover the alternately stacked first dielectric layers and first conductive layers, wherein the first interconnection layer is electrically connected with the peripheral device through the through contact and electrically connected with the conductive via.

16. The method of manufacturing according to claim 12, wherein an operating voltage of a device located in the second peripheral circuit is smaller than an operating voltage of a device located in the first peripheral circuit.

17. The method of manufacturing of claim 9, wherein after the step of bonding the first semiconductor structure and the second semiconductor structure, the method comprises:

removing a portion of the substrate corresponding to the second region to expose the memory string structure; and

and forming a semiconductor layer covering the memory string structure.

18. The method of manufacturing of claim 17, wherein after the step of forming the semiconductor layer covering the memory string structure, the method further comprises:

and forming a back-end-of-line interconnection layer covering the semiconductor layer and a portion of the substrate corresponding to the first region.