SG10201805399SA - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- SG10201805399SA SG10201805399SA SG10201805399SA SG10201805399SA SG10201805399SA SG 10201805399S A SG10201805399S A SG 10201805399SA SG 10201805399S A SG10201805399S A SG 10201805399SA SG 10201805399S A SG10201805399S A SG 10201805399SA SG 10201805399S A SG10201805399S A SG 10201805399SA
- Authority
- SG
- Singapore
- Prior art keywords
- region
- active
- substrate
- guard
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 3
- 238000002955 isolation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region. FIG 39
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170086435A KR102282136B1 (en) | 2017-07-07 | 2017-07-07 | Semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201805399SA true SG10201805399SA (en) | 2019-02-27 |
Family
ID=64903420
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201805399SA SG10201805399SA (en) | 2017-07-07 | 2018-06-22 | Semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US10515819B2 (en) |
KR (1) | KR102282136B1 (en) |
CN (1) | CN109216347B (en) |
SG (1) | SG10201805399SA (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102442933B1 (en) * | 2017-08-21 | 2022-09-15 | 삼성전자주식회사 | Three-dimensional semiconductor device |
KR20200073339A (en) | 2018-12-13 | 2020-06-24 | 삼성전자주식회사 | Three-dimensional semiconductor memory devices |
KR20220128111A (en) | 2021-03-12 | 2022-09-20 | 삼성전자주식회사 | Variable resistance memory device |
KR20220149828A (en) | 2021-04-30 | 2022-11-09 | 삼성전자주식회사 | Semiconductor devices |
CN113690173B (en) * | 2021-09-07 | 2024-04-05 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
CN115000060B (en) * | 2022-07-19 | 2022-10-18 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure and forming method thereof |
Family Cites Families (34)
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KR0155874B1 (en) | 1995-08-31 | 1998-12-01 | 김광호 | Isolating method and planerizing method |
EP0813239A1 (en) | 1996-02-21 | 1997-12-17 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
KR100235938B1 (en) * | 1996-06-24 | 1999-12-15 | 김영환 | A fabrication method of semicircle silicon |
JP3719650B2 (en) * | 2000-12-22 | 2005-11-24 | 松下電器産業株式会社 | Semiconductor device |
JP2004153015A (en) | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
KR100536805B1 (en) | 2004-05-11 | 2005-12-14 | 동부아남반도체 주식회사 | Semiconductor device and method of manufacturing the same |
KR100650870B1 (en) | 2005-08-08 | 2008-07-16 | 주식회사 하이닉스반도체 | Flash memory device and method for fabricating the same |
JP2007141962A (en) * | 2005-11-15 | 2007-06-07 | Toshiba Corp | Semiconductor storage device and its manufacturing method |
JP2008085101A (en) * | 2006-09-28 | 2008-04-10 | Toshiba Corp | Semiconductor device |
KR20080039095A (en) | 2006-10-31 | 2008-05-07 | 주식회사 하이닉스반도체 | Method for manufacturing nand type flash memory device |
JP5076570B2 (en) * | 2007-03-16 | 2012-11-21 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
KR101286644B1 (en) | 2007-11-08 | 2013-07-22 | 삼성전자주식회사 | Semiconductor device including dummy gate part and method of fabricating thereof |
KR101256551B1 (en) | 2008-03-06 | 2013-04-19 | 주식회사 엘지화학 | Cmp slurry and polishing method using the same |
JP5103232B2 (en) * | 2008-03-18 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
KR101043870B1 (en) | 2008-12-19 | 2011-06-22 | 주식회사 하이닉스반도체 | Semiconductor having CMP dummy pattern and method for manufacturing the CMP dummy pattern |
US8321828B2 (en) | 2009-02-27 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance |
JP2011082384A (en) * | 2009-10-08 | 2011-04-21 | Toshiba Corp | Semiconductor memory device |
KR101615650B1 (en) * | 2009-11-19 | 2016-04-26 | 삼성전자주식회사 | Semiconductor devices and methods of forming the same |
CN102822959B (en) * | 2010-03-30 | 2015-01-28 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing same |
KR101834930B1 (en) * | 2011-02-01 | 2018-03-06 | 삼성전자 주식회사 | Vertical structure non-volatile memory device |
KR20120129682A (en) | 2011-05-20 | 2012-11-28 | 삼성전자주식회사 | Semiconductor device |
JP6037499B2 (en) * | 2011-06-08 | 2016-12-07 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
KR102139944B1 (en) * | 2013-11-26 | 2020-08-03 | 삼성전자주식회사 | Three dimensional semiconductor device |
KR20150139223A (en) | 2014-06-03 | 2015-12-11 | 삼성전자주식회사 | Semiconductor device |
KR102258369B1 (en) * | 2014-06-23 | 2021-05-31 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
KR102239602B1 (en) * | 2014-08-12 | 2021-04-14 | 삼성전자주식회사 | Semiconductor Device and Method of fabricating the same |
KR102270099B1 (en) | 2014-12-08 | 2021-06-29 | 삼성전자주식회사 | Semiconductor devices having dummy patterns and methods for fabricating the same |
KR102276546B1 (en) * | 2014-12-16 | 2021-07-13 | 삼성전자주식회사 | Moisture blocking structure and/or guard ring, semiconductor device including the same, and method of manufacturing the same |
KR102310511B1 (en) * | 2014-12-19 | 2021-10-08 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
JP2016149409A (en) | 2015-02-10 | 2016-08-18 | マイクロン テクノロジー, インク. | Semiconductor device |
US9613953B2 (en) * | 2015-03-24 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, semiconductor device layout, and method of manufacturing semiconductor device |
US20160293625A1 (en) * | 2015-03-31 | 2016-10-06 | Joo-Heon Kang | Three Dimensional Semiconductor Memory Devices and Methods of Fabricating the Same |
KR102424964B1 (en) * | 2015-09-23 | 2022-07-25 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
KR102506430B1 (en) * | 2015-11-27 | 2023-03-08 | 삼성전자주식회사 | Method for manufacturing semiconductor device |
-
2017
- 2017-07-07 KR KR1020170086435A patent/KR102282136B1/en active IP Right Grant
- 2017-12-18 US US15/844,681 patent/US10515819B2/en active Active
-
2018
- 2018-05-25 CN CN201810516388.9A patent/CN109216347B/en active Active
- 2018-06-22 SG SG10201805399SA patent/SG10201805399SA/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN109216347B (en) | 2023-11-14 |
US20190013206A1 (en) | 2019-01-10 |
US10515819B2 (en) | 2019-12-24 |
KR102282136B1 (en) | 2021-07-27 |
KR20190005574A (en) | 2019-01-16 |
CN109216347A (en) | 2019-01-15 |
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