SG10201805426YA - Three-dimensional semiconductor device - Google Patents
Three-dimensional semiconductor deviceInfo
- Publication number
- SG10201805426YA SG10201805426YA SG10201805426YA SG10201805426YA SG10201805426YA SG 10201805426Y A SG10201805426Y A SG 10201805426YA SG 10201805426Y A SG10201805426Y A SG 10201805426YA SG 10201805426Y A SG10201805426Y A SG 10201805426YA SG 10201805426Y A SG10201805426Y A SG 10201805426YA
- Authority
- SG
- Singapore
- Prior art keywords
- step portion
- semiconductor device
- dimensional semiconductor
- sequentially lowered
- pad regions
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
OF THE DISCLOSURE A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction. FIG. 6
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170097636A KR102428273B1 (en) | 2017-08-01 | 2017-08-01 | Three-dimensional semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201805426YA true SG10201805426YA (en) | 2019-03-28 |
Family
ID=65230000
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201805426YA SG10201805426YA (en) | 2017-08-01 | 2018-06-25 | Three-dimensional semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US10453857B2 (en) |
KR (1) | KR102428273B1 (en) |
CN (1) | CN109326607B (en) |
SG (1) | SG10201805426YA (en) |
Families Citing this family (16)
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KR102373818B1 (en) * | 2017-07-18 | 2022-03-14 | 삼성전자주식회사 | Semiconductor devices |
KR20200047882A (en) * | 2018-10-25 | 2020-05-08 | 삼성전자주식회사 | Three-dimensional semiconductor device |
KR20200114285A (en) * | 2019-03-28 | 2020-10-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR20200132136A (en) * | 2019-05-15 | 2020-11-25 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
KR20210010725A (en) | 2019-07-18 | 2021-01-28 | 삼성전자주식회사 | Semiconductor device incuding stack structure haing gate region and insulating region |
JP2021072341A (en) * | 2019-10-30 | 2021-05-06 | キオクシア株式会社 | Semiconductor device |
KR20210051262A (en) | 2019-10-30 | 2021-05-10 | 삼성전자주식회사 | Semiconductor memory device and method of manufaturing the semiconductor memory device |
KR20210073143A (en) | 2019-12-10 | 2021-06-18 | 삼성전자주식회사 | Semiconductor device |
CN111244097B (en) * | 2020-01-13 | 2022-08-23 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
CN113270414A (en) * | 2020-03-23 | 2021-08-17 | 长江存储科技有限责任公司 | Staircase structure in three-dimensional memory device and method for forming the same |
CN114586153A (en) | 2020-03-23 | 2022-06-03 | 长江存储科技有限责任公司 | Staircase structure in three-dimensional memory device and method for forming the same |
JP2022540024A (en) * | 2020-03-23 | 2022-09-14 | 長江存儲科技有限責任公司 | 3D memory device |
KR20220000096A (en) * | 2020-06-25 | 2022-01-03 | 삼성전자주식회사 | Semiconductor device |
CN112470275B (en) | 2020-10-29 | 2024-01-09 | 长江存储科技有限责任公司 | Coaxial stepped structure in three-dimensional memory device and method of forming the same |
KR20220099382A (en) * | 2021-01-06 | 2022-07-13 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of semiconductor device |
CN112768468B (en) * | 2021-01-22 | 2024-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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US20130009274A1 (en) * | 2009-12-31 | 2013-01-10 | Industry-University Cooperation Foundation Hanyang University | Memory having three-dimensional structure and manufacturing method thereof |
KR101660488B1 (en) | 2010-01-22 | 2016-09-28 | 삼성전자주식회사 | Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same |
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JP5550604B2 (en) | 2011-06-15 | 2014-07-16 | 株式会社東芝 | Three-dimensional semiconductor device and manufacturing method thereof |
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JP2013055136A (en) * | 2011-09-01 | 2013-03-21 | Toshiba Corp | Nonvolatile semiconductor memory device and method of manufacturing the same |
KR101981996B1 (en) | 2012-06-22 | 2019-05-27 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
JP2014027104A (en) * | 2012-07-26 | 2014-02-06 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
KR101974352B1 (en) * | 2012-12-07 | 2019-05-02 | 삼성전자주식회사 | Method of Fabricating Semiconductor Devices Having Vertical Cells and Semiconductor Devices Fabricated Thereby |
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KR102650539B1 (en) * | 2016-09-23 | 2024-03-27 | 삼성전자주식회사 | Method for fabricating three-dimensional semiconductor device |
US20180197874A1 (en) * | 2017-01-11 | 2018-07-12 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
US10186452B2 (en) * | 2017-03-28 | 2019-01-22 | Macronix International Co., Ltd. | Asymmetric stair structure and method for fabricating the same |
-
2017
- 2017-08-01 KR KR1020170097636A patent/KR102428273B1/en active IP Right Grant
-
2018
- 2018-03-22 US US15/928,559 patent/US10453857B2/en active Active
- 2018-06-25 SG SG10201805426YA patent/SG10201805426YA/en unknown
- 2018-08-01 CN CN201810865994.1A patent/CN109326607B/en active Active
-
2019
- 2019-10-18 US US16/657,520 patent/US10978477B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10978477B2 (en) | 2021-04-13 |
US10453857B2 (en) | 2019-10-22 |
CN109326607A (en) | 2019-02-12 |
US20190043880A1 (en) | 2019-02-07 |
KR102428273B1 (en) | 2022-08-02 |
CN109326607B (en) | 2024-05-28 |
US20200051998A1 (en) | 2020-02-13 |
KR20190013266A (en) | 2019-02-11 |
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