SG10201807790YA - Semiconductor devices - Google Patents
Semiconductor devicesInfo
- Publication number
- SG10201807790YA SG10201807790YA SG10201807790YA SG10201807790YA SG10201807790YA SG 10201807790Y A SG10201807790Y A SG 10201807790YA SG 10201807790Y A SG10201807790Y A SG 10201807790YA SG 10201807790Y A SG10201807790Y A SG 10201807790YA SG 10201807790Y A SG10201807790Y A SG 10201807790YA
- Authority
- SG
- Singapore
- Prior art keywords
- threshold voltage
- channels
- pattern
- voltage control
- control pattern
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
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- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Abstract
A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction 5 metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second 10 workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern. FIG. 3A 15
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US11699736B2 (en) * | 2020-06-25 | 2023-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure and method |
US11563083B2 (en) * | 2020-08-14 | 2023-01-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual side contact structures in semiconductor devices |
US11658216B2 (en) * | 2021-01-14 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for metal gate boundary isolation |
KR20230138555A (en) * | 2021-03-23 | 2023-10-05 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3D NAND memory and its manufacturing method |
US20220310655A1 (en) * | 2021-03-29 | 2022-09-29 | Sandisk Technologies Llc | Memory device including a ferroelectric semiconductor channel and methods of forming the same |
US20220406909A1 (en) * | 2021-06-17 | 2022-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor with dual silicide and method |
US11849578B2 (en) * | 2021-07-29 | 2023-12-19 | Sandisk Technologies Llc | Three-dimensional memory device with a columnar memory opening arrangement and method of making thereof |
KR20230046013A (en) * | 2021-09-29 | 2023-04-05 | 삼성전자주식회사 | Semiconductor devices and manufacturing methods for the same |
-
2017
- 2017-09-18 KR KR1020170119813A patent/KR102316293B1/en active IP Right Grant
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2018
- 2018-07-20 US US16/040,807 patent/US10381490B2/en active Active
- 2018-09-10 SG SG10201807790YA patent/SG10201807790YA/en unknown
- 2018-09-18 CN CN201811085088.6A patent/CN109524468B/en active Active
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2019
- 2019-08-06 US US16/532,645 patent/US10923602B2/en active Active
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2020
- 2020-12-28 US US17/134,611 patent/US11411124B2/en active Active
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2022
- 2022-07-12 US US17/863,127 patent/US11784260B2/en active Active
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US11411124B2 (en) | 2022-08-09 |
KR102316293B1 (en) | 2021-10-22 |
CN109524468B (en) | 2023-12-15 |
US20190088798A1 (en) | 2019-03-21 |
KR20190031855A (en) | 2019-03-27 |
US10923602B2 (en) | 2021-02-16 |
US11784260B2 (en) | 2023-10-10 |
US20200035842A1 (en) | 2020-01-30 |
CN109524468A (en) | 2019-03-26 |
US10381490B2 (en) | 2019-08-13 |
US20220352389A1 (en) | 2022-11-03 |
US20210151610A1 (en) | 2021-05-20 |
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