CN112185892B - Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment - Google Patents

Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment Download PDF

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CN112185892B
CN112185892B CN202010943337.1A CN202010943337A CN112185892B CN 112185892 B CN112185892 B CN 112185892B CN 202010943337 A CN202010943337 A CN 202010943337A CN 112185892 B CN112185892 B CN 112185892B
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layer
semiconductor structure
dipole
semiconductor
mos
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CN112185892A (en
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李永亮
程晓红
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment, relates to the technical field of semiconductors, and aims to solve the technical problem that a mask is filled between nano sheets or wires of the device to influence the electrical performance of the device, such as threshold voltage and the like. The manufacturing method of the semiconductor device comprises the following steps: providing a plurality of semiconductor structures; each semiconductor structure at least comprises a plurality of nano-sheets or wires which are arranged at intervals, and gate dielectric layers which are formed on the peripheries of the nano-sheets or the wires; forming dipole layers with corresponding thicknesses on the peripheries of the gate dielectric layers of the semiconductor structures by adopting multiple deposition and removal processes, so that each semiconductor structure has a corresponding threshold value regulating structure, and thus, obtaining a plurality of threshold value regulating structures with different threshold value regulating parameters; the multiple deposition and removal processes include forming a sacrificial layer in each semiconductor structure using a multiple deposition process and removing the sacrificial layer using a multiple removal process.

Description

Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic device.
Background
In the manufacturing process of the multi-threshold stacked nanosheet or wire device, in order to meet the requirement of multiple thresholds, not only metal gate materials of different materials but also metal gate materials of various thicknesses are adopted. Currently, a scheme of selectively removing metal gate materials in different regions is generally adopted, so as to meet the requirement of multiple thresholds. And even multiple deposition-removal-re-deposition processes may be required to meet the requirements of using different thicknesses or different materials of metal gate materials without using semiconductor devices. The selective removal technique typically employs a mask to remove the metal gate material in different areas. However, for the stacked nanosheet or line device structure, after the sacrificial layer is removed, a gap with a certain thickness exists between the stacked nanosheets or lines, and the mask can be filled between the nanosheets or lines of the device to be opened. Therefore, selective removal of the metal gate material between the nanosheets or the wires cannot be achieved, and the electrical properties of the device, such as the threshold voltage, are affected.
Disclosure of Invention
The invention aims to provide a semiconductor device, a manufacturing method thereof, an integrated circuit and electronic equipment, and aims to solve the technical problem that a mask is filled between nanosheets or lines of the device to influence the electrical performance of the device, such as threshold voltage and the like.
In a first aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of:
providing a plurality of semiconductor structures; each semiconductor structure at least comprises a plurality of nano sheets or lines arranged at intervals and a gate dielectric layer formed on the periphery of each nano sheet or line;
forming a dipole layer with corresponding thickness on the periphery of the gate dielectric layer of each semiconductor structure by adopting multiple deposition and removal processes, so that each semiconductor structure has corresponding threshold value regulation parameters, and thus obtaining a plurality of threshold value regulation structures with different threshold value regulation parameters;
wherein the multiple deposition and removal processes include forming a sacrificial layer in each semiconductor structure using a multiple deposition process and removing the sacrificial layer using a multiple removal process.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention adopts multiple deposition and removal processes to form the dipole layer with the corresponding thickness on the periphery of the gate dielectric layer of each semiconductor structure, so that each semiconductor structure has corresponding threshold value regulating and controlling parameters, a plurality of threshold value regulating and controlling structures with different threshold value regulating and controlling parameters are obtained, and finally the semiconductor device has a plurality of threshold value regulating and controlling structures with different threshold value regulating and controlling parameters. According to the invention, the threshold value regulating and controlling structures with different threshold value regulating and controlling parameters are obtained based on the dipole layers with corresponding thicknesses of different semiconductor structures, and when the dipole layers with corresponding thicknesses in different semiconductor structures are obtained, a sacrificial layer is deposited to solve the filling problem of the mask in the prior art between the nano sheets or lines of the opened device. The sacrificial layer can be completely removed by adopting selective corrosion, so that a high-performance semiconductor device with multiple threshold control parameters is obtained.
In a second aspect, the invention also provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device.
In a third aspect, the invention also provides an integrated circuit comprising the above semiconductor device.
In a fourth aspect, the present invention also provides an electronic device including the above semiconductor device, or including the above integrated circuit.
The advantageous effects of the second, third and fourth aspects and their various implementations in the present invention are the same as the advantageous effects of the first aspect or any possible implementation of the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a plurality of semiconductor structures according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a plurality of semiconductor structures having dipole layers according to an embodiment of the present invention;
fig. 3 to 17B are schematic structural diagrams of stages in a method for fabricating a semiconductor device according to an embodiment of the present invention, in which dipole layers with corresponding thicknesses are formed in a plurality of P-MOS semiconductor structures;
fig. 18 to fig. 36 are schematic structural diagrams illustrating stages of forming dipole layers of corresponding thicknesses in a plurality of N-MOS semiconductor structures in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 37 and 38 are schematic diagrams illustrating a process of removing the sacrificial layer and the dipole layer in the first N-MOS semiconductor structure and the third N-MOS semiconductor structure of fig. 32.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions according to the actual needs.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the manufacturing process of the multi-threshold stacked nanosheet or wire device, in order to meet the requirement of multiple thresholds, metal gate materials of different materials and metal gate materials with various thicknesses can be adopted. Currently, a scheme of selectively removing metal gate materials in different regions is generally adopted, so as to meet the requirement of multiple thresholds. Even multiple deposition-removal-re-deposition processes may be required to meet the requirement of using different thicknesses or different materials of metal gate materials without using semiconductor devices. The selective removal technique generally uses a mask to remove the gate dielectric layer material or the metal gate material in different regions. However, for the stacked nanosheet or line device structure, after the sacrificial layer is removed, a gap with a certain thickness exists between the stacked nanosheets or lines, and the mask can be filled between the nanosheets or lines of the device to be opened. Therefore, the selective removal of the metal gate material between the nanosheets or the wires cannot be realized, and the performance of the device is affected.
In order to solve the above technical problems, embodiments of the present invention provide a semiconductor device, a method of manufacturing the same, an integrated circuit, and an electronic apparatus. The manufacturing method of the semiconductor device comprises the following steps:
referring to fig. 1, a plurality of semiconductor structures is provided. Each semiconductor structure comprises a substrate 40, a plurality of nano-sheets or wires 10 formed on the substrate 40 at intervals, and a gate dielectric layer 20 formed on the periphery of the nano-sheets or wires 10.
The plurality of semiconductor structures comprise semiconductor structures which are used for forming N-MOS device regions later and/or semiconductor structures which are used for forming P-MOS device regions later. And a plurality of semiconductor structures which are included in the plurality of semiconductor structures and form the N-MOS device region, and/or a plurality of semiconductor structures which are included in the plurality of semiconductor structures and form the P-MOS device region.
Referring to fig. 2, in order to enable N-MOS device regions and/or P-MOS device regions formed by a plurality of semiconductor structures to have different threshold value adjusting structures, in the embodiment of the present invention, a dipole layer 30 with a corresponding thickness is formed on the periphery of the gate dielectric layer 20 of each semiconductor structure by using multiple deposition and removal processes, so that each semiconductor structure subsequently has a corresponding threshold value adjusting structure, thereby obtaining a plurality of threshold value adjusting structures with different threshold value adjusting parameters. Compared with the prior art, the method for manufacturing the semiconductor device provided by the embodiment of the invention adopts multiple deposition and removal processes to form the dipole layer with the corresponding thickness on the periphery of the gate dielectric layer of each semiconductor structure, so that each semiconductor structure has the corresponding threshold value regulating structure, a plurality of threshold value regulating structures with different threshold value regulating parameters are obtained, and finally the semiconductor device has a plurality of threshold value regulating structures with different threshold value regulating parameters.
Referring to fig. 2, it will be appreciated that the dipole layers 30 at the periphery of the multiple nanosheets/wires 10 in the same semiconductor structure are of the same thickness. The dipole layers 30 in different semiconductor structures may be the same or different in thickness, but at least two thicknesses of dipole layers in the plurality of semiconductor structures are ensured. Specifically, the corresponding thickness of the dipole layer in the semiconductor structure may be set according to an actual threshold adjustment parameter, which is not specifically limited herein.
The forming of the dipole layer with the corresponding thickness on the periphery of the gate dielectric layer by adopting the multiple deposition and removal processes comprises the following steps:
a dipole layer of a reference thickness is formed at a periphery of a gate dielectric layer of one or more semiconductor structures using a deposition process, and a sacrificial layer is formed in each semiconductor structure using a deposition process. The sacrificial layer at least fills gaps between adjacent gate dielectric layers and gaps between the gate dielectric layers and the substrate, wherein the gaps are included in each semiconductor structure. When other materials are deposited subsequently, the other materials cannot enter between the adjacent gate dielectric layers and between the gate dielectric layers and the substrate, so that after the sacrificial layer is removed, gaps between the adjacent gate dielectric layers and between the gate dielectric layers and the substrate can be completely released, and finally the formed semiconductor device meets the performance requirement.
The reference thickness may be a thickness of a dipole layer corresponding to one of the plurality of semiconductor structures, or may be a thickness determined according to thicknesses of dipole layers corresponding to two semiconductor structures. For example: when the number of the semiconductor structures in the plurality of semiconductor structures is 3 and the thicknesses of the respective dipole layers in the 3 semiconductor structures are 0nm,0.5nm and 1nm, respectively, the reference thickness may be 0.5nm or 1nm.
Another example is: when the number of the semiconductor structures in the plurality of semiconductor structures is 4 and the thicknesses of the respective dipole layers in the 4 semiconductor structures are 0nm,0.5nm,0.7nm and 1nm, respectively, the reference thickness may be 0.2nm or 0.3nm.
Then, removing at least the sacrificial layer in the target semiconductor structure; the target semiconductor structure is at least one semiconductor structure in which the thickness of the dipole layer does not satisfy the respective thickness. Specifically, the target semiconductor structure may be a semiconductor structure having a dipole layer thickness smaller than a corresponding thickness, or may be a semiconductor structure having a dipole layer thickness larger than a corresponding thickness.
The reference thickness dipole layer in the target semiconductor structure is then removed. And depositing the dipole layer with other thickness in the next deposition process, so that the dipole layer with the thickness at least meets the requirement of the corresponding thickness in one or more semiconductor structures.
After removing the dipole layer with the reference thickness in the target semiconductor structure, for the plurality of semiconductor structures except the target semiconductor structure, when the thickness of the dipole layer in the remaining semiconductor structure is smaller than the corresponding thickness, the sacrificial layer in the remaining semiconductor structure can be removed, so that the sum of the thicknesses of the dipole layer with the thickness and the dipole layer with the reference thickness can at least meet the requirement of the corresponding thickness in the remaining one or more semiconductor structures after the dipole layer with other thickness is deposited next time.
Then, the above steps are repeated until the thickness of the dipole layer in each semiconductor structure meets the requirement, that is, the thickness of the dipole layer in each semiconductor structure is the corresponding thickness.
It should be noted that, in the embodiment of the present invention, when the thickness of the dipole layer in one or more of the plurality of semiconductor structures satisfies the corresponding thickness requirement, at least the sacrificial layer deposited in the one or more semiconductor structures is not removed, and then, if the dipole layer and the sacrificial layer with other thicknesses are deposited for multiple times, the sacrificial layer of the one or more semiconductor structures is sequentially deposited on the sacrificial layer of the one or more semiconductor structures, and the sacrificial layer deposited in the one or more semiconductor structures is not removed by using the corresponding etching solution until the thickness of the dipole layer in each of the plurality of semiconductor structures satisfies the corresponding thickness requirement.
As a specific example, the plurality of semiconductor structures includes 3 semiconductor structures for subsequently forming N-MOS device regions and 2 semiconductor structures for subsequently forming P-MOS device regions.
When the dipole layers are formed in the plurality of semiconductor devices, the dipole layers with the corresponding thicknesses can be formed in the semiconductor structures of 2P-MOS device regions firstly, and then the dipole layers with the corresponding thicknesses can be formed in the semiconductor structures of 3N-MOS device regions.
Illustratively, the semiconductor structure of the P-MOS device region comprises a first P-MOS semiconductor structure and a second P-MOS semiconductor structure, wherein the thickness of the dipole layer in the first P-MOS semiconductor structure is 0.5nm, and the thickness of the dipole layer in the second P-MOS semiconductor structure is 1nm.
The semiconductor structure of the N-MOS device region comprises a first N-MOS semiconductor structure, a second N-MOS semiconductor structure and a third N-MOS semiconductor structure, wherein the thickness of a dipole layer in the first N-MOS semiconductor structure is 0.5nm, the thickness of a dipole layer in the second N-MOS semiconductor structure is 1nm, and the thickness of a dipole layer in the third N-MOS semiconductor structure is 0nm.
Forming the dipole layers of corresponding thicknesses in the first P-MOS semiconductor structure and the second P-MOS semiconductor structure may include the following several ways:
first, referring to fig. 3, a dipole layer 301 with a thickness of 0.5nm is formed on the periphery of the gate dielectric layer 20 in each semiconductor structure by using an atomic layer deposition process. Illustratively, the dipole layer 301 is a layer of aluminum oxide material. Then, an atomic layer deposition process or a chemical vapor deposition process is used to form a sacrificial layer 501 on the periphery of the dipole layer 301 in each semiconductor structure, so that the sacrificial layer 501 at least fills the gaps between adjacent gate dielectric layers 20 and between the gate dielectric layers 20 and the substrate 40 included in each semiconductor structure.
Referring to fig. 4, a first mask pattern is formed on the sacrificial layer 501 using a photolithography process, and the sacrificial layer 501 and the dipole layer 301 of the first P-MOS device region and the three N-MOS device regions are removed under the mask of the first mask pattern. Then, the mask material forming the first mask pattern and the sacrificial layer 501 of the second P-MOS device region are removed, and the dipole layer 301 with the thickness of 0.5nm of the second P-MOS device region is remained.
Referring to fig. 5, a 0.5nm thick dipole layer 302 is formed at the outer periphery of each of the N-MOS device region, the gate dielectric layer 20 of the first P-MOS device region, and the dipole layer 301 of the second P-MOS device region using an atomic layer deposition process. Illustratively, dipole layer 302 is a layer of aluminum oxide material.
Referring to fig. 6, a sacrificial layer 502 is formed on the outer periphery of the dipole layer 302 of each semiconductor structure, so that the sacrificial layer 502 at least fills the gaps between adjacent gate dielectric layers 20 and between the gate dielectric layer 20 and the substrate 40 included in each semiconductor structure.
A second mask pattern is formed on sacrificial layer 502 by a photolithography process, and sacrificial layer 502 and dipole layer 302 of the three N-MOS device regions are removed under the mask of the second mask pattern.
Thereafter, referring to fig. 7A, the remaining mask material forming the second mask pattern, the sacrificial layer 502 of the first P-MOS device region and the second P-MOS device region may be selectively removed to obtain a first P-MOS semiconductor structure and a second P-MOS semiconductor structure with dipole layers satisfying the thickness requirement.
Referring to fig. 7B, since dipole layers with corresponding thicknesses are required to be formed on the three N-MOS devices subsequently, in order to avoid the influence of the dipole layers in the N-MOS devices on the P-MOS devices, at least the sacrificial layers 502 in the first P-MOS device region and the second P-MOS device region may not be removed, so as to obtain the first P-MOS semiconductor structure and the second P-MOS semiconductor structure with dipole layers meeting the thickness requirement.
In the first method, when the dipole layer with a corresponding thickness is formed in the semiconductor structure of 2P-MOS device regions, the gate dielectric layer in the semiconductor structure of 3N-MOS device regions needs to be etched twice, and it should be understood that the performance of the finally formed semiconductor device is affected by the excessive etching times of the gate dielectric layer.
In order to reduce the number of times of etching the gate dielectric layer in the semiconductor structure of 3N-MOS device regions, the embodiment of the invention provides a second way of forming the dipole layers with corresponding thicknesses in the first P-MOS semiconductor structure and the second P-MOS semiconductor structure.
The process of the second mode is as follows: referring to fig. 8, a dipole layer 303 with a thickness of 0.5nm is formed on the outer circumference of the gate dielectric layer 20 in each semiconductor structure using an atomic layer deposition process. Illustratively, the dipole layer is a layer of aluminum oxide material. And forming a sacrificial layer 503 on the periphery of the dipole layer 303 in each semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 503 at least fills gaps between adjacent gate dielectric layers 20 and gaps between the gate dielectric layers 20 and the substrate 40 included in each semiconductor structure.
Referring to fig. 9, a third mask pattern is formed on the sacrificial layer 503 using a photolithography process, and the sacrificial layer 503 and the dipole layer 303 of the first P-MOS device region are removed under the mask of the third mask pattern. Then, the remaining mask material forming the third mask pattern, the sacrificial layer 503 of the second P-MOS device region and the sacrificial layer 503 of the three N-MOS device regions are removed, and the dipole layer 303 with a thickness of 0.5nm of the second P-MOS device region and the three N-MOS device regions is remained.
Referring to fig. 10, a dipole layer 304 with a thickness of 0.5nm is formed at the outer peripheries of the dipole layers 303 of the three N-MOS device regions, the gate dielectric layer 20 of the first P-MOS device region, and the dipole layer 303 of the second P-MOS device region by using an atomic layer deposition process.
Referring to fig. 11, a sacrificial layer 504 is formed on the outer periphery of the dipole layer 304 of each semiconductor structure, such that the sacrificial layer 504 at least fills the gaps between adjacent gate dielectric layers 20 included in each semiconductor structure and between the gate dielectric layers 20 and the substrate 40.
A fourth mask pattern is formed on the sacrificial layer 504 by using a photolithography process, the sacrificial layer 504, the dipole layer 304 and the dipole layer 303 in the three N-MOS device regions are removed under the mask of the fourth mask pattern, and then the mask material forming the fourth mask pattern is removed.
Thereafter, referring to fig. 12A, the sacrificial layer 504 of the first P-MOS device region and the second P-MOS device region may be removed to obtain a first P-MOS semiconductor structure and a second P-MOS semiconductor structure with dipole layers satisfying thickness requirements.
Referring to fig. 12B, since dipole layers with corresponding thicknesses are required to be formed on the three N-MOS devices subsequently, in order to avoid the influence of the dipole layers in the N-MOS devices on the P-MOS devices, at least the sacrificial layers 504 in the first P-MOS device region and the second P-MOS device region may be optionally not removed, so as to obtain the first P-MOS semiconductor structure and the second P-MOS semiconductor structure with dipole layers meeting the thickness requirement.
It can be understood that the manner of forming the dipole layers with the corresponding thicknesses in the first P-MOS semiconductor structure and the second P-MOS semiconductor structure may be various, and the dipole layers with the corresponding thicknesses may be formed in the first P-MOS semiconductor structure first, and then the thickness of the dipole layers in the second P-MOS semiconductor structure is adjusted to form the dipole layers with the corresponding thicknesses in the second P-MOS semiconductor structure. Or a dipole layer with a corresponding thickness is formed in the second P-MOS semiconductor structure, and then the dipole layer in the first P-MOS semiconductor structure is adjusted in thickness, so as to form a dipole layer with a corresponding thickness in the first P-MOS semiconductor structure.
The two manners are both a manner of forming the dipole layer with a corresponding thickness in the first P-MOS semiconductor structure and then forming the dipole layer with a corresponding thickness in the second P-MOS semiconductor structure, and the following illustrates a manner of forming the dipole layer with a corresponding thickness in the second P-MOS semiconductor structure and then forming the dipole layer with a corresponding thickness in the first P-MOS semiconductor structure.
In a third way, referring to fig. 13, a dipole layer 305 with a thickness of 1nm is formed on the periphery of the gate dielectric layer 20 in each semiconductor structure by using an atomic layer deposition process. Illustratively, dipole layer 305 is a layer of aluminum oxide material. Then, a sacrificial layer 505 is formed on the periphery of the dipole layer 305 in each semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 505 at least fills the gaps between adjacent gate dielectric layers 20 and between the gate dielectric layers 20 and the substrate 40 included in each semiconductor structure.
Referring to fig. 14, a fifth mask pattern formed by a photolithography process is formed on the sacrificial layer 505, and under the mask of the fifth mask pattern, the sacrificial layer 505 and the dipole layer 305 of the first P-MOS device region and the three N-MOS device regions are removed, and the sacrificial layer 505 of the second P-MOS device region and the dipole layer 305 of the second P-MOS device region having a thickness of 1nm remain. And finally, removing the residual mask material for forming the fifth mask pattern.
Referring to fig. 15, a 0.5nm thick dipole layer 306 is formed on each of the N-MOS device region, the outer periphery of the gate dielectric layer 20 of the first P-MOS device region, and the sacrificial layer 505 of the second P-MOS device region using an atomic layer deposition process.
Referring to fig. 16, a sacrificial layer 506 is formed on the outer periphery of the dipole layer 306 of each semiconductor structure, so that the sacrificial layer 506 fills at least the gaps between adjacent gate dielectric layers 20 included in each semiconductor structure and between the gate dielectric layer 20 and the substrate 40.
A sixth mask pattern formed using a photolithography process is formed on the sacrificial layer 506, and under the mask of the fourth mask pattern, the sacrificial layer 506 and the dipole layer 306 of the three N-MOS device regions are removed, and the dipole layer 306 and the sacrificial layer 506 formed on the sacrificial layer 505 of the second P-MOS device region are removed. And removing the residual mask material for forming the sixth mask pattern.
Thereafter, referring to fig. 17A, the sacrificial layer 506 of the first P-MOS device region and the sacrificial layer 505 of the second P-MOS device region are removed to obtain a first P-MOS semiconductor structure and a second P-MOS semiconductor structure with dipole layers meeting the thickness requirement.
Referring to fig. 17B, since dipole layers with corresponding thicknesses are required to be formed on the three N-MOS devices subsequently, in order to avoid the influence of the dipole layers in the N-MOS devices on the P-MOS devices, at least the first P-MOS device region sacrificial layer 506 and the second P-MOS device region sacrificial layer 505 may not be removed, so as to obtain the first P-MOS semiconductor structure and the second P-MOS semiconductor structure with dipole layers meeting the thickness requirement.
Above, a dipole layer of corresponding thickness has been formed in the semiconductor structure of 2P-MOS device regions, and how to form a dipole layer of corresponding thickness in the semiconductor structure of 3N-MOS device regions is explained below.
Several ways of forming a dipole layer of corresponding thickness in 3N-MOS semiconductor structures are exemplified below.
The first way is that the dipole layer of the corresponding thickness in the P-MOS semiconductor structure is exposed, i.e., the structure shown in fig. 7A, 12A and 17A. The following example is based on the structure shown in fig. 17A, with dipole layers of corresponding thickness formed in three N-MOS semiconductor structures. It is to be understood that the aspects of the embodiments of the present invention are not limited in this manner.
Referring to fig. 18, a 0.5nm thick dipole layer 601 is formed at the periphery of a gate dielectric layer 20 in an N-MOS semiconductor structure and at the periphery of a dipole layer in a P-MOS semiconductor structure by using an atomic layer deposition process. Illustratively, dipole layer 601 is a layer of lanthanum oxide material.
Referring to fig. 19, a sacrificial layer 701 is formed on the periphery of the dipole layer 601 in each of the N-MOS semiconductor structure and the P-MOS semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 701 at least fills gaps between adjacent gate dielectric layers 20 included in the N-MOS semiconductor structure and between the gate dielectric layers 20 and the substrate 40.
Third, referring to fig. 20, a seventh mask pattern is formed on the sacrificial layer 701, and the sacrificial layer 701 and the dipole layer 601 deposited in the first N-MOS semiconductor structure, in the third N-MOS semiconductor structure, and on the two P-MOS semiconductor structures are removed based on the seventh mask pattern. The remaining mask material forming the seventh mask pattern and the remaining sacrificial layer 701 are then removed to leave the dipole layer 601 formed in the second N-MOS semiconductor structure. Fourthly, referring to fig. 21, a dipole layer 602 with a thickness of 0.5nm is formed on the peripheries of the gate dielectric layer 20 in the first N-MOS semiconductor structure, the gate dielectric layer 20 in the third N-MOS semiconductor structure, the dipole layer 601 in the second N-MOS semiconductor structure, and the dipole layers in the two P-MOS semiconductor structures by using an atomic layer deposition process.
Fifthly, referring to fig. 22, a sacrificial layer 702 is formed on the dipole layer 602 of each N-MOS semiconductor structure and the dipole layer of each P-MOS semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 702 at least fills the gaps between the adjacent gate dielectric layers 20 included in the N-MOS semiconductor structure and between the gate dielectric layers 20 and the substrate 40.
Sixth, referring to fig. 23, an eighth mask pattern is formed on sacrificial layer 702, and sacrificial layer 702 and dipole layer 602 deposited in and on the third N-MOS semiconductor structure are removed based on the eighth mask pattern. The remaining masking material forming the eighth mask pattern and sacrificial layer 702 are then removed to leave the dipole layer 602 formed in the first and second N-MOS semiconductor structures. To form dipole layers of corresponding thickness in the three N-MOS semiconductor structures.
The difference from the first is that the second way is that the dipole layer of corresponding thickness in the P-MOS semiconductor structure is covered with a sacrificial layer, i.e., the structure shown in fig. 7B, 12B and 17B. The following example is based on the structure shown in fig. 7B, with dipole layers of corresponding thickness formed in three N-MOS semiconductor structures. It is to be understood that the aspects of the embodiments of the present invention are not limited in this manner.
Referring to fig. 24, a dipole layer 603 with a thickness of 0.5nm is formed at the periphery of the gate dielectric layer 20 in the N-MOS semiconductor structure and at the periphery of the P-MOS semiconductor structure by using an atomic layer deposition process. Illustratively, dipole layer 603 is a layer of lanthanum oxide material.
Second, referring to fig. 25, an atomic layer deposition process or a chemical vapor deposition process is used to form a sacrificial layer 703 on the periphery of the dipole layer 603 of each N-MOS semiconductor structure and the periphery of the dipole layer 603 of each P-MOS semiconductor structure, so that the sacrificial layer 703 at least fills gaps between adjacent gate dielectric layers 20 included in the N-MOS semiconductor structure and gaps between the gate dielectric layers 20 and the substrate 40.
Third, referring to fig. 26, a ninth mask pattern is formed on the sacrificial layer 703, and the sacrificial layer 703 and the dipole layer 603 deposited in the first N-MOS semiconductor structure, in the third N-MOS semiconductor structure, and on the two P-MOS semiconductor structures are removed based on the ninth mask pattern. The remaining masking material forming the ninth mask pattern, sacrificial layer 703 in the second N-MOS semiconductor structure, and sacrificial layer 503 in the P-MOS semiconductor structure are then removed to leave dipole layer 603 formed in the second N-MOS semiconductor structure.
Fourth, referring to fig. 27, a sacrificial layer 704 is formed in the two P-MOS semiconductor structures to protect the respective dipole layers in the two P-MOS semiconductor structures.
Fifthly, referring to fig. 28, a dipole layer 604 with a thickness of 0.5nm is formed on the peripheries of the gate dielectric layer 20 in the first N-MOS semiconductor structure, the gate dielectric layer 20 in the third N-MOS semiconductor structure, the dipole layer 603 in the second N-MOS semiconductor structure, and the sacrificial layers 704 in the two P-MOS semiconductor structures by using an atomic layer deposition process.
Sixthly, referring to fig. 29, a sacrificial layer 705 is formed on the dipole layer 604 of each N-MOS semiconductor structure and the dipole layer 604 of each P-MOS semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 705 at least fills the gaps between the adjacent gate dielectric layers 20 included in the N-MOS semiconductor structure and between the gate dielectric layers 20 and the substrate 40.
Seventh, referring to fig. 30, a tenth mask pattern is formed on the sacrificial layer 705, and the sacrificial layer 705 and the dipole layer 604 deposited in the third N-MOS semiconductor structure and on the P-MOS semiconductor structure are removed based on the tenth mask pattern. The remaining masking material forming the tenth mask pattern, sacrificial layer 705 in the first N-MOS semiconductor structure, sacrificial layer 705 in the second N-MOS semiconductor structure, and sacrificial layers 705 on both P-MOS semiconductor structures are then removed to leave the dipole layer 604 formed in the first N-MOS semiconductor structure and the second N-MOS semiconductor structure. To form dipole layers of corresponding thickness in the three N-MOS semiconductor structures.
A third way is that the dipole layers of corresponding thickness in the P-MOS semiconductor structure are exposed, i.e. the structure shown in fig. 7A, fig. 12A and fig. 17A. The following example is based on the structure shown in fig. 12A, with dipole layers of corresponding thickness formed in three N-MOS semiconductor structures. It is to be understood that the aspects of the embodiments of the present invention are not limited in this manner.
In a first step, referring to fig. 31, a dipole layer 605 with a thickness of 0.5nm is formed on the periphery of the gate dielectric layer 20 in the N-MOS semiconductor structure and on the periphery of the dipole layer in the P-MOS semiconductor structure by using an atomic layer deposition process. Illustratively, dipole layer 605 is a layer of lanthanum oxide material.
Second, referring to fig. 32, a sacrificial layer 706 is formed on the outer periphery of the dipole layer 605 of each N-MOS semiconductor structure and the outer periphery of the dipole layer 605 of each P-MOS semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 706 at least fills the gaps between the adjacent gate dielectric layers 20 and between the gate dielectric layers 20 and the substrate 40 included in the N-MOS semiconductor structures.
Third, referring to fig. 33, an eleventh mask pattern is formed on the sacrificial layer 706, and the sacrificial layer 706 and the dipole layer 605 deposited in the first N-MOS semiconductor structure and the third N-MOS semiconductor structure are removed based on the eleventh mask pattern. The remaining mask material forming the eleventh mask pattern, the sacrificial layer 706 in the second N-MOS semiconductor structure, and the sacrificial layer 706 in the P-MOS semiconductor structure are then removed to leave the dipole layer 605 formed in the second N-MOS semiconductor structure and the dipole layer 605 formed in the P-MOS semiconductor structure.
Fourth, referring to fig. 34, a dipole layer 606 is formed at the outer circumference of the gate dielectric layer 20 of the third N-MOS semiconductor structure, the outer circumference of the dipole layer 605 of the second N-MOS semiconductor structure, and the outer circumference of the dipole layer 605 of the P-MOS semiconductor structure in the first N-MOS semiconductor structure. Illustratively, dipole layer 606 is a layer of lanthanum oxide material.
Fifthly, referring to fig. 35, a sacrificial layer 707 is formed on the periphery of the dipole layer 606 of each N-MOS semiconductor structure and the periphery of the dipole layer 606 of each P-MOS semiconductor structure by using an atomic layer deposition process or a chemical vapor deposition process, so that the sacrificial layer 707 at least fills the gaps between adjacent gate dielectric layers 20 and between the gate dielectric layers 20 and the substrate 40 included in the N-MOS semiconductor structure.
Sixthly, referring to fig. 36, a twelfth mask pattern is formed on sacrificial layer 707, and sacrificial layer 707 and dipole layer 606 deposited in the third N-MOS semiconductor structure are removed based on the twelfth mask pattern. And then removing the rest mask material forming the eleventh mask pattern, the sacrificial layer 707 in the first N-MOS semiconductor structure, the sacrificial layer 707 in the second N-MOS semiconductor structure and the sacrificial layer 707 in the P-MOS semiconductor structure to reserve the dipole layers 606 formed in the first N-MOS semiconductor structure and the second N-MOS semiconductor structure and the dipole layers 606 formed in the P-MOS semiconductor structure.
After forming the respective dipole layers in the plurality of semiconductor structures, each semiconductor structure of the plurality of semiconductor structures further comprises: and an interface layer formed between each nanosheet or wire and the corresponding gate dielectric layer. In the above process, a plurality of deposition and removal processes are adopted, and the forming of the dipole layer with a corresponding thickness on the periphery of the gate dielectric layer of each semiconductor structure further comprises: annealing the plurality of semiconductor structures to form a plurality of dipole pairs at the interface of the gate dielectric layer and the corresponding interface layer in each semiconductor structure; the plurality of dipole pairs are used for regulating and controlling threshold regulating and controlling parameters in the corresponding threshold regulating and controlling structure. The number of dipole pairs in each semiconductor structure may be the same or different from the number of dipole pairs in other semiconductor structures. However, the number of dipole pairs included in the plurality of semiconductor structures is at least two, so that the plurality of semiconductor structures have at least two threshold adjustment structures with two threshold adjustment parameters.
It can be seen that, in the third way of forming the dipole layer with a corresponding thickness in the N-MOS semiconductor structure, the dipole layer of the N-MOS semiconductor structure with the required material is formed on the corresponding dipole layer in the P-MOS semiconductor structure. In the P-MOS semiconductor structure, the corresponding dipole layer in the P-MOS semiconductor structure is closer to the interface layer than the dipole layer of the required material in the N-MOS semiconductor structure, so that when the plurality of semiconductor structures are annealed, the probability of forming a dipole pair at the interface between the corresponding dipole layer and the corresponding interface layer in the P-MOS semiconductor structure is much greater than the probability of forming a dipole pair at the interface between the dipole layer of the required material and the corresponding interface layer in the N-MOS semiconductor structure, and therefore, the third mode of forming the dipole layer of the corresponding thickness in the N-MOS semiconductor structure does not have a significant influence on the threshold value regulation parameter in the corresponding threshold value regulation structure.
Furthermore, for the third mode of forming the dipole layer with the corresponding thickness in the N-MOS semiconductor structure, the influence on the threshold value regulation parameter of the P-MOS semiconductor structure due to the dipole layer with the required material in the N-MOS semiconductor structure in the P-MOS semiconductor structure can be reduced by adjusting the thickness of the corresponding dipole layer in the P-MOS semiconductor structure. For example, the thickness of the corresponding dipole layer in the P-MOS semiconductor structure is increased. It can be understood that increasing the thickness of the corresponding dipole layer in the P-MOS semiconductor structure not only reduces the number of dipole pairs formed at the interface between the dipole layer requiring material and the corresponding interface layer in the N-MOS semiconductor structure, but also increases the number of dipole pairs formed at the interface between the corresponding dipole layer and the corresponding interface layer. Based on the above, in the P-MOS semiconductor structure, the thickness of the corresponding dipole layer can be determined by balancing the number of dipole pairs formed at the interface between the dipole layer of the N-MOS semiconductor structure requiring material and the corresponding interface layer and the number of dipole pairs formed at the interface between the corresponding dipole layer and the corresponding interface layer, so that the threshold value regulation parameter of the P-MOS semiconductor structure meets the requirement.
In the above, when removing the sacrificial layer and/or the dipole layer in the corresponding semiconductor structure, a mask material covering the semiconductor structure needs to be formed on the corresponding semiconductor structure. And then, forming a mask pattern on the mask material by utilizing a photoetching process, and removing the sacrificial layer and/or the dipole layer in the corresponding semiconductor structure by taking the mask pattern as a mask. The specific process of the sacrificial layer and/or the dipole layer in the corresponding semiconductor structure is described below with reference to the accompanying drawings:
fig. 37 and 38 show a schematic illustration of a process of removing the sacrificial layer 706 and the dipole layer 605 deposited in the first N-MOS semiconductor structure and in the third N-MOS semiconductor structure of fig. 32. Specifically, referring to fig. 37, a masking material 801 is formed on sacrificial layers 706 of a plurality of semiconductor structures to cover the sacrificial layers. Thereafter, a mask pattern is formed on the mask material 801 by a photolithography process. Referring to fig. 38, the sacrificial layer 706 and the dipole layer 605 in the first N-MOS semiconductor structure, the third N-MOS semiconductor structure are removed under the mask action of the mask pattern. Finally, the remaining mask material 801 and the sacrificial layer 706 are removed, resulting in the structure of fig. 33.
Illustratively, the sacrificial layer is an amorphous silicon sacrificial layer; removing the sacrificial layer in the target semiconductor structure at this time includes: forming a mask pattern covering the amorphous silicon sacrificial layer; and removing the sacrificial layer in the target semiconductor structure by using the ammonium hydroxide solution by taking the mask pattern as a mask.
In order to make the mask pattern have better masking effect, the forming of the mask pattern on the amorphous silicon sacrificial layer of the plurality of semiconductor structures may be: firstly, forming an amorphous carbon layer covering an amorphous silicon sacrificial layer in a semiconductor structure; then, forming a photoetching pattern on the amorphous carbon layer; then, taking the photoetching pattern as a mask, and transferring the photoetching pattern to the amorphous carbon layer by adopting a dry etching process to form a mask pattern; finally, removing the photoetching pattern.
It should be understood that after the sacrificial layer of the sacrificial layer in the target semiconductor structure is removed by using the above mask pattern, the remaining mask material is also removed, wherein the mask material may be the amorphous carbon layer as described above. At this time, the remaining amorphous carbon layer may be removed using a plasma gas containing oxygen.
It will be appreciated that in order to obtain a complete semiconductor structure, a metal gate needs to be formed in the semiconductor structure after the annealing process. Specifically, a metal gate may be formed at the outer periphery of the dipole layer of each semiconductor structure.
In practice, in order not to affect the thickness of the metal gate, the metal gate may be formed on the outer periphery of the gate dielectric layer of each semiconductor structure after the dipole layer is annealed and the corresponding dipole layer is removed. The material of the metal gates in all N-MOS semiconductor structures is the same, and the material of the metal gates in all P-MOS semiconductor structures is the same, where the material of the metal gates in the N-MOS semiconductor structures and the material of the metal gates in the P-MOS semiconductor structures may be materials in the prior art, which is not limited in the embodiment of the present invention.
For example, in order to form a required gate stack structure, the gate dielectric layer may be a hafnium oxide material layer, and it is understood that the gate dielectric layer may also be a gate dielectric layer of another material.
Illustratively, in order to realize different functions of the N-MOS semiconductor structure and the P-MOS semiconductor structure, the dipole layer in the N-MOS semiconductor structure is made of different materials from the dipole layer in the P-MOS semiconductor structure. For example: the dipole layer in the N-MOS semiconductor structure is a lanthanum oxide material layer, and the dipole layer in the P-MOS semiconductor structure is an aluminum oxide material layer.
Illustratively, the annealed dipole layer may not be removed in order to reduce process steps due to the smaller distance between two adjacent nanosheets or wires. At this time, the metal grid is formed on the outer periphery of the dipole layer, and in order not to affect the thickness requirement of the metal grid, the thickness of the dipole layer of the embodiment of the present invention needs to be set to be greater than or equal to 0nm and less than or equal to 1nm.
The embodiment of the invention also provides a semiconductor device, and the semiconductor device is manufactured by the manufacturing method of the semiconductor device.
The beneficial effects of the semiconductor device provided by the embodiment of the present invention are the same as the beneficial effects of the manufacturing method of the semiconductor device provided by the above embodiment, and are not described herein again.
The embodiment of the invention also provides an integrated circuit which comprises the semiconductor device provided by the technical scheme.
The advantageous effects of the integrated circuit provided by the embodiment of the present invention are the same as those of the semiconductor device provided by the above embodiment, and are not described herein again.
The embodiment of the invention also provides electronic equipment which comprises the semiconductor device provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, the terminal device comprises a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligence device, a mobile power supply and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the invention are the same as those of the method for manufacturing the semiconductor device provided by the embodiment, and are not described herein again.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (15)

1. A method for manufacturing a semiconductor device, comprising:
providing a plurality of semiconductor structures; each semiconductor structure at least comprises a plurality of nano sheets or wires which are arranged at intervals, and a gate dielectric layer formed on the periphery of each nano sheet or wire;
forming a dipole layer with a corresponding thickness on the periphery of the gate dielectric layer of each semiconductor structure by adopting multiple deposition and removal processes, so that each semiconductor structure has corresponding threshold value regulation parameters, and thus obtaining a plurality of threshold value regulation structures with different threshold value regulation parameters;
wherein the multiple deposition and removal processes include forming a sacrificial layer in each of the semiconductor structures using multiple deposition processes and removing the sacrificial layer using multiple removal processes;
each of the semiconductor structures further includes a substrate;
the forming of the dipole layer with the corresponding thickness on the periphery of the gate dielectric layer by adopting the multiple deposition and removal process comprises the following steps:
forming a dipole layer with reference thickness at least on the periphery of the gate dielectric layers of one or more semiconductor structures by adopting a deposition process, and forming a sacrificial layer on the periphery of the dipole layer with reference thickness by utilizing the deposition process, so that the sacrificial layer at least fills gaps between the adjacent gate dielectric layers and gaps between the gate dielectric layers and the substrate, which are included in each semiconductor structure;
removing the sacrificial layer in the target semiconductor structure; the target semiconductor structure is at least one semiconductor structure for which the thickness of the dipole layer does not satisfy the respective thickness;
removing the dipole layer of the reference thickness in the target semiconductor structure;
repeating the above steps until the thickness of the dipole layer in each semiconductor structure satisfies the corresponding thickness.
2. The method of fabricating a semiconductor device according to claim 1, wherein in a case where the dipole layers in the remaining semiconductor structures of the plurality of semiconductor structures are smaller in thickness than the respective thicknesses in addition to the target semiconductor structure, after removing the dipole layer of the reference thickness in the target semiconductor structure, the method of fabricating a semiconductor device further comprises:
and removing the remaining sacrificial layer.
3. A method of manufacturing a semiconductor device according to claim 1, wherein the dipole layer of the reference thickness is formed by an atomic layer deposition process; and/or
The sacrificial layer is formed using an atomic layer deposition process or using a chemical vapor deposition process.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial layer is an amorphous silicon sacrificial layer;
the removing the sacrificial layer in the target semiconductor structure comprises:
forming a mask pattern covering the amorphous silicon sacrificial layer;
and removing the sacrificial layer in the target semiconductor structure by using the mask pattern as a mask and using an ammonium hydroxide solution.
5. The method of claim 4, wherein forming the mask pattern overlying the sacrificial layer of amorphous silicon of the plurality of semiconductor structures comprises:
forming an amorphous carbon layer covering the amorphous silicon sacrificial layer in the semiconductor structure;
forming a photoetching pattern on the amorphous carbon layer;
taking the photoetching pattern as a mask, and transferring the photoetching pattern to the amorphous carbon layer to form the mask pattern;
and removing the photoetching pattern.
6. The method of claim 5, wherein after removing the reference thickness dipole layer in the target semiconductor structure, the method further comprises:
and removing the residual amorphous carbon layer by using plasma gas containing oxygen element.
7. The method of fabricating a semiconductor device according to any of claims 1-6, wherein each of said semiconductor structures further comprises, an interfacial layer formed between each of said nanosheets or wires and the corresponding gate dielectric layer;
the forming of the dipole layer with the corresponding thickness at the periphery of the gate dielectric layer of each semiconductor structure by adopting the multiple deposition and removal process further comprises:
annealing the plurality of semiconductor structures to form a plurality of dipole pairs at the interface of the gate dielectric layer and the corresponding interface layer in each semiconductor structure; the plurality of dipole pairs are used for regulating and controlling threshold regulating and controlling parameters in the corresponding threshold regulating and controlling structure.
8. The method of manufacturing a semiconductor device according to claim 7, wherein after the annealing the plurality of semiconductor structures, the method further comprises:
and forming a metal gate on the dipole layer after the annealing treatment.
9. The method of manufacturing a semiconductor device according to claim 7, wherein after the annealing the plurality of semiconductor structures, the method of manufacturing a semiconductor device further comprises:
removing the annealed dipole layer;
and forming a metal gate on the annealed gate dielectric layer.
10. Method for manufacturing a semiconductor device according to any of claims 1 to 6, characterized in that said semiconductor structure comprises an N-MOS semiconductor structure and/or a P-MOS semiconductor structure;
the dipole layer in the N-MOS semiconductor structure is a lanthanum oxide material layer;
the dipole layer in the P-MOS semiconductor structure is an aluminum oxide material layer.
11. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the gate dielectric layer is a hafnium oxide material layer.
12. A method for fabricating a semiconductor device according to any one of claims 1 to 6, wherein the thickness of the dipole layer of corresponding thickness is 0nm or more and 1nm or less.
13. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 12.
14. An integrated circuit comprising the semiconductor device according to claim 13.
15. An electronic device comprising the semiconductor device according to claim 13 or the integrated circuit according to claim 14.
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