CN114093880A - Processing method of semiconductor structure and three-dimensional memory - Google Patents
Processing method of semiconductor structure and three-dimensional memory Download PDFInfo
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- CN114093880A CN114093880A CN202111292815.8A CN202111292815A CN114093880A CN 114093880 A CN114093880 A CN 114093880A CN 202111292815 A CN202111292815 A CN 202111292815A CN 114093880 A CN114093880 A CN 114093880A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application provides a processing method of a semiconductor structure and a three-dimensional memory. The semiconductor structure comprises a laminated structure, a grid gap structure penetrating through the laminated structure and protruding out of the laminated structure, and a slit positioned between the grid gap structure and the laminated structure, wherein the processing method of the semiconductor structure comprises the following steps: forming a dielectric layer in the slit; and forming a semiconductor layer overlying the dielectric layer. The processing method of the semiconductor structure and the three-dimensional memory are beneficial to reducing the risk of short circuit and electric leakage of the semiconductor layer and the grid electrode conducting layer (word line) through the slit, and are also beneficial to saving production cost.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a method for processing a semiconductor structure and a three-dimensional memory.
Background
For some three-dimensional memory fabrication processes, the channel layer is exposed by removing the substrate and a functional layer of silicon oxide-silicon nitride-silicon oxide (ONO) that extends to the channel structure in the substrate. Further, the channel layer is electrically connected to the semiconductor layer by forming the semiconductor layer in contact with the exposed channel layer.
In some applications, a complex mask pattern is required to avoid adversely affecting, for example, the gate gap structure during the removal of the functional layer of the channel structure. However, this solution is disadvantageous in saving manufacturing costs and also increases process complexity.
On the other hand, the exposed channel layer may form a native oxide layer during a waiting time after the process of removing the functional layer of the channel structure. Similarly, the process of removing the native oxide layer may adversely affect, for example, the gate gap structure.
Therefore, how to deal with the above technical problems occurring during the process of manufacturing the three-dimensional memory is one of the directions in which those skilled in the art are working.
Disclosure of Invention
The application provides a method for processing a semiconductor structure, which comprises the following steps: the semiconductor device comprises a laminated structure, a gate gap structure penetrating through the laminated structure and protruding out of the laminated structure, and a slit positioned between the gate gap structure and the laminated structure, wherein the processing method of the semiconductor device comprises the following steps: forming a dielectric layer in the slit; and forming a semiconductor layer overlying the dielectric layer.
In some embodiments, the dielectric layer may be formed in the slit while covering the first side of the stacked structure, and the portion of the gate slit structure protruding from the stacked structure is located on the first side.
In some embodiments, the semiconductor structure may further include a channel structure penetrating the stacked structure and protruding from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure has an outer wall of the channel layer, the dielectric layer is formed in the slit while covering the channel layer, and the portion of the channel structure protruding from the stacked structure is located on the first side.
In some embodiments, after the step of forming the dielectric layer in the slit, the processing method may include: the portion of the dielectric layer outside the slit is removed.
In some embodiments, the thickness of the portion of the dielectric layer outside the slit is greater than or equal to 15 nm.
In some embodiments, before the step of forming the dielectric layer in the slit, the processing method may include: and removing the natural oxide layer on the channel layer and forming a slit.
In some embodiments, the material of the dielectric layer may include silicon oxide.
The present application provides a three-dimensional memory, comprising: a laminated structure; the grid gap structure penetrates through the laminated structure and protrudes out of the laminated structure; the slit structure is positioned between the gate slit structure and the laminated structure, and the material of the slit structure is dielectric material; and a semiconductor layer covering the slit structure.
In some embodiments, the dielectric material may include silicon oxide.
In some embodiments, the three-dimensional memory may further include: and the channel structure penetrates through the laminated structure and protrudes out of the laminated structure, wherein one part of the channel structure protruding out of the laminated structure is provided with the outer wall of the channel layer, and the semiconductor layer is in contact with the channel layer.
According to the processing method of the semiconductor structure and the three-dimensional memory provided by the embodiment of the application, the dielectric layer is formed in the slit, so that on one hand, the risk of short circuit and electric leakage between the semiconductor layer and the gate conductive layer (word line) through the semiconductor material in the slit after the semiconductor layer is formed is favorably reduced, and the yield of the processed semiconductor structure is favorably improved. On the other hand, the method can be compatible with the process for removing the natural oxide layer under the condition that the waiting time is exceeded, thereby being beneficial to improving the flexibility of the process treatment of the semiconductor structure and saving the production cost of scrapping the semiconductor structure due to the removal of the natural oxide layer.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to the related art;
FIG. 2 is a cross-sectional view illustrating a semiconductor structure with a native oxide layer formed thereon according to the related art;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present application;
FIG. 4 is a flow chart of a method of processing a semiconductor structure according to an embodiment of the present application; and
fig. 5A to 5C are schematic process cross-sectional views of a method of processing a semiconductor structure according to an application embodiment.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.
The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure 100' according to the related art. Illustratively, the semiconductor structure 100' may be an intermediate structure during a fabrication process of a three-dimensional memory, such as a 3D NAND memory. As shown in fig. 1, the semiconductor structure 100' may include a stack structure 110, a gate slit structure 120, and a channel structure 130.
In some embodiments, the stacked structure 110 may include a plurality of dielectric layers and a plurality of conductive layers, such as gate dielectric layers 111 and gate conductive layers 112, which are alternately stacked along the first direction D1. Alternatively, the material of the gate conductive layer 112 may include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof. Alternatively, the first surface 11 of the stacked structure 110 may have a polysilicon layer 113 formed thereon.
In some embodiments, the gate slit structure 120 may penetrate through the stacked structure 110 and protrude from the first surface 11 of the stacked structure 110 along the first direction D1 or a direction substantially parallel to the first direction D1. Alternatively, the gate slit structure 120 may include a conductive layer 121 and an insulating layer 122 located at an outer sidewall of the conductive layer 121. Alternatively, the high-k layer (not shown) may be located on at least a portion of outer sidewalls of the gate slit structure 120, such as outer sidewalls corresponding to the plurality of gate dielectric layers 111 in the stacked structure 110 and outer sidewalls of a portion protruding from the first surface 11 of the stacked structure 110. Alternatively, the material of the conductive layer 121 may include a conductive material such as tungsten, cobalt, copper, aluminum, doped polysilicon, or any combination thereof. Alternatively, the material of the insulating layer 122 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Alternatively, the material of the high dielectric constant layer may include a high dielectric constant material such as aluminum oxide, hafnium oxide, tantalum oxide, or any combination thereof.
In some embodiments, the channel structure 130 may penetrate the stacked structure 110 and protrude from the first surface 11 of the stacked structure 110 along the first direction D1 or a direction substantially parallel to the first direction D1. A portion of the channel structure 130 that penetrates the stacked-layer structure 110 may have an outer wall of the channel layer 131 and the functional layer 132 from the outside inward. A portion of the channel structure 130 protruding from the first surface 11 (e.g., a portion protruding from the polysilicon layer 113) may have an outer wall of the channel layer 131. Illustratively, the functional layer 132 may include an outside-in charge blocking layer 1321, a charge trapping layer 1322, and a tunneling layer 1323. Alternatively, the materials of the charge blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may include, for example, silicon oxide, silicon nitride, and silicon oxide, in that order. Alternatively, the material of the channel layer 132 may include, for example, doped polysilicon.
In some related art processing methods for the semiconductor structure 100 ', the gate slit structure 120 and the channel structure 130 in the semiconductor structure 100' may be obtained by a process method as described below. Illustratively, the semiconductor structure 100' may include a substrate (not shown) outside the first surface 11 of the stacked-layer structure 110, and the initial channel structure (not shown) may have outward-facing outer walls of the functional layer 132 and the channel layer 131. A portion of the functional layer 132 and the channel layer 131 may extend into the substrate. Alternatively, a portion of the functional layer 132 extending into the substrate may be removed using, for example, a dry or wet etching process, so that a portion of the channel layer 131 protruding from a portion of the stacked-layer structure 110 (e.g., a portion protruding from the polysilicon layer 113) is exposed, so as to form a semiconductor layer (not shown) in contact with the channel layer 131 during a subsequent process. However, during the process of removing the portion of the functional layer 132 extending into the substrate, the etching material (e.g., etching gas) may cause a slit (divot) to be generated on both sides of the gate slit structure 120, for example, between the high-k layer and the stacked structure 110. In other words, the slit may be located between the gate slit structure 120 and the stack structure 110.
In some practical processes, fig. 2 illustrates a native oxide layer 141 formed on the channel layer 131 after the semiconductor structure 100' has been removed from a portion of the functional layer 132. Fig. 3 illustrates the semiconductor structure 100 'after the native oxide layer 141 has been removed from the semiconductor structure 100'. As shown in fig. 2 and 3, between the process of removing the functional layer 132 and forming the semiconductor layer, the risk of forming the native oxide layer 141 of the channel layer 132 exposed after removing the substrate may be reduced by controlling a waiting time (Q-time, for example, less than 3.5 hours). Alternatively, in the case where the polysilicon layer 113 is formed on the first surface 11 of the stacked structure 110, the native oxide layer 141 may also be formed on the polysilicon layer 113, and the thickness of the native oxide layer 141 may be, for example, about 1nm to 2 nm. In the case where the native oxide layer 141 has been formed, the native oxide layer 141 overlying the channel layer 132 may be removed by, for example, a hydrofluoric acid solution. However, during the process of removing the native oxide layer 141, a slit 142 may be formed on two sides of the gate slit structure 120, for example, between the high-k layer and the stack structure 110.
As described above, on the premise that the slit has been formed during the process of removing a portion of the functional layer 131, the slit 142 may be enlarged due to the formation of the native oxide layer 141 due to the exceeding of the waiting time and during the process of removing the native oxide layer 141. For example, the slits 142 may extend into the gate conductive layer 112, so that the semiconductor material is filled in the slits 142 and contacts the gate conductive layer 112 during a subsequent semiconductor layer forming process, thereby causing the semiconductor layer to be shorted with the gate conductive layer 112 (i.e., word line) via the semiconductor material filled in the slits. Alternatively, the size of the slit 142 in a direction parallel to the first surface 11 of the stacked structure 110 and perpendicular to the gate slit structure 120 is about 20nm, and the size of the slit 142 in the first direction D1 is about 100 nm.
The processing method of the semiconductor structure 100 according to the embodiment of the present disclosure may at least partially solve the technical problem of short circuit and leakage between the semiconductor layer and the gate conductive layer (i.e., the word line) through the semiconductor material filled in the slit. Fig. 4 is a flow chart of a method 1000 of processing a semiconductor structure 100 according to an embodiment of the present application. As shown in fig. 4, a method 1000 of processing a semiconductor structure 100 may comprise: s110, forming a dielectric layer in the slit; and S120, forming a semiconductor layer covering the dielectric layer.
Fig. 5A to 5C are schematic process cross-sectional views of a method 1000 of processing a semiconductor structure 100 according to an embodiment of the present disclosure. The processing method 1000 according to the embodiment of the present application will be described in detail below with reference to fig. 5A to 5C.
In step S110, as shown in fig. 5A, in some embodiments, the dielectric layer 151 may be formed in the slit 142 (refer to fig. 3) using a thin film deposition process such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any combination thereof. Alternatively, during the process of forming the dielectric layer 151 in the slit 142, the dielectric layer 151 may be formed on a surface of a portion of the channel layer 131 protruding from the stacked-layer structure 100 (e.g., a portion protruding from the polysilicon layer 113). Alternatively, during the process of forming the dielectric layer 151 in the slit 142, the dielectric layer 151 may be formed on the first side of the stacked structure 110 (e.g., the surface of the polysilicon layer 113). Alternatively, the material of the dielectric layer 151 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Alternatively, as shown in fig. 5B, a portion of the dielectric layer 151 outside the slit 142, for example, a portion of the dielectric layer 151 on the surface of the channel layer 131 and/or a portion of the surface of the polysilicon layer 113, may be removed using, for example, a dry or wet etching process. Optionally, during the process of forming the dielectric layer 151, a thickness of a portion of the dielectric layer 151 located outside the slit 142, for example, a portion of the dielectric layer 151 located on the surface of the channel layer 131 and/or a portion of the surface of the polysilicon layer 113, may be made greater than or equal to 15nm, so as to facilitate control of a process (e.g., an etching process) for removing the portion of the dielectric layer 151 located outside the slit 142, thereby facilitating reduction of a risk of etching and generating the slit between the channel structure 130 and the stacked-layer structure 110 during the process for removing the portion of the dielectric layer 151 located outside the slit 142. Alternatively, in the case where the material of the dielectric layer 151 is silicon oxide, a hydrofluoric acid solution, for example, may be used to remove the portion of the dielectric layer 151 located outside the slit 142.
In some embodiments, the dielectric layer 151 may be filled in the slit 142 without being formed outside the slit 142 (e.g., a surface of a portion of the dielectric layer 151 located on the channel layer 131 and/or a surface of a portion of the polysilicon layer 113), for example, by controlling a thin film deposition process.
In step S120, as shown in fig. 5C, a semiconductor layer 152 covering the dielectric layer 151 in the slit 142 may be formed using a thin film deposition process such as PVD, CVD, ALD, or any combination thereof. Alternatively, during the process of forming the semiconductor layer 152 covering the dielectric layer 151 in the slit 142, the semiconductor layer 152 may be in contact with the channel layer 151, for example, the semiconductor layer 152 covers the surface of the polysilicon layer 113 and surrounds the gate slit structure 120 and the portion of the channel structure 130 protruding from the polysilicon layer 113. Alternatively, the material of the semiconductor layer 152 may include, for example, polysilicon.
In some embodiments, in the case that the material of the semiconductor layer 152 is polysilicon, the semiconductor layer 152 can be prepared by the method described below. An amorphous silicon layer (not shown) covering the dielectric layer 151 may be first formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, the amorphous silicon may be crystallized into the polycrystalline silicon using, for example, a laser annealing process to form the semiconductor layer 152.
According to the processing method of the semiconductor structure provided by the embodiment of the application, the dielectric layer is formed in the slit, so that on one hand, the risk of short circuit and electric leakage between the semiconductor layer and the gate conductive layer (word line) through the semiconductor material in the slit after the semiconductor layer is formed is favorably reduced, and the yield of the processed semiconductor structure is favorably improved. On the other hand, the method can be compatible with the process for removing the natural oxide layer under the condition that the waiting time is exceeded, thereby being beneficial to improving the flexibility of the process treatment of the semiconductor structure and saving the production cost of scrapping the semiconductor structure due to the removal of the natural oxide layer.
Another aspect of the present application also provides a three-dimensional memory, which may include: the semiconductor device comprises a laminated structure, a gate gap structure, a slit structure and a semiconductor layer.
The grid gap structure penetrates through the laminated structure and is arranged to protrude out of the laminated structure. The slit structure is located between the gate slit structure and the stacked structure, and the material of the slit structure is a dielectric material. The semiconductor layer is arranged to cover the slit structure.
In some embodiments, the dielectric material comprises silicon oxide.
In some embodiments, the three-dimensional memory further comprises a channel structure. The channel structure is disposed through and protruding from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure includes an outer wall of the channel layer, and the semiconductor layer is in contact with the channel layer.
Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.
The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. A processing method of a semiconductor structure, wherein the semiconductor structure comprises a laminated structure, a gate gap structure penetrating through the laminated structure and protruding out of the laminated structure, and a slit between the gate gap structure and the laminated structure, wherein the processing method comprises:
forming a dielectric layer in the slit; and
and forming a semiconductor layer covering the dielectric layer.
2. The processing method as claimed in claim 1, wherein the dielectric layer is formed in the slit while covering a first side of the stacked structure with a portion of the gate slit structure protruding from the stacked structure on the first side.
3. The processing method as claimed in claim 1, wherein the semiconductor structure further comprises a channel structure penetrating through the stacked structure and protruding from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure has an outer wall of a channel layer, the dielectric layer is formed in the slit while covering the channel layer with the dielectric layer, and the portion of the channel structure protruding from the stacked structure is located on the first side.
4. The processing method according to claim 2 or 3, characterized in that after the step of forming a dielectric layer in the slit, the processing method further comprises:
removing a portion of the dielectric layer outside the slit.
5. The processing method according to claim 2 or 3, characterized in that the thickness of the portion of the dielectric layer outside the slit is greater than or equal to 15 nm.
6. The process of claim 3, wherein prior to the step of forming a dielectric layer in the slots, the process comprises:
and removing the natural oxide layer on the channel layer and forming the slit.
7. The process of claim 1, wherein the material of the dielectric layer comprises silicon oxide.
8. A three-dimensional memory, comprising:
a laminated structure;
the grid gap structure penetrates through the laminated structure and protrudes out of the laminated structure;
the slit structure is positioned between the gate slit structure and the laminated structure, and the material of the slit structure is a dielectric material; and
and the semiconductor layer covers the slit structure.
9. The three-dimensional memory according to claim 8, wherein the dielectric material comprises silicon oxide.
10. The three-dimensional memory according to claim 8, further comprising:
and the channel structure penetrates through the laminated structure and protrudes out of the laminated structure, wherein the part of the channel structure protruding out of the laminated structure is provided with the outer wall of a channel layer, and the semiconductor layer is in contact with the channel layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111292815.8A CN114093880A (en) | 2021-11-03 | 2021-11-03 | Processing method of semiconductor structure and three-dimensional memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111292815.8A CN114093880A (en) | 2021-11-03 | 2021-11-03 | Processing method of semiconductor structure and three-dimensional memory |
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| Publication Number | Publication Date |
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| CN114093880A true CN114093880A (en) | 2022-02-25 |
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| CN202111292815.8A Pending CN114093880A (en) | 2021-11-03 | 2021-11-03 | Processing method of semiconductor structure and three-dimensional memory |
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