CN117545275B

CN117545275B - Method for manufacturing semiconductor structure

Info

Publication number: CN117545275B
Application number: CN202410026735.5A
Authority: CN
Inventors: 宛伟
Original assignee: Changxin Xinqiao Storage Technology Co ltd
Current assignee: Changxin Xinqiao Storage Technology Co ltd
Priority date: 2024-01-08
Filing date: 2024-01-08
Publication date: 2024-05-14
Anticipated expiration: 2044-01-08
Also published as: CN117545275A

Abstract

The disclosure relates to the technical field of semiconductors, and provides a manufacturing method of a semiconductor structure, which is used for solving the technical problem that contact plugs in different areas need to be manufactured independently. The manufacturing method comprises the following steps: forming a barrier layer covering the substrate and a patterned first hard mask layer including a first opening pattern and a second opening pattern having a feature size larger than that of the first opening pattern; forming a spacer layer in the first hard mask layer; etching the barrier layer to form a third opening pattern by taking the first hard mask layer with the spacer layer as a mask; transferring the third opening pattern, the first opening pattern and the second opening pattern into the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole and a second contact hole; first and second contact plugs are formed in the first and second contact holes, respectively. Thus, the first contact plug and the second contact plug can be manufactured in the first area and the second area at the same time, and the manufacturing process is simplified.

Description

Method for manufacturing semiconductor structure

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.

Background

With the continuous development of mobile devices, mobile devices with battery power, such as mobile phones, tablet computers, wearable devices and the like, are increasingly applied to life, a memory is used as an indispensable element in the mobile devices, and great demands are put forward by people on the small size and integration of the memory.

Currently, dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in mobile devices at its fast transmission speed. However, in the manufacturing process of the DRAM, because the film layers of the different regions are different, the Contact (CT) plugs of the different regions need to be manufactured separately, which results in complicated manufacturing process and high production cost of the DRAM.

Disclosure of Invention

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps:

Providing a substrate, wherein the substrate comprises a first lamination layer positioned in a first area and a second lamination layer positioned in a second area, the first lamination layer comprises a first conductive layer, a first dielectric layer and a second dielectric layer which are sequentially stacked, the second lamination layer comprises a second conductive layer and a third dielectric layer which are sequentially stacked, the materials of the first dielectric layer and the second dielectric layer are different, the materials of the second dielectric layer and the third dielectric layer are the same, and the thickness of the first lamination layer is larger than the thickness of the second lamination layer in the direction perpendicular to the substrate;

forming a barrier layer covering the substrate;

Forming a patterned first hard mask layer on the barrier layer, the first hard mask layer including a first opening pattern and a second opening pattern exposing the barrier layer on the first stack and the second stack, respectively, a feature size of the first opening pattern being greater than a feature size of the second opening pattern;

Forming a spacer layer in the first hard mask layer, the spacer layer covering the first opening pattern sidewall and filling the second opening pattern;

etching the barrier layer on the first laminated layer by taking the first hard mask layer with the spacer layer as an etching mask to form a third opening pattern in the barrier layer;

Removing the spacer layer, and transferring the third opening pattern, the first opening pattern and the second opening pattern into the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole exposing the first conductive layer in the first dielectric layer and the second dielectric layer and a second contact hole exposing the second conductive layer in the third dielectric layer;

And forming a first contact plug and a second contact plug in the first contact hole and the second contact hole respectively, wherein the first contact plug and the second contact plug are connected with the first conductive layer and the second conductive layer respectively.

In some embodiments, the method of making further comprises:

forming a second hard mask layer covering the substrate; wherein the second hard mask layer is located between the substrate and the barrier layer;

The transferring the third opening pattern, the first opening pattern, and the second opening pattern into the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively, includes:

Performing a first etch to selectively etch the second hard mask layer to transfer the third opening pattern to the second hard mask layer;

Performing a second etching to selectively etch the barrier layer to transfer the first and second opening patterns to the barrier layer;

performing third etching, and selectively etching the second dielectric layer to transfer the third opening pattern to the second dielectric layer;

Performing a fourth etch to selectively etch the second hard mask layer to transfer the first and second opening patterns to the second hard mask layer;

And executing fifth etching, namely etching the first dielectric layer, the second dielectric layer and the third dielectric layer to transfer the third opening pattern to the first dielectric layer, transfer the first opening pattern to the second dielectric layer and transfer the second opening pattern to the third dielectric layer, so as to form the first contact hole and the second contact hole.

In some embodiments, the thicknesses of the first, second, and third dielectric layers are substantially equal; in the fifth etching, etching rates of the first dielectric layer, the second dielectric layer and the third dielectric layer are substantially the same.

In some embodiments, the method of making further comprises:

performing a sixth etching to selectively etch the second hard mask layer to transfer the third opening pattern to the second hard mask layer;

performing seventh etching, and selectively etching the second dielectric layer to transfer the third opening pattern to the second dielectric layer;

performing eighth etching to selectively etch the barrier layer to transfer the first and second opening patterns to the barrier layer;

Performing a ninth etching to selectively etch the second hard mask layer to transfer the first and second opening patterns to the second hard mask layer;

And performing tenth etching, namely etching the first dielectric layer, the second dielectric layer and the third dielectric layer to transfer the third opening pattern to the first dielectric layer, transfer the first opening pattern to the second dielectric layer and transfer the second opening pattern to the third dielectric layer, thereby forming the first contact hole and the second contact hole.

In some embodiments, the thicknesses of the first, second, and third dielectric layers are substantially equal; in the tenth etching, etching rates of the first dielectric layer, the second dielectric layer and the third dielectric layer are substantially the same.

In some embodiments, before forming the first contact plug and the second contact plug, the fabrication method further includes: and removing the remaining second hard mask layer.

In some embodiments, the forming the spacer layer in the first hard mask layer comprises:

forming a spacer material layer conformally covering the first hard mask layer;

and etching back the spacer material layer, wherein the spacer material layer remained on the side wall of the first opening pattern and the spacer material layer remained in the second opening pattern are used as the spacer layer.

In some embodiments, the forming the first contact plug and the second contact plug in the first contact hole and the second contact hole, respectively, includes:

forming a contact material layer, wherein the contact material layer covers the second dielectric layer and the third dielectric layer and fills the first contact hole and the second contact hole;

and etching the contact material layer back, wherein the contact material layer reserved in the first contact hole is used as the first contact plug, and the contact material layer reserved in the second contact hole is used as the second contact plug.

In some embodiments, the second contact plug has a T-shaped cross-sectional shape.

In some embodiments, the material of the first dielectric layer includes: silicon oxide;

the materials of the second dielectric layer and the third dielectric layer include: silicon nitride;

The material of the barrier layer comprises: amorphous silicon;

The material of the first hard mask layer includes: silicon oxynitride;

the material of the second hard mask layer includes: amorphous carbon;

The spacer layer comprises the following materials: silicon oxide.

In an embodiment of the disclosure, a barrier layer is formed to cover a substrate; forming a patterned first hard mask layer on the barrier layer, the first hard mask layer including a first opening pattern and a second opening pattern, a feature size of the first opening pattern being greater than a feature size of the second opening pattern; forming a spacer layer in the first hard mask layer, the spacer layer covering sidewalls of the first opening pattern and filling up the second opening pattern; etching the barrier layer on the first laminated layer by taking the first hard mask layer with the spacer layer as an etching mask to form a third opening pattern in the barrier layer; removing the spacer layer, and transferring the third opening pattern, the first opening pattern and the second opening pattern to the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole exposing the first conductive layer in the first dielectric layer and the second dielectric layer and a second contact hole exposing the second conductive layer in the third dielectric layer; first and second contact plugs are formed in the first and second contact holes, respectively. Therefore, the first contact plug and the second contact plug can be manufactured in the first area and the second area at the same time through one photoetching and one etching process, which is beneficial to simplifying the manufacturing process, shortening the process flow and saving the process cost.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure shown in an exemplary embodiment;

FIG. 2A is a schematic diagram illustrating a first photoresist layer formed according to an exemplary embodiment;

FIG. 2B is a schematic diagram illustrating an exemplary embodiment after forming a first photoresist pattern;

FIG. 2C is a schematic diagram illustrating an exemplary embodiment after transferring the first photoresist pattern to the first mask layer;

FIG. 2D is a schematic diagram illustrating an exemplary embodiment after forming a first contact hole;

FIG. 2E is a schematic diagram illustrating removal of the first mask layer in accordance with an exemplary embodiment;

FIG. 2F is a schematic illustration I after filling contact material, as shown in an exemplary embodiment;

fig. 2G is a schematic diagram illustrating a first contact plug formed in accordance with an exemplary embodiment;

FIG. 2H is a schematic diagram illustrating a second photoresist layer formed according to an exemplary embodiment;

FIG. 2I is a schematic diagram illustrating a second photoresist pattern formed according to an exemplary embodiment;

FIG. 2J is a schematic diagram illustrating an exemplary embodiment after transferring a second photoresist pattern to a second mask layer;

FIG. 2K is a schematic diagram illustrating an exemplary embodiment after forming a second contact hole;

FIG. 2L is a schematic diagram II after filling the contact material, as shown in an exemplary embodiment;

Fig. 2M is a schematic diagram illustrating a second contact plug formed in accordance with an exemplary embodiment;

Fig. 3 is a flow chart of a method of fabricating a semiconductor shown in an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a photoresist layer formed according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a first photoresist pattern and a second photoresist pattern formed according to an embodiment of the present disclosure;

Fig. 6 is a schematic view of a first opening pattern and a second opening pattern formed according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a photoresist layer removed according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram illustrating a spacer material layer formed in accordance with an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a back-etched spacer material layer shown in an embodiment of the present disclosure;

Fig. 10 is a schematic view of a third opening pattern formed according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram illustrating removal of a spacer layer according to an embodiment of the present disclosure;

Fig. 12 is a schematic view of an embodiment of the present disclosure after forming a first via;

fig. 13 is a schematic view of a fourth and fifth opening patterns formed according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram illustrating a third opening pattern transferred to a second dielectric layer according to an embodiment of the present disclosure;

Fig. 15 is a schematic view of the second and third vias formed as shown in an embodiment of the present disclosure;

Fig. 16 is a schematic view of a first contact hole and a second contact hole formed according to an embodiment of the present disclosure;

FIG. 17 is a schematic diagram illustrating removal of a second mask layer according to an embodiment of the present disclosure;

FIG. 18 is a schematic diagram illustrating a filled contact material according to an embodiment of the present disclosure;

Fig. 19 is a schematic view of the first contact plug and the second contact plug after formation, as shown in an embodiment of the present disclosure;

FIG. 20 is a schematic diagram illustrating a third opening pattern transferred to a second dielectric layer according to an embodiment of the present disclosure;

fig. 21 is a schematic view of a fourth and fifth opening patterns formed according to an embodiment of the present disclosure;

Fig. 22 is a schematic diagram of a semiconductor structure shown in an embodiment of the disclosure.

Detailed Description

The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It is to be understood that the meaning of the disclosure "on … …", "over … …" and "over … …" should be read in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

In the presently disclosed embodiments, the terms "first," "second," "third," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers.

Fig. 1 is a schematic view of a semiconductor structure 100 according to an exemplary embodiment, and fig. 2A to 2M are schematic views of a manufacturing process of the semiconductor structure 100 according to an exemplary embodiment. An exemplary description of the semiconductor structure 100 and its fabrication process will now be provided with reference to fig. 1, 2A-2M.

Referring to fig. 1, the semiconductor structure 100 includes a substrate 110, a first conductive layer 121, a second conductive layer 122, a first dielectric structure 131, a second dielectric structure 132, a first contact plug 141, and a second contact plug 142; the first conductive layer 121, the first dielectric structure 131 and the first contact plug 141 are located in the first area A1, and the first contact plug 141 penetrates through the first dielectric structure 131 and is connected with the first conductive layer 121; the second conductive layer 122, the second dielectric structure 132 and the second contact plug 142 are located in the second area A2, and the second contact plug 142 penetrates through the second dielectric structure 132 and is connected to the second conductive layer 122. In this example, the first area A1 may be one of an array area and a peripheral area, and the second area A2 may be the other of the array area and the peripheral area.

In some embodiments, the film layers of the first dielectric structure 131 and the second dielectric structure 132 are different, as shown in fig. 1, the first dielectric structure 131 includes a stacked first dielectric layer 1311 and second dielectric layer 1312, the second dielectric structure 132 includes a third dielectric layer, the materials of the first dielectric layer 1311 and the second dielectric layer 1312 are different, and the materials of the second dielectric layer 1312 and the third dielectric layer are the same. Because the film layers of the first dielectric structure 131 and the second dielectric structure 132 are different, separate photolithography and etching are required for the first contact plug 141 and the second contact plug 142, which results in a complex manufacturing process and high production cost (for example, two photomasks are required) of the semiconductor structure 100. The process of fabricating the first contact plug 141 and the second contact plug 142 will be described in detail below with reference to fig. 2A to 2M.

Referring to fig. 2A, a base is provided, the base including a substrate 110, a first conductive layer 121, a second conductive layer 122, a first initial dielectric structure 131', and a second initial dielectric structure 132'; wherein the first conductive layer 121 and the first initial dielectric structure 131 'are located in the first area A1, and the first initial dielectric structure 131' includes a first initial dielectric layer 1311 'and a second initial dielectric layer 1312' stacked in sequence; the second conductive layer 122 and the second initial dielectric structure 132' are located in the second region A2, the second initial dielectric structure including a third initial dielectric layer. Here, the first initial dielectric layer 1311', the second initial dielectric layer 1312', and the third initial dielectric layer will be etched in a subsequent process to form the first dielectric layer 1311, the second dielectric layer 1312, and the third dielectric layer shown in fig. 1, respectively.

Sequentially forming a first mask layer 151 and a first photoresist layer 152 covering the substrate, as shown in fig. 2A; a first photolithography process is performed on the first photoresist layer 152 to form a first photoresist pattern 153 in the first photoresist layer 152, the first photoresist pattern 153 exposing a portion of the first mask layer 151 of the second region A2, as shown in fig. 2B.

A first etch process is performed to transfer the first photoresist pattern 153 into the second initial dielectric structure 132'. It is understood that after the first photoresist pattern 153 is transferred to the second preliminary dielectric structure 132', the first contact hole 154 may be formed, the bottom of the first contact hole 154 exposes the second conductive layer 122, the remaining second preliminary dielectric structure 132' constitutes the second dielectric structure 132, and the remaining third preliminary dielectric layer constitutes the third dielectric layer, as shown in fig. 2B to 2D.

The second contact plug 142 is formed in the first contact hole 154. The remaining first mask layer 151 may be removed before the second contact plug 142 is formed; the first contact hole 154 is filled with a contact material, and the contact material is etched back until the third dielectric layer is exposed, thereby forming the second contact plug 142, as shown in fig. 2D to 2G.

Sequentially forming a second mask layer 161 and a second photoresist layer 162 covering the third dielectric layer, the second contact plug 142 and the first preliminary dielectric structure 131', as shown in fig. 2H; a second photolithography process is performed on the second photoresist layer 162 to form a second photoresist pattern 163 in the second photoresist layer 162, the second photoresist pattern 163 exposing a portion of the second mask layer 161 of the first region A1, as shown in fig. 2I.

A second etching process is performed to transfer the second photoresist pattern 163 into the first preliminary dielectric structure 131'. It can be appreciated that after the second photoresist pattern 163 is transferred to the first initial dielectric structure 131', the second contact hole 164 may be formed, the bottom of the second contact hole 164 exposes the first conductive layer 121, the remaining first initial dielectric structure 131' forms the first dielectric structure 131, and the remaining first initial dielectric layer 1311 'and the second initial dielectric layer 1312' form the first dielectric layer 1311 and the second dielectric layer 1312, respectively, as shown in fig. 2I to 2K.

The first contact plug 141 is formed in the second contact hole 164. The remaining second mask layer 161 may be removed before the first contact plug 141 is formed; the second contact hole 164 is filled with a contact material, and the contact material is etched back to form a first contact plug 141, as shown in fig. 2K to 2M.

In the above examples of fig. 2A to 2M, the second contact plug 142 of the second area A2 is formed first, and then the first contact plug 141 of the first area A1 is formed, that is, the first contact plug 141 and the second contact plug 142 are separately manufactured and need to perform two photolithography processes and two etching processes, which results in complex manufacturing process and high production cost of the semiconductor structure 100.

In view of the foregoing, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.

Fig. 3 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the disclosure. Referring to fig. 3, the manufacturing method at least includes the following steps:

S210: providing a substrate, wherein the substrate comprises a first lamination layer positioned in a first area and a second lamination layer positioned in a second area, the first lamination layer comprises a first conductive layer, a first dielectric layer and a second dielectric layer which are sequentially stacked, the second lamination layer comprises a second conductive layer and a third dielectric layer which are sequentially stacked, the materials of the first dielectric layer and the second dielectric layer are different, the materials of the second dielectric layer and the third dielectric layer are the same, and the thickness of the first lamination layer is larger than that of the second lamination layer in the direction vertical to the substrate;

s220: forming a barrier layer covering the substrate;

S230: forming a patterned first hard mask layer on the barrier layer, the first hard mask layer including a first opening pattern and a second opening pattern exposing the barrier layer on the first stack and the second stack, respectively, the first opening pattern having a feature size greater than a feature size of the second opening pattern;

S240: forming a spacer layer in the first hard mask layer, the spacer layer covering sidewalls of the first opening pattern and filling up the second opening pattern;

S250: etching the barrier layer on the first laminated layer by taking the first hard mask layer with the spacer layer as an etching mask to form a third opening pattern in the barrier layer;

S260: removing the spacer layer, and transferring the third opening pattern, the first opening pattern and the second opening pattern to the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole exposing the first conductive layer in the first dielectric layer and the second dielectric layer and a second contact hole exposing the second conductive layer in the third dielectric layer;

s270: and forming a first contact plug and a second contact plug in the first contact hole and the second contact hole respectively, wherein the first contact plug and the second contact plug are connected with the first conductive layer and the second conductive layer respectively.

It should be noted that the steps shown in fig. 3 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 3 can be sequentially adjusted according to actual requirements.

Fig. 4 to 21 are schematic views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure. A method for fabricating a semiconductor structure according to an embodiment of the present disclosure will be exemplarily described with reference to fig. 3 and fig. 4 to 21.

In step S210, referring to fig. 4, a substrate is provided, the substrate including a first stack 320 located in a first region A1 and a second stack 330 located in a second region A2, the first stack 320 including a first conductive layer 321, a first dielectric layer 322, and a second dielectric layer 323 stacked in this order, the second stack 330 including a second conductive layer 331 and a third dielectric layer 332 stacked in this order, the materials of the first dielectric layer 322 and the second dielectric layer 323 being different, the materials of the second dielectric layer 323 and the third dielectric layer 332 being the same, and the thickness of the first stack 320 being greater than the thickness of the second stack 330 in a direction perpendicular to the substrate.

In some embodiments, referring to fig. 4, the step S210 includes: providing a substrate 310; a first stack 320 and a second stack 330 are formed on a substrate 310. For example, an initial conductive layer and a first initial dielectric layer are sequentially formed overlying the substrate 310; etching the first initial dielectric layer positioned in the second area A2 until the initial conductive layer is exposed, wherein the reserved first initial dielectric layer forms a first dielectric layer 322; a second initial dielectric layer is formed overlying the exposed initial conductive layer and the first dielectric layer 322, the second initial dielectric layer being of a different material than the first initial dielectric layer.

In this embodiment, part of the film layers in the first stack 320 and the second stack 330 may be formed at the same time, so that the process may be simplified. For example, the first conductive layer 321 and the second conductive layer 331 are formed simultaneously and the second dielectric layer 323 and the third dielectric layer 332 are formed simultaneously. Of course, in other embodiments, the first stack 320 and the second stack 330 may each be formed separately. It should be noted that the first stack 320 and the second stack 330 in fig. 4 are only examples, the number of the film layers in the first stack 320 and the second stack 330 is not limited thereto, and those skilled in the art can reasonably set according to actual needs, and the disclosure is not particularly limited thereto.

For ease of understanding, the initial conductive layer and the second initial dielectric layer located in the first region A1 may be denoted as a first conductive layer 321 and a second dielectric layer 323, respectively, and the initial conductive layer and the second initial dielectric layer located in the second region A2 may be denoted as a second conductive layer 331 and a third dielectric layer 332, respectively. Accordingly, the first conductive layer 321 and the second conductive layer 331 are the same, the first dielectric layer 322 and the second dielectric layer 323 are different, and the second dielectric layer 323 and the third dielectric layer 332 are the same.

In some embodiments, the thicknesses of the first dielectric layer 322, the second dielectric layer 323, and the third dielectric layer 332 are substantially equal. It should be noted that "substantially equal" as used in this disclosure means completely equal or having an error, but the error is within the allowable process error.

The material of the substrate 310 includes an elemental semiconductor material (e.g., silicon (Si) or germanium (Ge), etc.), a group III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), etc.), a group II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art, and the substrate 310 will be described as a silicon substrate in this embodiment.

The materials of the first conductive layer 321 and the second conductive layer 331 include conductive materials, such as at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, platinum, titanium, or aluminum, and in this embodiment, the first conductive layer 321 and the second conductive layer 331 are both tungsten layers.

The material of the first dielectric layer 322 may include silicon oxide, and the material of the second dielectric layer 323 and the third dielectric layer 332 may include silicon nitride, and in this embodiment, the first dielectric layer 322 is a silicon oxide layer, and the second dielectric layer 323 and the third dielectric layer 332 are silicon nitride layers.

In some embodiments, referring to fig. 4, the above manufacturing method further includes: a second hard mask layer 340 is formed overlying the substrate. For example, forming a spin-on hard mask (Spin On Hardmask, SOH) on a substrate; the spin-on hard mask is subjected to a curing process, and the cured spin-on hard mask constitutes a second hard mask layer 340, the second hard mask layer 340 being located between the substrate and a barrier layer 350 formed later, and the material of the second hard mask layer 340 may include amorphous carbon or spin-on carbon.

In step S220, referring to fig. 4, a barrier layer 350 is formed to cover the substrate. For example, the barrier layer 350 as shown in fig. 4 may be formed through a thin film deposition process, and the material of the barrier layer 350 may include polysilicon or amorphous silicon, etc.

In step S230, referring to fig. 6 and 7, a patterned first hard mask layer 360 is formed on the barrier layer 350, the first hard mask layer 360 including a first opening pattern 361 and a second opening pattern 362, the first opening pattern 361 and the second opening pattern 362 exposing the barrier layer 350 on the first stack 320 and the second stack 330, respectively, a feature size D1 of the first opening pattern 361 being greater than a feature size D2 of the second opening pattern 362. Here, the patterned first hard mask layer 360 may be formed through photolithography and etching processes, and the material of the first hard mask layer 360 may include silicon oxynitride, and the first hard mask layer 360 will be described as an example of a silicon oxynitride layer in this embodiment.

Illustratively, referring to fig. 4, a first hard mask layer 360 and a photoresist layer 370 are sequentially formed to cover the barrier layer 350; performing exposure and development treatment on the photoresist layer 370 to form a patterned photoresist layer 370, as shown in fig. 5, wherein the patterned photoresist layer 370 includes a first photoresist pattern 371 located in the first region A1 and a second photoresist pattern 372 located in the second region A2, and the feature size of the first photoresist pattern 371 is larger than that of the second photoresist pattern 372; transferring the first and second photoresist patterns 371 and 372 into the first hard mask layer 360, thereby forming first and second opening patterns 361 and 362 as shown in fig. 6; thereafter, if there is a remaining photoresist layer 370, the remaining photoresist layer 370 is removed, as shown in fig. 7. In practical applications, the sizes of the first photoresist pattern 371 and the second photoresist pattern 372 can be adjusted by designing a mask (also called a photomask), so that the feature size of the first photoresist pattern 371 is larger than that of the second photoresist pattern 372.

It should be noted that the feature sizes used in the present disclosure are used to represent geometric shapes, sizes, features, etc. of patterns. For example, the feature size may include at least one of a length, width, diameter, radius, and like geometric parameters.

In step S240, referring to fig. 9, a spacer layer 380 is formed in the first hard mask layer 360, the spacer layer 380 covering sidewalls of the first opening pattern 361 and filling the second opening pattern 362. The material of the spacer layer 380 may include silicon oxide, and in this embodiment, the spacer layer 380 will be exemplified as a silicon oxide layer.

In some embodiments, the step S240 includes: forming a spacer material layer 380' conformally covering the first hard mask layer 360, as shown in fig. 8; the spacer material layer 380' is etched back, and the spacer material layer 380' remaining on the sidewalls of the first opening pattern 361 and the spacer material layer 380' remaining in the second opening pattern 362 serve as spacer layers 380, as shown in fig. 9.

In this embodiment, since the uniformity, shape retention and compactness of the atomic layer thin film deposition technique are good, the atomic layer thin film deposition technique can be used to form the spacer material layers 380' with substantially equal thickness at each position, and the spacer material layers 380' are etched back until the first hard mask layer 360 is exposed, the spacer material layers 380' on the bottom of the first opening pattern 361 are removed, the spacer material layers 380' on the sidewalls of the first opening pattern 361 remain, and the second opening pattern 362 is substantially filled with the spacer material layers 380', so as to form the spacer layer 380 shown in fig. 9.

In step S250, referring to fig. 10, the barrier layer 350 on the first stack 320 is etched using the first hard mask layer 360 formed with the spacer layer 380 as an etching mask to form a third opening pattern 351 in the barrier layer 350. In this embodiment, since the material of the barrier layer 350 is different from the material of the first hard mask layer 360 and the material of the spacer layer 380, by adjusting the etching selectivity of the barrier layer 350, the first hard mask layer 360 and the spacer layer 380, it is ensured that the exposed barrier layer 350 in fig. 9 is etched and the first hard mask layer 360 and the spacer layer 380 are not substantially etched, thereby forming the third opening pattern 351 shown in fig. 10. It is understood that the feature size of the third opening pattern 351 is smaller than that of the first opening pattern 361.

In step S260, referring to fig. 11 to 16, the spacer layer 380 is removed, and the third opening pattern 351, the first opening pattern 361, and the second opening pattern 362 are transferred into the first dielectric layer 322, the second dielectric layer 323, and the third dielectric layer 332, respectively, to form a first contact hole 391 exposing the first conductive layer 321 in the first dielectric layer 322 and the second dielectric layer 323, and to form a second contact hole 392 exposing the second conductive layer 331 in the third dielectric layer 332.

In some embodiments, the step S260 includes: performing a first etch to selectively etch the second hard mask layer 340 to transfer the third opening pattern 351 to the second hard mask layer 340; performing a second etch to selectively etch the barrier layer 350 to transfer the first and second opening patterns 361 and 362 to the barrier layer 350; performing a third etching to selectively etch the second dielectric layer 323 to transfer the third opening pattern 351 to the second dielectric layer 323; performing a fourth etching to selectively etch the second hard mask layer 340 to transfer the first and second opening patterns 361 and 362 to the second hard mask layer 340; a fifth etch is performed to etch the first, second and third dielectric layers 322, 323 and 332 to transfer the third opening pattern 351 to the first dielectric layer 322, to transfer the first opening pattern 361 to the second dielectric layer 323, and to transfer the second opening pattern 362 to the third dielectric layer 332, thereby forming first and second contact holes 391 and 392.

After forming the third opening pattern 351, the spacer layer 380 may be removed, forming a structure as shown in fig. 11. Referring to fig. 11, the third opening pattern 351 and the first opening pattern 361 communicate, the third opening pattern 351 exposes a portion of the second hard mask layer 340, and the second opening pattern 362 exposes a portion of the blocking layer 350; the exposed second hard mask layer 340 is etched based on the third opening pattern 351, a first via hole 341 penetrating the second hard mask layer 340 is formed, and a bottom of the first via hole 341 exposes a portion of the second dielectric layer 323, thereby transferring the third opening pattern 351 to the second hard mask layer 340. It will be appreciated that in the first etching, since the material of the second hard mask layer 340 is different from the material of the barrier layer 350 and the material of the first hard mask layer 360, by adjusting the etching selectivity of the second hard mask layer 340, the barrier layer 350 and the first hard mask layer 360, it is ensured that the exposed second hard mask layer 340 is etched and the first hard mask layer 360 and the barrier layer 350 are not substantially etched, thereby forming the structure shown in fig. 12.

Illustratively, referring to fig. 12, the exposed barrier layer 350 is etched based on the first and second opening patterns 361 and 362 to form fourth and fifth opening patterns 352 and 353, respectively, in the barrier layer 350, thereby transferring the first and second opening patterns 361 and 362 to the barrier layer 350. It will be appreciated that in the second etching, since the material of the barrier layer 350 is different from the material of the first hard mask layer 360 and the exposed second dielectric layer 323, by adjusting the etching selectivity of the barrier layer 350, the first hard mask layer 360 and the second dielectric layer 323, it is ensured that the exposed barrier layer 350 is etched and the first hard mask layer 360 and the second dielectric layer 323 are not substantially etched in fig. 12, thereby forming the structure shown in fig. 13.

Illustratively, referring to fig. 13, the second dielectric layer 323 is etched based on the first via hole 341 until the first dielectric layer 322 is exposed, thereby transferring the third opening pattern 351 to the second dielectric layer 323. It will be appreciated that in the third etching, since the material of the second dielectric layer 323 is different from the material of the first hard mask layer 360 and the material of the second hard mask layer 340, by adjusting the etching selection ratio of the second dielectric layer 323, the first hard mask layer 360 and the second hard mask layer 340, it is ensured that the exposed second dielectric layer 323 is etched and the first hard mask layer 360 and the second hard mask layer 340 are not substantially etched, thereby forming the structure shown in fig. 14.

Illustratively, referring to fig. 14, the second hard mask layer 340 is etched based on the fourth opening pattern 352 and the fifth opening pattern 353, a second via hole 342 and a third via hole 343 are formed through the second hard mask layer 340, the second via hole 342 is located in the first region A1 and exposes the second dielectric layer 323, and the third via hole 343 is located in the second region A2 and exposes the third dielectric layer 332. It will be appreciated that in the fourth etching, since the material of the second hard mask layer 340 is different from the material of the first hard mask layer 360 and the material of the first dielectric layer 322, by adjusting the etching selectivity of the second hard mask layer 340, the first hard mask layer 360 and the first dielectric layer 322, it is ensured that the exposed second hard mask layer 340 is etched and the first hard mask layer 360 and the first dielectric layer 322 are not substantially etched in fig. 14. After the second and third via holes 342 and 343 are formed, if there is a remaining first hard mask layer 360 and barrier layer 350, the remaining first hard mask layer 360 and barrier layer 350 may be removed, thereby forming the structure shown in fig. 15.

Illustratively, referring to fig. 15, first contact hole 391 and second contact hole 392 are formed by etching first dielectric layer 322, second dielectric layer 323, and third dielectric layer 332 using remaining second hard mask layer 340 as an etching mask, first contact hole 391 exposing first conductive layer 321, and second contact hole 392 exposing second conductive layer 331. It can be understood that in the fifth etching, since the materials of the first dielectric layer 322 and the second dielectric layer 323 are different and the materials of the second dielectric layer 323 and the third dielectric layer 332 are the same, by adjusting the etching selection ratio of the first dielectric layer 322 and the second dielectric layer 323, the first dielectric layer 322, the second dielectric layer 323 and the third dielectric layer 332 exposed in fig. 15 can be ensured to be etched, thereby forming the structure shown in fig. 16.

In one embodiment, in the fifth etching, the etching rates of the first, second and third dielectric layers 322, 323 and 332 are substantially the same, thereby ensuring accurate transfer of the third opening patterns 351, 361 and 362 into the first, second and third dielectric layers 322, 323 and 332.

It should be noted that the first etching to the fifth etching are the same etching procedure, that is, the first etching to the fifth etching can be performed in the same etching equipment, and the components and/or the proportion of the etching gas introduced in each etching step in the first etching to the fifth etching are regulated so as to achieve the desired etching selection ratio, thereby realizing the selective etching of the film layers in different areas, and the first contact plug and the second contact plug can be manufactured in the first area A1 and the second area A2 at the same time by only performing one photoetching and one etching procedure, thereby being beneficial to simplifying the manufacturing process, shortening the technological process and saving the technological cost.

In other embodiments, the step S260 includes: performing a sixth etching to selectively etch the second hard mask layer 340 to transfer the third opening pattern 351 to the second hard mask layer 340; performing a seventh etch to selectively etch the second dielectric layer 323 to transfer the third opening pattern 351 to the second dielectric layer 323; performing an eighth etch to selectively etch the barrier layer 350 to transfer the first and second opening patterns 361 and 362 to the barrier layer 350; performing a ninth etching to selectively etch the second hard mask layer 340 to transfer the first and second opening patterns 361 and 362 to the second hard mask layer 340; a tenth etch is performed to etch the first, second and third dielectric layers 322, 323 and 332 to transfer the third opening pattern 351 to the first dielectric layer 322, to transfer the first opening pattern 361 to the second dielectric layer 323, and to transfer the second opening pattern 362 to the third dielectric layer 332, thereby forming first and second contact holes 391 and 392.

In this embodiment, the sixth etching is similar to the first etching, the ninth etching is similar to the fourth etching, and the tenth etching is similar to the fifth etching, and for the sixth etching, the ninth etching, and the tenth etching, reference may be made to the related descriptions of the first etching, the fourth etching, and the fifth etching, respectively, and for brevity, description will not be repeated. The seventh etching and the eighth etching will be exemplarily described below with reference to fig. 12, 20, and 21.

Illustratively, referring to fig. 12, the second dielectric layer 323 is etched based on the first via hole 341 until the first dielectric layer 322 is exposed, thereby transferring the third opening pattern 351 to the second dielectric layer 323. It will be appreciated that in the seventh etching, since the material of the second dielectric layer 323 is different from the material of the first hard mask layer 360 and the material of the barrier layer 350, by adjusting the etching selectivity of the second dielectric layer 323, the first hard mask layer 360 and the barrier layer 350, it is ensured that the exposed second dielectric layer 323 is etched and the first hard mask layer 360 and the barrier layer 350 are not substantially etched, thereby forming the structure shown in fig. 20.

Illustratively, the exposed barrier layer 350 is etched based on the first and second opening patterns 361 and 362 to form the fourth and fifth opening patterns 352 and 353, respectively, in the barrier layer 350, thereby transferring the first and second opening patterns 361 and 362 to the barrier layer 350. It will be appreciated that in the eighth etching, since the material of the barrier layer 350 is different from the material of the first hard mask layer 360 and the exposed material of the first dielectric layer 322, by adjusting the etching selectivity of the barrier layer 350, the first hard mask layer 360 and the first dielectric layer 322, it is ensured that the exposed barrier layer 350 is etched and the first hard mask layer 360 and the first dielectric layer 322 are not substantially etched in fig. 20, thereby forming the structure shown in fig. 21.

It can be understood that in this embodiment, after the sixth etching, the second dielectric layer 323 is selectively etched to transfer the third opening pattern 351 to the second dielectric layer 323, and then the selective etching barrier layer 350 transfers the first opening pattern 361 and the second opening pattern 362 to the barrier layer 350, so that the structure substantially the same as that of fig. 14 can be formed, and the subsequent steps can be performed, i.e., the first etching to the fifth etching (or the sixth etching to the tenth etching) can be sequentially adjusted according to the actual requirements, so as to meet different production requirements, and increase the flexibility of the process production.

In some embodiments, in the tenth etch, the etch rates of first dielectric layer 322, second dielectric layer 323, and third dielectric layer 332 are substantially the same. For the tenth etching, reference may be made to the description of the fifth etching, and for brevity, description will not be repeated.

In some embodiments, referring to fig. 16, the above manufacturing method further includes: the remaining second hard mask layer 340 is removed, thereby forming the structure shown in fig. 17. The removal process of the second hard mask layer 340 includes a dry etching, an ashing process, and the like.

In step S270, as shown with reference to fig. 19, a first contact plug 324 and a second contact plug 334 are formed in the first contact hole 391 and the second contact hole 392, respectively, and the first contact plug 324 and the second contact plug 334 are connected to the first conductive layer 321 and the second conductive layer 331, respectively. The material of the first contact plug 324 and the second contact plug 334 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, platinum, titanium, or aluminum.

In some embodiments, referring to fig. 18 and 19, the step S270 includes: forming a contact material layer covering the second dielectric layer 323 and the third dielectric layer 332 and filling the first contact hole 391 and the second contact hole 392; the contact material layer is etched back, the contact material layer remaining in the first contact hole 391 serves as the first contact plug 324, and the contact material layer remaining in the second contact hole 392 serves as the second contact plug 334. In this embodiment, the contact material layer may be formed by a thin film deposition process, and the contact material layer is etched back by a dry etching or a chemical mechanical polishing process until the second dielectric layer and the third dielectric layer are exposed.

In some embodiments, the cross-sectional shape of the second contact plug 334 is T-shaped, while the cross-sectional shape of the first contact plug 324 is rectangular or inverted trapezoidal.

In the method for manufacturing the semiconductor structure provided by the embodiment of the disclosure, a barrier layer covering a substrate is formed; forming a patterned first hard mask layer on the barrier layer, the first hard mask layer including a first opening pattern and a second opening pattern, a feature size of the first opening pattern being greater than a feature size of the second opening pattern; forming a spacer layer in the first hard mask layer, the spacer layer covering sidewalls of the first opening pattern and filling up the second opening pattern; etching the barrier layer on the first laminated layer by taking the first hard mask layer with the spacer layer as an etching mask to form a third opening pattern in the barrier layer; removing the spacer layer, and transferring the third opening pattern, the first opening pattern and the second opening pattern to the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole exposing the first conductive layer in the first dielectric layer and the second dielectric layer and a second contact hole exposing the second conductive layer in the third dielectric layer; first and second contact plugs are formed in the first and second contact holes, respectively. Therefore, the first contact plug and the second contact plug can be manufactured in the first area and the second area at the same time through one photoetching and one etching process, which is beneficial to simplifying the manufacturing process, shortening the process flow and saving the process cost.

Fig. 22 is a schematic diagram of a semiconductor structure 300 shown in an embodiment of the disclosure. Referring to fig. 22, the semiconductor structure 300 includes a first stack 320 located in a first region A1 and a second stack 330 located in a second region A2, the first stack 320 including a first conductive layer 321, a first dielectric layer 322, and a second dielectric layer 323 stacked in sequence, the second stack 330 including a second conductive layer 331 and a third dielectric layer 332 stacked in sequence, the materials of the first dielectric layer 322 and the second dielectric layer 323 being different, the materials of the second dielectric layer 323 and the third dielectric layer 332 being the same, and the thickness of the first stack 320 being greater than the thickness of the second stack 330. The first stack 320 and the second stack 330 may both be located over the substrate 310, the first region A1 may be one of an array region and a peripheral region, and the second region A2 may be the other of the array region and the peripheral region. Semiconductor structure 300 includes, but is not limited to, a DRAM.

The semiconductor structure 300 further includes a first contact plug 324 located in the first area A1 and a second contact plug 334 located in the second area A2, wherein the first contact plug 324 penetrates through the first dielectric layer 322 and the second dielectric layer 323 and is connected with the first conductive layer 321, and the second contact plug 334 penetrates through the third dielectric layer 332 and is connected with the second conductive layer 331. The first contact plug 324 is used to electrically draw out the first conductive layer 321 of the first region A1, and the second contact plug 334 is used to electrically draw out the second conductive layer 331 of the second region A2.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a barrier layer covering the substrate;

Removing the spacer layer, and transferring the third opening pattern, the first opening pattern and the second opening pattern into the first dielectric layer, the second dielectric layer and the third dielectric layer respectively to form a first contact hole exposing the first conductive layer in the first dielectric layer and the second dielectric layer and a second contact hole exposing the second conductive layer in the third dielectric layer; the etching rates of the first dielectric layer, the second dielectric layer and the third dielectric layer are basically the same;

2. The method of manufacturing according to claim 1, further comprising:

3. The method of claim 2, wherein the thicknesses of the first dielectric layer, the second dielectric layer, and the third dielectric layer are substantially equal.

4. The method of manufacturing according to claim 1, further comprising:

5. The method of claim 4, wherein the thicknesses of the first dielectric layer, the second dielectric layer, and the third dielectric layer are substantially equal.

6. The manufacturing method according to claim 2 or 4, characterized in that before forming the first contact plug and the second contact plug, the manufacturing method further comprises:

and removing the remaining second hard mask layer.

7. The method of any one of claims 1 to 5, wherein forming the spacer layer in the first hard mask layer comprises:

forming a spacer material layer conformally covering the first hard mask layer;

8. The method according to any one of claims 1 to 5, wherein the forming the first contact plug and the second contact plug in the first contact hole and the second contact hole, respectively, includes:

9. The method according to any one of claims 1 to 5, wherein the second contact plug has a T-shaped cross-section.

10. The method of claim 2 or 4, wherein the material of the first dielectric layer comprises: silicon oxide;

The material of the barrier layer comprises: amorphous silicon;

The material of the first hard mask layer includes: silicon oxynitride;

the material of the second hard mask layer includes: amorphous carbon;

The spacer layer comprises the following materials: silicon oxide.