CN114823486A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114823486A
CN114823486A CN202110091012.XA CN202110091012A CN114823486A CN 114823486 A CN114823486 A CN 114823486A CN 202110091012 A CN202110091012 A CN 202110091012A CN 114823486 A CN114823486 A CN 114823486A
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China
Prior art keywords
layer
forming
core layer
core
semiconductor structure
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CN202110091012.XA
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Chinese (zh)
Inventor
陈栋
姚达林
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110091012.XA priority Critical patent/CN114823486A/en
Publication of CN114823486A publication Critical patent/CN114823486A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched; forming a buffer layer on the layer to be etched; forming a core layer on the buffer layer, wherein the material of the core layer is different from that of the buffer layer, a plurality of first openings are formed in the core layer, and part of the surface of the buffer layer is exposed by the first openings; forming a side wall on the side wall of the first opening, wherein the material of the side wall is different from that of the core layer, and the material of the side wall is different from that of the buffer layer; etching the buffer layer by taking the core layer as a mask, and forming a second opening in the buffer layer; after forming a second opening, removing the core layer and the side walls; and after removing the core layer and the side wall, etching the layer to be etched by taking the buffer layer as a mask. The performance of the semiconductor structure formed by the method is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
At present, in a back end of line (BEOL) process of a semiconductor device, when a semiconductor integrated circuit is manufactured, after a semiconductor device layer is formed, a metal interconnection layer needs to be formed on the semiconductor device layer, each metal interconnection layer includes a metal interconnection line and an interlayer dielectric layer (ILD), which requires that a trench (trench) and a connection hole (Via) are formed in the interlayer dielectric layer, and then metal is deposited in the trench and the connection hole, where the deposited metal is the metal interconnection line.
However, there are also some problems to be improved in the process of manufacturing the trench and the connection hole.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming a buffer layer on the layer to be etched; forming a core layer on the buffer layer, wherein the material of the core layer is different from that of the buffer layer, a plurality of first openings are formed in the core layer, and part of the surface of the buffer layer is exposed by the first openings; forming a side wall on the side wall of the first opening, wherein the material of the side wall is different from that of the core layer, and the material of the side wall is different from that of the buffer layer; etching the buffer layer by taking the core layer as a mask, and forming a second opening in the buffer layer; after forming a second opening, removing the core layer and the side walls; and after removing the core layer and the side wall, etching the layer to be etched by taking the buffer layer as a mask.
Optionally, after forming the sidewall, before etching the buffer layer by using the core layer as a mask, the method further includes: and forming a filling layer in the sacrificial layer or the core layer, wherein the filling layer is positioned between the adjacent side walls.
Optionally, the method for forming the filling layer in the sacrificial layer or the core layer includes: forming a sacrificial layer in the first opening; forming a patterned mask structure on the sacrificial layer and the core layer, wherein the patterned mask structure exposes a part of the surface of the core layer or a part of the surface of the sacrificial layer; etching the sacrificial layer or the core layer by taking the patterned mask structure as a mask, forming a third opening in the sacrificial layer or the core layer, and exposing the side wall at two sides of the third opening; and forming a filling layer in the third openings, wherein the filling layer penetrates through the sacrificial layer along the first direction parallel to the surface of the substrate, or penetrates through the core layer between the adjacent first openings along the first direction parallel to the surface of the substrate.
Optionally, after forming the filling layer, removing the sacrificial layer; after removing the sacrificial layer, a portion of the core layer is removed, and a fourth opening is formed in the core layer.
Optionally, the method for forming the second opening further includes: and etching the buffer layer by taking the core layer, the side wall and the filling layer as masks until the surface of the layer to be etched is exposed, and forming the second opening.
Optionally, after forming the second opening, removing the core layer and the side wall, and simultaneously further including: and removing the filling layer.
Optionally, the method for removing the core layer, the side wall, and the filling layer includes a first step and a second step after the first step; the first step is to remove the core layer, the process for removing the core layer comprises a dry etching process or a wet etching process, etching gas of the dry etching process comprises plasma of nitrogen trifluoride and ammonia gas, and etching liquid of the wet etching process comprises hydrofluoric acid; and the second step is to remove the side wall and the filling layer, wherein the process for removing the side wall and the filling layer comprises a wet etching process, and etching liquid of the wet etching process comprises mixed solution of hydrogen peroxide and hydrofluoric acid. Optionally, the process for removing the core layer, the side wall, and the filling layer includes a wet etching process, and an etching solution of the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid.
Optionally, the material of the filling layer is the same as that of the side wall.
Optionally, the material of the sacrificial layer is different from that of the core layer, the material of the sacrificial layer is different from that of the side wall, and the material of the sacrificial layer is different from that of the buffer layer.
Optionally, the material of the sacrificial layer includes silicon nitride.
Optionally, the material of the sidewall includes an oxide of metal titanium or an oxide of metal tantalum.
Optionally, the material of the core layer comprises silicon oxide.
Optionally, the material of the buffer layer includes silicon.
Optionally, the thickness range of the buffer layer is: 300 to 1000 angstroms.
Optionally, before forming the buffer layer on the layer to be etched, the method further includes: forming a first stop layer on the layer to be etched; the material of the first stop layer is different from the material of the buffer layer, and the material of the first stop layer is different from the material of the core layer.
Optionally, the layer to be etched includes a substrate, and the substrate includes: a substrate; the device comprises a substrate, a device layer, a first electrode, a second electrode, a third electrode and a fourth electrode, wherein the device layer is positioned on the substrate and comprises an isolation structure and a device structure positioned in the isolation structure, and the device structure comprises a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure and the like; a conductive layer on the device layer, the conductive layer electrically connected to the device structure; and etching the conducting layer by taking the buffer layer as a mask until the surface of the device layer is exposed.
Optionally, the layer to be etched further includes: a second stop layer on the substrate; a hard mask layer on the second stop layer; a third stop layer on the hard mask layer; the forming method further includes: and etching the first stop layer, the third stop layer, the hard mask layer, the second stop layer and the conducting layer by taking the buffer layer as a mask until the surface of the device layer is exposed.
Optionally, the material of the first stop layer includes silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure in the technical scheme, the buffer layer is formed on the layer to be etched, the material of the buffer layer is different from that of the core layer, the buffer layer is etched by taking the core layer as a mask, the second opening is formed in the buffer layer, and after the second opening is formed, the core layer and the side wall are removed. After the patterns of the core layer and the side wall are transferred to the buffer layer, the core layer and the side wall are removed, so that the material of the core layer, the material of the side wall and reaction byproducts generated by the material in the core layer forming process can be completely removed, the condition that the material of the core layer, the material of the side wall and the reaction byproducts generated by the material in the core layer forming process are transferred to the layer to be etched to influence the formed semiconductor structure is avoided, and the performance of the semiconductor structure is improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of a semiconductor structure formation process in one embodiment;
fig. 3 to 16 are schematic views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the process of fabricating the trench and the connection hole still needs to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic diagrams of a process for forming a semiconductor structure in one embodiment.
Please refer to fig. 1, which includes: providing a layer to be etched 100; forming a first stop layer 101 on the layer to be etched 100; forming a hard mask layer 102 on the first stop layer 101; forming a second stop layer 103 on the hard mask layer 102; forming a core layer 104 and a plurality of openings (not shown) in the core layer 104 on the second stop layer 103; forming a side wall 105 on the side wall of the core layer 104; after forming the side walls 105, forming a sacrificial layer (not shown) in the openings; after forming the sacrificial layer, removing a portion of the core layer 104, and forming a first groove (not shown) in the core layer 104; forming a first filling layer 106 in the first groove; removing part of the sacrificial layer to form a second groove (not shown) in the sacrificial layer; a second fill-in layer 107 is formed within the second recess.
Referring to fig. 2, the core layer 104, the sidewall spacers 105, the first filling layer 106 and the second filling layer 107 are used as masks to etch the second stop layer 103 and the hard mask layer 102, and a hard mask pattern 108 is formed on the first stop layer 101.
In the formation process of the semiconductor structure, the materials of the core layer 104, the sidewall 105, the first filling layer 106 and the second filling layer 107 are different from each other, and the materials of the core layer 104, the sidewall 105, the first filling layer 106 and the second filling layer 107 are different from the material of the hard mask layer 102. In the process of forming the hard mask pattern 108 by etching, the core layer 104, the sidewall 105, the first filling layer 106 and the second filling layer 107 are naturally consumed in the etching process, however, since the materials of the core layer 104, the sidewall 105, the first filling layer 106 and the second filling layer 107 are different from the material of the hard mask layer 102, a large amount of reaction byproducts 109 may remain on the hard mask pattern 108 after the hard mask pattern 108 is formed. Subsequently, when the layer to be etched 100 is continuously etched by using the hard mask pattern 108, the reaction by-product 109 remaining on the hard mask pattern 108 is also transferred to the layer to be etched 100, so that the dimensional accuracy of the formed semiconductor structure is affected, and the performance of the formed semiconductor structure is further affected.
In order to solve the above problems, a technical solution of the present invention provides a method for forming a semiconductor structure, in which a buffer layer is formed on a layer to be etched, the buffer layer is made of a material different from that of a core layer, the buffer layer is etched using the core layer as a mask, a second opening is formed in the buffer layer, and after the second opening is formed, the core layer and a sidewall are removed. After the patterns of the core layer and the side wall are transferred to the buffer layer, the core layer and the side wall are removed, so that the material of the core layer, the material of the side wall and reaction byproducts generated by the material in the core layer forming process can be completely removed, the condition that the material of the core layer, the material of the side wall and the reaction byproducts generated by the material in the core layer forming process are transferred to the layer to be etched to influence the formed semiconductor structure is avoided, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 16 are schematic views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a layer to be etched is provided.
The layer to be etched comprises a substrate 200, and the substrate 200 comprises: a substrate (not shown); a device layer (not shown) on the substrate, the device layer including an isolation structure and a device structure within the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor, a conductive structure, or the like; a conductive layer (not shown) on the device layer, the conductive layer electrically connected to the device structure.
In this embodiment, the substrate is made of silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the layer to be etched further includes: a second stop layer 201 on the substrate 200; a hard mask layer 202 on the second stop layer 201; a third stop layer 203 is located on the hard mask layer 202.
The material of the second stop layer 201 is different from that of the hard mask layer 202; the hard mask layer 202 is made of a material different from that of the third stop layer 203.
The second stop layer 201 is used for etching an etching stop layer of the hard mask layer 202 subsequently; the third stop layer 203 is used for transitioning the hard mask layer 202 and a first stop layer 204 formed on the third stop layer 203, so as to avoid a situation that the stress difference between the first stop layer 204 and the hard mask layer 202 is large, and the bonding force generated by the direct contact between the first stop layer 204 and the hard mask layer 202 is poor.
In the present embodiment, the material of the second stop layer 201 includes silicon oxide; the hard mask layer 202 is made of a material including titanium nitride, titanium oxide, tantalum nitride or tantalum oxide; the material of the third stop layer 203 comprises silicon oxide.
Referring to fig. 4, a first stop layer 204 is formed on the layer to be etched.
The material of the first stop layer 204 is different from the material of the subsequently formed buffer layer, and the material of the first stop layer 204 is different from the material of the subsequently formed core layer.
The first stop layer 204 is used as an etch stop layer for a subsequently formed buffer layer.
In the present embodiment, the material of the first stop layer 204 includes silicon nitride.
With continued reference to fig. 4, a buffer layer 205 is formed on the first stop layer 204.
In this embodiment, the material of the buffer layer 205 includes silicon. The process of forming the buffer layer 205 includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the thickness range of the buffer layer 205 is: 300 to 1000 angstroms.
The buffer layer 205 is used as a mask for continuously etching the layer to be etched after the core layer and the sidewall are subsequently removed, if the thickness of the buffer layer 205 is too thin, the core layer and the sidewall cannot effectively block the damage of the etching process, and if the thickness of the buffer layer 205 is too thick, the aspect ratio of a second opening formed in the buffer layer 205 subsequently is increased, which is not favorable for pattern transfer.
The material of the buffer layer 205 is different from that of a subsequently formed core layer, and the material of the buffer layer 205 is different from that of a subsequently formed side wall, so that the buffer layer 205 can be less damaged by the removing process when the core layer and the side wall are subsequently removed, and the pattern of the semiconductor structure can be continuously transferred from the buffer layer 205.
Referring to fig. 5 and fig. 6, fig. 5 is a schematic cross-sectional view taken along a section line AA1 in fig. 6, fig. 6 is a top view of fig. 5, a core layer 206 is formed on a buffer layer 205, the material of the core layer 206 is different from that of the buffer layer 205, the core layer 206 has a plurality of first openings 207 therein, and the first openings 207 expose a portion of the surface of the buffer layer 205.
The method for forming the first opening 207 includes: forming a core material layer (not shown) on the buffer layer 205; forming a patterned first mask layer (not shown) on the core material layer; and etching the core material layer by using the patterned first mask layer as a mask until the surface of the buffer layer 205 is exposed, so as to form the core layer 206 and a first opening 207 in the core layer 206.
The material of the core layer 206 is different from that of the buffer layer 205, and the material of the core layer 206 is different from that of the subsequently formed side wall. The material of the core layer 206 is different from the material of the buffer layer 205, so that the etching process can stop on the buffer layer 205 when the core material layer is etched.
In the present embodiment, the material of the core layer 206 includes silicon oxide.
Referring to fig. 7 and 8, fig. 7 is a schematic cross-sectional view taken along a section line BB1 in fig. 8, fig. 8 is a top view in fig. 7, a sidewall 208 is formed on a sidewall of the first opening 207, the material of the sidewall 208 is different from that of the core layer 206, and the material of the sidewall 208 is different from that of the buffer layer 205.
The forming method of the side wall 208 includes: forming a side wall material layer (not shown) on the bottom surface and the side wall surface of the first opening 207 and the top surface of the core layer 206; the spacer material layer is etched back until the surface of the core layer 206 and the surface of the buffer layer 205 at the bottom of the first opening 207 are exposed, so as to form the spacer 208.
In this embodiment, the material of the sidewall spacers 208 includes titanium oxide or tantalum oxide.
With continued reference to fig. 7 and 8, after forming the sidewall spacers 208, a sacrificial layer 209 is formed in the first opening 207.
The method for forming the sacrificial layer 209 comprises the following steps: forming a sacrificial material layer (not shown) within the first opening 207 and on the core layer 206; the sacrificial material layer is planarized until the surface of the core layer 206 is exposed, and the sacrificial layer 209 is formed within the first opening 207.
The material of the sacrificial layer 209 is different from that of the core layer 206, the material of the sacrificial layer 209 is different from that of the sidewall 209, and the material of the sacrificial layer 209 is different from that of the buffer layer 205. Therefore, when the sacrificial layer 209 is subsequently removed, the core layer 206, the side walls 209 and the buffer layer 205 can be damaged less by the removal process.
In the present embodiment, the material of the sacrificial layer 209 includes silicon nitride.
Referring to fig. 9 and 10, fig. 9 is a schematic cross-sectional view taken along a sectional line CC1 in fig. 10, fig. 10 is a top view of fig. 9, a filling layer 210 is formed in the sacrificial layer 209 and the core layer 206, and the filling layer 210 is located between the adjacent side walls 208.
In the present embodiment, the filling layers 210 are located in the sacrificial layer 209 and the core layer 206, one filling layer 210 penetrates through the sacrificial layer 209 along the first direction Y parallel to the substrate surface, and one filling layer 210 penetrates through the core layer 206 between the adjacent first openings 207 along the first direction Y.
In other embodiments, the filling layer penetrates the sacrificial layer along a first direction Y parallel to the substrate surface, or alternatively, the filling layer penetrates the core layer between adjacent first openings along the first direction Y.
The method of forming the filler layer 210 in the sacrificial layer 209 includes: forming a patterned mask structure (not shown) on the sacrificial layer 209 and on the core layer 206, the patterned mask structure exposing a portion of the surface of the sacrificial layer 209; etching the sacrificial layer 209 by using the patterned mask structure as a mask, and forming a third opening (not shown) in the sacrificial layer 209, wherein the side wall 208 is exposed at two sides of the third opening; forming a filling material layer (not shown) in the third opening; the filling material layer is planarized until the surface of the sacrificial layer 209 is exposed, and a filling layer 210 is formed in the sacrificial layer 209.
The method of forming the filler layer 210 within the core layer 206 includes: forming a patterned mask structure (not shown) on the sacrificial layer 209 and on the core layer 206, the patterned mask structure exposing a portion of the surface of the core layer 206; etching the core layer 206 by using the patterned mask structure as a mask, forming a third opening (not shown) in the core layer 206, wherein the sidewall 208 is exposed at two sides of the third opening; forming a filling material layer (not shown) in the third opening; the filler material layer is planarized until the surface of the core layer 206 is exposed, forming a filler layer 210 within the core layer 206.
The material of the filling layer 210 is the same as that of the side wall 208, that is, the material of the filling layer 210 is different from that of the sacrificial layer 209, and the material of the filling layer 210 is different from that of the core layer 206. So that the filler layer 210 is less damaged when the sacrificial layer 209 is subsequently removed.
In the present embodiment, the material of the filling layer 210 includes titanium oxide or tantalum oxide.
Referring to fig. 11 and 12, fig. 11 is a schematic cross-sectional view taken along a section line DD1 in fig. 12, and fig. 12 is a top view of fig. 11, after forming the filling layer 210, the sacrificial layer 209 is removed to expose the first opening 207.
The process for removing the sacrificial layer 209 includes a dry etching process or a wet etching process.
The material of the sacrificial layer 209 is different from that of the core layer 206, the material of the sacrificial layer 209 is different from that of the sidewall 209, and the material of the sacrificial layer 209 is different from that of the buffer layer 205. Therefore, when the sacrificial layer 209 is removed, the core layer 206, the side walls 209 and the buffer layer 205 can be damaged less by the removal process.
With continued reference to fig. 11 and fig. 12, after removing the sacrificial layer 209, a portion of the core layer 206 is removed, and a fourth opening 211 is formed in the core layer 206, wherein the fourth opening 211 is located between two adjacent first openings 207 and exposes the sidewall 208 of the sidewall of the first opening 207 and the filling layer 210 in the core layer 206.
The method of removing a portion of the core layer 206 includes: forming a patterned second mask layer (not shown) on the core layer 206, the patterned second mask layer exposing a portion of the surface of the core layer 206; and etching the core layer 206 by using the patterned second mask layer as a mask until the surface of the buffer layer 205 is exposed, and forming a fourth opening 211 in the core layer 206.
The process of etching the core layer 206 includes a dry etching process or a wet etching process.
The material of the core layer 206 is different from that of the buffer layer 205, the material of the core layer 206 is different from that of the side wall 208, and the material of the core layer 206 is different from that of the filling layer 210, so that when the core layer 206 is etched, the etching process can be stopped on the buffer layer 205, and meanwhile, the buffer layer 205, the side wall 208 and the filling layer 210 are less damaged, thereby avoiding affecting the size accuracy of the formed semiconductor structure pattern.
Referring to fig. 13 and 14, fig. 13 is a schematic cross-sectional view taken along a sectional line EE1 in fig. 14, fig. 14 is a top view of fig. 13, after forming the fourth opening 211, etching the buffer layer 205 by using the core layer 206, the sidewall spacers 208 and the filling layer 210 as masks until the surface of the first stop layer 205 is exposed, and forming a second opening 212 in the buffer layer 205.
The process for etching the buffer layer 205 includes a dry etching process, and the dry etching process can form a pattern of a semiconductor structure with good sidewall morphology and high dimensional accuracy, and is beneficial to transfer of subsequent patterns of the semiconductor structure.
Referring to fig. 15 and 16, fig. 15 is a schematic cross-sectional view taken along a sectional line FF1 in fig. 16, and fig. 16 is a top view in fig. 15, after forming the second opening 212, the core layer 206 and the side walls 208 are removed.
In this embodiment, when removing the core layer 206 and the side walls 208, the method further includes: the filling layer 210 is removed.
In this embodiment, the method for removing the core layer 206, the side walls 208 and the filling layer 210 includes a first step of removing the core layer 206 and a second step of removing the side walls 208 and the filling layer 210 after the first step.
The process of removing the core layer 206 includes a dry etching process of which an etching gas includes plasma of nitrogen trifluoride or ammonia gas, or a wet etching process of which an etching liquid includes hydrofluoric acid. The process of removing the core layer 206 has a greater etch rate for the core layer 206 than for the buffer layer 205.
The process for removing the sidewall 208 and the filling layer 210 includes a wet etching process, and an etching solution of the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid. The etching rate of the process for removing the spacers 208 and the filling layer 210 to the spacers 208 and the filling layer 210 is greater than that to the buffer layer 205.
The core layer 206 is made of different materials than the side walls 208 and the filling layers 210, the core layer 206 is removed first, and then the side walls 208 and the filling layers 210 are removed by a wet etching process, so that the condition of etching rate difference caused by the different materials of the core layer 206, the side walls 208 and the filling layers 210 can be overcome, the core layer 206, the side walls 208 and the filling layers 210 can be removed completely, and the residue on the buffer layer 205 can be reduced to the maximum extent.
In another embodiment, the process for removing the core layer, the side wall and the filling layer includes a wet etching process, and an etching solution of the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid. The wet etching process can remove the core layer, the side wall and the filling layer together, so that the process flow can be saved, and the production efficiency can be improved.
After the patterns of the core layer 206, the side wall 208 and the filling layer 210 are transferred to the buffer layer 205, the core layer 206, the side wall 208 and the filling layer 210 are removed, so that the reaction byproducts generated by the material of the core layer 206, the material of the side wall 208 and the material in the process of forming the core layer 206 can be completely removed, the condition that the reaction byproducts generated by the material of the core layer 206, the material of the side wall 208 and the material in the process of forming the core layer 206 are transferred to the layer to be etched to influence the formed semiconductor structure is avoided, the size accuracy of the semiconductor structure can be improved, and the performance of the semiconductor structure is improved.
After removing the core layer 206, the sidewall spacers 208 and the filling layer 210, the buffer layer 205 is used as a mask to etch the layer to be etched.
The method for etching the layer to be etched by taking the buffer layer 205 as a mask comprises the following steps: and etching the first stop layer 204, the third stop layer 203, the hard mask layer 202, the second stop layer 201 and the conductive layer by taking the buffer layer 205 as a mask until the surface of the device layer is exposed.
The process for etching the layer to be etched by using the buffer layer 205 as a mask comprises a dry etching process, and the dry etching process can form a semiconductor structure with good sidewall morphology and high dimensional accuracy, so that the performance of the semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a layer to be etched;
forming a buffer layer on the layer to be etched;
forming a core layer on the buffer layer, wherein the material of the core layer is different from that of the buffer layer, a plurality of first openings are formed in the core layer, and part of the surface of the buffer layer is exposed by the first openings;
forming a side wall on the side wall of the first opening, wherein the material of the side wall is different from that of the core layer, and the material of the side wall is different from that of the buffer layer;
etching the buffer layer by taking the core layer as a mask, and forming a second opening in the buffer layer;
after forming a second opening, removing the core layer and the side walls;
and after removing the core layer and the side wall, etching the layer to be etched by taking the buffer layer as a mask.
2. The method for forming a semiconductor structure according to claim 1, wherein after forming the spacers and before etching the buffer layer using the core layer as a mask, the method further comprises: and forming a filling layer in the sacrificial layer or the core layer, wherein the filling layer is positioned between the adjacent side walls.
3. The method of forming a semiconductor structure of claim 2, wherein the step of forming a filler layer within the sacrificial layer or the core layer comprises: forming a sacrificial layer in the first opening; forming a patterned mask structure on the sacrificial layer and the core layer, wherein the patterned mask structure exposes a part of the surface of the core layer or a part of the surface of the sacrificial layer; etching the sacrificial layer or the core layer by taking the patterned mask structure as a mask, forming a third opening in the sacrificial layer or the core layer, and exposing the side wall at two sides of the third opening; and forming a filling layer in the third openings, wherein the filling layer penetrates through the sacrificial layer along the first direction parallel to the surface of the substrate, or penetrates through the core layer between the adjacent first openings along the first direction parallel to the surface of the substrate.
4. The method of forming a semiconductor structure according to claim 2, wherein after the filling layer is formed, the sacrifice layer is removed; after removing the sacrificial layer, a portion of the core layer is removed, and a fourth opening is formed in the core layer.
5. The method of forming a semiconductor structure of claim 2, wherein the method of forming the second opening further comprises: and etching the buffer layer by taking the core layer, the side wall and the filling layer as masks until the surface of the layer to be etched is exposed, and forming the second opening.
6. The method for forming a semiconductor structure according to claim 2, wherein after forming the second opening, removing the core layer and the side walls, and further comprising: and removing the filling layer.
7. The method for forming a semiconductor structure according to claim 6, wherein the method for removing the core layer, the sidewall spacers and the filling layer comprises a first step and a second step after the first step; the first step is to remove the core layer, the process for removing the core layer comprises a dry etching process or a wet etching process, etching gas of the dry etching process comprises plasma of nitrogen trifluoride and ammonia gas, and etching liquid of the wet etching process comprises hydrofluoric acid; and the second step is to remove the side wall and the filling layer, wherein the process for removing the side wall and the filling layer comprises a wet etching process, and etching liquid of the wet etching process comprises mixed solution of hydrogen peroxide and hydrofluoric acid.
8. The method according to claim 6, wherein the step of removing the core layer, the sidewall spacer and the filling layer comprises a wet etching step, and an etching solution of the wet etching step comprises a mixed solution of hydrogen peroxide and hydrofluoric acid.
9. The method for forming the semiconductor structure according to claim 2, wherein the material of the filling layer is the same as the material of the sidewall.
10. The method according to claim 3, wherein a material of the sacrificial layer is different from a material of the core layer, a material of the sacrificial layer is different from a material of the sidewall, and a material of the sacrificial layer is different from a material of the buffer layer.
11. The method of forming a semiconductor structure of claim 10, wherein a material of the sacrificial layer comprises silicon nitride.
12. The method for forming the semiconductor structure according to claim 1, wherein the material of the sidewall spacers comprises an oxide of metallic titanium or an oxide of metallic tantalum.
13. The method of forming a semiconductor structure of claim 1, wherein the material of the core layer comprises silicon oxide.
14. The method of forming a semiconductor structure of claim 1, wherein a material of the buffer layer comprises silicon.
15. The method of forming a semiconductor structure of claim 1, wherein the buffer layer has a thickness in a range of: 300 to 1000 angstroms.
16. The method of forming a semiconductor structure according to claim 1, further comprising, before forming the buffer layer on the layer to be etched: forming a first stop layer on the layer to be etched; the material of the first stop layer is different from the material of the buffer layer, and the material of the first stop layer is different from the material of the core layer.
17. The method of forming a semiconductor structure of claim 16, wherein the layer to be etched comprises a substrate comprising: a substrate; the device comprises a substrate, a device layer, a first electrode, a second electrode, a third electrode and a fourth electrode, wherein the device layer is positioned on the substrate and comprises an isolation structure and a device structure positioned in the isolation structure, and the device structure comprises a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure and the like; a conductive layer on the device layer, the conductive layer electrically connected to the device structure; and etching the conducting layer by taking the buffer layer as a mask until the surface of the device layer is exposed.
18. The method of forming a semiconductor structure of claim 17, wherein the layer to be etched further comprises: a second stop layer on the substrate; a hard mask layer on the second stop layer; a third stop layer on the hard mask layer; the forming method further includes: and etching the first stop layer, the third stop layer, the hard mask layer, the second stop layer and the conducting layer by taking the buffer layer as a mask until the surface of the device layer is exposed.
19. The method of forming a semiconductor structure of claim 16, wherein a material of the first stop layer comprises silicon nitride.
CN202110091012.XA 2021-01-22 2021-01-22 Method for forming semiconductor structure Pending CN114823486A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117545275A (en) * 2024-01-08 2024-02-09 长鑫新桥存储技术有限公司 Method for manufacturing semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117545275A (en) * 2024-01-08 2024-02-09 长鑫新桥存储技术有限公司 Method for manufacturing semiconductor structure
CN117545275B (en) * 2024-01-08 2024-05-14 长鑫新桥存储技术有限公司 Method for manufacturing semiconductor structure

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