CN106409677B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN106409677B
CN106409677B CN201510459384.8A CN201510459384A CN106409677B CN 106409677 B CN106409677 B CN 106409677B CN 201510459384 A CN201510459384 A CN 201510459384A CN 106409677 B CN106409677 B CN 106409677B
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layer
barrier layer
forming
semiconductor device
dielectric layer
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CN106409677A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a forming method thereof are provided, wherein the forming method of the semiconductor device comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate; forming a gate dielectric layer covering the bottom and the side wall of the groove; forming a first barrier layer covering the gate dielectric layer; carrying out non-crystallizing treatment on the first barrier layer to convert the first barrier layer into a second barrier layer; and forming a metal layer covering the second barrier layer, wherein the surface of the metal layer is flush with the surface of the interlayer dielectric layer. The semiconductor device and the forming method thereof improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; the semiconductor structure comprises a grid structure positioned on the surface of a substrate, a source region positioned in the semiconductor substrate on one side of the grid structure and a drain region positioned in the semiconductor substrate on the other side of the grid structure. The MOS transistor generates a switching signal by regulating a current through a bottom channel of the gate structure by applying a voltage to the gate structure.
With the increasing integration of the MOS transistors, the voltage and current required for the MOS transistors to work are continuously reduced, the speed of switching the transistors is increased, and the requirements on the semiconductor process are greatly increased. Therefore, the industry has sought alternatives to SiO2The High-K Material (High-K Material) is used as a gate dielectric layer to better isolate the gate structure from other parts of the MOS transistor and reduce leakage. Meanwhile, in order to be compatible with a high-K (K is more than 3.9) dielectric constant material, a metal material is adopted to replace the original polycrystalline silicon to be used as a gate electrode layer. The leakage of the MOS transistor of the high-K gate dielectric layer metal gate electrode is further reduced.
However, as feature sizes are further scaled down, MOS transistors formed in the prior art have poor performance.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can improve the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate; forming a gate dielectric layer covering the bottom and the side wall of the groove; forming a first barrier layer covering the gate dielectric layer; carrying out non-crystallizing treatment on the first barrier layer to convert the first barrier layer into a second barrier layer; and forming a metal layer covering the second barrier layer, wherein the surface of the metal layer is flush with the surface of the interlayer dielectric layer.
Optionally, the method further includes: and before the gate dielectric layer is formed, forming an interface layer, wherein the interface layer covers the bottom and the side wall of the groove.
Optionally, the method further includes: forming a work function layer overlying the second barrier layer prior to forming the metal layer.
Optionally, when the semiconductor device is an N-type MOS transistor, the work function layer is made of TiAl; when the semiconductor device is a P-type MOS transistor, the work function layer is made of TaN.
Optionally, the substrate includes a substrate and a fin portion located on a surface of the substrate; the recess exposes a top surface and sidewalls of the fin.
Optionally, the base is a substrate, and the groove exposes a surface of the substrate.
Optionally, the gate dielectric layer is made of a high-K dielectric material.
Optionally, the material of the first barrier layer is TiN or TaN.
Optionally, the amorphization processing method includes: doping first ions in the first barrier layer by adopting a first ion implantation process; and carrying out first annealing treatment on the first barrier layer doped with the first ions so that the first barrier layer is converted into a second barrier layer.
Optionally, the parameters of the first ion implantation process are as follows: the implanted ions are silicon ions, the implantation energy is 0.5 KeV-5 KeV, and the implantation dosage is 1E 15atom/cm2～5E 16atom/cm2The injection angle is 7-20 degrees.
Optionally, the first annealing treatment is spike annealing, and the gas adopted is N2Or Ar, the annealing temperature is 950-1050 ℃.
Optionally, when the first barrier layer is TiN and the first ions are Si ions, the formed second barrier layer is TiSiN.
Optionally, the amorphization processing method includes: forming a silicon layer covering the first barrier layer; carrying out second annealing treatment on the silicon layer and the first barrier layer to enable silicon atoms in the silicon layer to enter the first barrier layer to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer.
Optionally, the process for forming the silicon layer is a low-pressure chemical vapor deposition process, and the specific process parameters are as follows: the gas used is SiH4，SiH4The flow rate of the deposition chamber is 10-60 sccm, the temperature is 350-500 ℃, and the pressure of the deposition chamber is 0.4-2 torr.
Optionally, the thickness of the silicon layer is 40to 100 angstroms.
Optionally, the second annealing treatment is spike annealing, and the gas adopted is N2Or Ar, the annealing temperature is 800-1000 ℃.
Optionally, when the first barrier layer is TiN, the second barrier layer is TiSiN.
Optionally, the thickness of the second barrier layer is 10 to 30 angstroms.
Optionally, the metal layer is W, Al, Ti, Cu, Mo, or Pt.
The present invention also provides a semiconductor device formed by any of the above methods, comprising: a substrate; the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate; the gate dielectric layer covers the bottom and the side wall of the groove; a second barrier layer covering the gate dielectric layer, wherein the second barrier layer has an amorphous structure; and the surface of the metal layer is flush with the surface of the interlayer dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the semiconductor device, the first barrier layer is subjected to non-crystallizing treatment to be converted into the second barrier layer, the second barrier layer has an amorphous structure, so that the blocking effect of the second barrier layer is larger than that of the first barrier layer, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second barrier layer can effectively prevent intermediate products generated by the precursor from entering the gate dielectric layer.
Further, before forming the gate dielectric layer, an interface layer covering the bottom and the side wall of the groove is formed. The interface layer is used as a transition layer between the substrate and the gate dielectric layer, so that the phenomenon that the gate dielectric layer is directly and firmly combined with the substrate is avoided. Meanwhile, the second barrier layer can effectively prevent metal atoms in the metal layer from entering the interface layer, and effectively prevent intermediate products generated by the precursor from entering the interface layer in the process of forming the metal layer.
Further, a work function layer is formed between the second barrier layer and the metal layer. The work function layer is capable of adjusting a threshold voltage of the semiconductor device. Meanwhile, the second barrier layer can effectively prevent metal atoms in the work function layer from entering the gate dielectric layer.
Further, the method for amorphization treatment comprises the following steps: forming a silicon layer covering the first barrier layer; carrying out second annealing treatment on the silicon layer and the first barrier layer to enable silicon atoms in the silicon layer to enter the first barrier layer to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer. The amorphization processing method can enable the first barrier layer to be converted into a second barrier layer; in addition, during the second annealing treatment, the silicon layer can absorb oxygen atoms in the interface layer, so that the equivalent oxide thickness of the interface layer is reduced, and the performance of the semiconductor device is improved.
In the semiconductor device provided by the invention, the second barrier layer has an amorphous structure, so that the barrier effect of the second barrier layer is stronger, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, the second barrier layer can effectively prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.
Drawings
Fig. 1 to 3 are schematic views illustrating a process of forming a semiconductor device according to an embodiment of the present invention;
fig. 4to 13 are schematic views illustrating a process of forming a semiconductor device according to another embodiment of the present invention;
fig. 14 to 18 are schematic views illustrating a process of forming a semiconductor device according to still another embodiment of the present invention.
Detailed Description
As feature sizes shrink further, the performance of semiconductor devices formed in the prior art is poor.
Fig. 1 to 3 are schematic structural diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 1, a base is provided, the base including a substrate 100 and a fin 120 on a surface of the substrate 100; an interlayer dielectric layer 130 is formed on the surface of the substrate, a groove 131 is formed in the interlayer dielectric layer 130, and the groove 131 exposes the top surface and the sidewall of the fin portion 120.
Referring to fig. 2, a gate dielectric layer 140 covering the bottom and sidewalls of the recess 131 (refer to fig. 1) is formed; forming a barrier layer 141 covering the gate dielectric layer 140; and forming a metal layer 142 covering the barrier layer 141, wherein the whole surface of the metal layer 142 is higher than the surface of the interlayer dielectric layer 130.
The barrier layer 141 is made of TiN, and the metal layer 142 is made of W.
Referring to fig. 3, the metal layer 142, the barrier layer 141 and the gate dielectric layer 140 are planarized with the interlayer dielectric layer 130 as a stop layer, so that the metal layer 142, the barrier layer 141 and the gate dielectric layer 140 are flush with the interlayer dielectric layer 130.
The research finds that the reason of poor performance of the semiconductor device formed by the method is as follows:
because the metal layer is formed by adopting the precursor containing fluorine in the process of forming the metal layerBodies, e.g. WF6The precursor generates a fluorine-containing intermediate product, and fluorine atoms in the intermediate product are easy to diffuse into the gate dielectric layer. In addition, the barrier layer is made of TiN, the TiN has a polycrystalline structure, and the barrier effect of the barrier layer is weak, so that fluorine atoms of the intermediate product are easy to diffuse into the gate dielectric layer through a grain boundary in the barrier layer, defects are formed in the gate dielectric layer, and the threshold voltage of the semiconductor device is unstable.
On this basis, another embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate; forming a gate dielectric layer covering the bottom and the side wall of the groove; forming a first barrier layer covering the gate dielectric layer; carrying out non-crystallizing treatment on the first barrier layer to convert the first barrier layer into a second barrier layer; and forming a metal layer covering the second barrier layer, wherein the surface of the metal layer is flush with the surface of the interlayer dielectric layer.
Compared with the embodiment, the first barrier layer is subjected to non-crystallization treatment, so that the first barrier layer is converted into the second barrier layer, the second barrier layer has an amorphous structure, the blocking effect of the second barrier layer is larger than that of the first barrier layer, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second barrier layer can effectively prevent intermediate products generated by the precursor from entering the gate dielectric layer.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4to 13 are schematic views of a process of forming a semiconductor device according to another embodiment of the present invention. In this embodiment, a semiconductor device is exemplified as a fin field effect transistor.
Referring to fig. 4 and 5 in combination, fig. 5 is a cross-sectional view taken along the extending direction of the fin portion (axis a-a 1) in fig. 4, providing a base including a substrate 200 and a fin portion 220 on the surface of the substrate 200; the surface of the fin 220 has a dummy gate structure 230 crossing the fin 220, and the dummy gate structure 230 covers a portion of the top surface and sidewalls of the fin 220.
The substrate 200 provides a process platform for the subsequent formation of semiconductor devices.
The substrate 200 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; the substrate 200 may be a bulk material or may be a composite structure, such as silicon-on-insulator; in this embodiment, the substrate 200 is made of silicon.
The fin portion 220 is formed by: forming a patterned mask layer on the surface of the substrate 200, wherein the patterned mask layer defines the position of the fin portion 220; and etching the substrate 200 with a part of thickness by taking the patterned mask layer as a mask to form the fin part 220.
Since the fin 220 is formed by etching the substrate 200, the material of the fin 220 is the same as that of the substrate 200. In other embodiments, the material of the fin 220 may be different from the material of the substrate 200.
In the present embodiment, three fins 220 are taken as an example, and do not represent the number of fins 220 in the actual process. In an actual process, the specific number of fins 220 may be selected as desired.
The substrate 200 also has an isolation structure 210 on a surface thereof, the surface of the isolation structure 210 is lower than the top surface of the fin 220, and the isolation structure 210 is used for electrically isolating the adjacent fins 220. The material of the isolation structure 210 includes silicon oxide or silicon oxynitride. In this embodiment, the isolation structure 210 is made of silicon oxide.
The dummy gate structure 230 includes a dummy gate dielectric layer 231 crossing the fin portion 220 and a dummy gate electrode layer 232 covering the dummy gate dielectric layer 231. The dummy gate dielectric layer 231 is located on the surface of the isolation structure 210 and covers a portion of the top surface and the sidewall of the fin portion 220. In this embodiment, the dummy gate dielectric layer 231 is made of silicon oxide, and the dummy gate electrode layer 232 is made of polysilicon.
In this embodiment, one dummy gate structure 230 is taken as an example, and does not represent the number of dummy gate structures 230 in an actual process. In an actual process, the number of the dummy gate structures 230 may be selected as needed.
Referring to fig. 6, fig. 6 is a schematic view formed on the basis of fig. 5, and a sidewall spacer 240 covering sidewalls of two sides of the dummy gate structure 230 is formed; forming a source region (not shown) and a drain region (not shown), wherein the source region is located in the sidewall spacers 240 and the fin portion 220 on one side of the dummy gate structure 230, and the drain region is located in the sidewall spacers 240 and the fin portion 220 on the other side of the dummy gate structure 230; after the source region and the drain region are formed, an interlayer dielectric layer 250 is formed on the surface of the substrate, the interlayer dielectric layer 250 covers the side wall of the sidewall spacer 240, and the surface of the interlayer dielectric layer 250 is flush with the surface of the dummy gate structure 230.
The interlayer dielectric layer 250 is made of silicon oxide, silicon oxynitride or silicon oxycarbide.
The steps of forming the interlayer dielectric layer 250 are as follows: forming an interlayer dielectric material layer covering the fin portion 220, the dummy gate structure 230, the isolation structure 210 and the substrate 200, wherein the whole surface of the interlayer dielectric material layer is higher than the top surface of the dummy gate structure 230; the interlayer dielectric material layer is planarized until the top surface of the dummy gate structure 230 is exposed, forming an interlayer dielectric layer 250.
Referring to fig. 7, the dummy gate structure 230 (refer to fig. 6) is removed, and a recess 251 is formed.
And etching to remove the dummy gate structure 230 by using a dry etching process or a wet etching process.
After removing the dummy gate structure 230, the top surface and sidewalls of the fin 220 are exposed, forming a recess 251.
Referring to fig. 8, a gate dielectric layer 260 covering the bottom and sidewalls of the recess 251 (refer to fig. 7) is formed.
The gate dielectric layer 260 serves to isolate the substrate from other material layers that may be subsequently formed on the surface of the gate dielectric layer.
The gate dielectric layer 260 is made of a high-K (K is greater than 3.9) dielectric material, such as HfO2、HfSiO、HfSiON、Al2O3Or ZrO2. In the embodiment of the present invention, the gate dielectric layer 260 is HfO2。
The process for forming the gate dielectric layer 260 is a deposition process, such as an atomic layer deposition process or a plasma chemical vapor deposition process. In this embodiment, the gate dielectric layer 260 is formed by a plasma chemical vapor deposition process.
In this embodiment, an interfacial layer (not shown) may also be formed at the bottom of the gate dielectric layer 260 to serve as a transition layer between the substrate and the gate dielectric layer 260, thereby avoiding the problem of weak direct bonding between the gate dielectric layer 260 and the substrate.
The interface layer is made of SiO2Or SiON. In this embodiment, the interface layer is made of silicon oxide.
The process of forming the interfacial layer is a deposition process such as an atomic layer deposition process, a chemical vapor deposition process, a thermal oxidation process, and a nitridation process. In this embodiment, the interfacial layer is formed by a thermal oxidation process.
With continued reference to fig. 8, a first blocking layer 261 is formed overlying the gate dielectric layer 260.
The first barrier layer 261 functions to: preventing metal atoms in the subsequently formed metal layer from diffusing into the gate dielectric layer 260 and the interface layer; intermediate products generated in the process of forming the metal layer are prevented from entering the interface layer of the gate dielectric layer 260
The material of the first barrier layer 261 is TiN or TaN. In this embodiment, the material of the first barrier layer 261 is TiN.
The thickness of the first barrier layer 261 is 10 to 30 angstroms.
The process of forming the first barrier layer 261 is a deposition process, such as an atomic layer deposition process or a plasma chemical vapor deposition process. In this embodiment, the first blocking layer 261 is formed by a plasma chemical vapor deposition process.
Since the first blocking layer 261 has a polycrystalline structure, an intermediate product is generated in a subsequent metal layer forming process, and the intermediate product is easy to enter the gate dielectric layer 260, for example, when the metal layer is made of W, the intermediate product contains fluorine atoms, and the fluorine atoms are easy to diffuse into the gate dielectric layer 260 through a grain boundary in the first blocking layer 261, so that defects in the gate dielectric layer 260 are increased, and the threshold voltage of the semiconductor device is unstable. That is, the first blocking layer 261 has a weak blocking effect on fluorine atoms in the intermediate product, so that the first blocking layer 261 is converted into a second blocking layer having an amorphous structure by performing an amorphization process on the first blocking layer 261 in this embodiment, and the first blocking layer 261 has a strong blocking effect, so that the intermediate product generated in the process of forming the metal layer can be prevented from entering the gate dielectric layer 260.
In one embodiment, the method of the amorphization process is as follows: doping first ions in the first blocking layer 261 by using a first ion implantation process; the first blocking layer 261 doped with the first ions is subjected to a first annealing process, so that the first blocking layer 261 is converted into a second blocking layer.
The principle of the transformation of the first barrier layer 261 into the second barrier layer is: first ion implantation is employed such that first ions enter the grain boundary gaps of the first barrier layer 261 and the first ions impact atoms in the first barrier layer 261 leaving lattice sites and entering the lattice gaps while leaving vacancies; during the first annealing process, the first ions occupy vacancies and combine with atoms in the first barrier layer 261 to change the composition and crystal orientation of the first barrier layer 261, forming a second barrier layer having an amorphous structure.
In a specific embodiment, the parameters of the first ion implantation process are: the implanted ions are silicon ions, the implantation energy is 0.5 KeV-5 KeV, and the implantation dosage is 1E 15atom/cm2～5E 16atom/cm2The injection angle is 7-20 degrees. The implantation angle is the angle formed with the normal to the substrate 200.
The first annealing treatment is spike annealing, and the adopted gas is N2Or Ar, the annealing temperature is 950-1050 ℃.
It should be noted that the first ions are not limited to silicon ions, and in other embodiments, other ions may be used to convert the first barrier layer 261 into a second barrier layer with an amorphous structure. Preferably, the ion radius of the first ions is larger than the size of the lattice gap of the first blocking layer 261, so that the degree of lattice distortion of the first blocking layer 261 is enhanced after the first ions are implanted into the first blocking layer 261, which is beneficial to forming the amorphized second blocking layer.
In this embodiment, the first blocking layer 261 is made of TiN, the implanted ions used in the first ion implantation are silicon ions, and the formed second blocking layer is made of TiSiN.
In another embodiment, the amorphization process comprises: forming a silicon layer overlying the first barrier layer 261; performing second annealing treatment on the silicon layer and the first barrier layer 261 to make silicon atoms in the silicon layer enter the first barrier layer 261 to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer.
Referring to fig. 9, a silicon layer 262 covering the first barrier layer 261 is formed.
The process of forming the silicon layer 262 is a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process, or a low pressure chemical vapor deposition process.
In this embodiment, the silicon layer 262 is formed by a low-pressure chemical vapor deposition process, and the specific process parameters are as follows: the gas used is SiH4，SiH4The flow rate of the deposition chamber is 10-60 sccm, the temperature is 350-500 ℃, and the pressure of the deposition chamber is 0.4-2 torr.
The thickness of the silicon layer 262 is 40to 100 angstroms.
Referring to fig. 10, the silicon layer 262 and the first barrier layer 261 (refer to fig. 9) are subjected to a second annealing process so that silicon atoms in the silicon layer 262 enter the first barrier layer 261, forming a second barrier layer 263.
The principle of the transformation of the first barrier layer 261 into the second barrier layer 263 is: during the second annealing process, silicon atoms in the silicon layer 262 enter the first barrier layer 261, and the silicon atoms and atoms in the first barrier layer 261 are recombined into bonds, thereby changing the composition and crystal orientation of the first barrier layer 261 to form the second barrier layer 263, and the second barrier layer 263 has an amorphous structure.
The second annealing treatment is spike annealing, and the adopted gas is N2Or Ar, the annealing temperature is 800-1000 ℃.
In this embodiment, the first blocking layer 261 is made of TiN, and the second blocking layer 263 is made of TiSiN.
The first blocking layer 261 is transformed into a second blocking layer 263 after the amorphization process.
The second blocking layer 263 functions as: preventing metal atoms in the subsequently formed metal layer from diffusing into the gate dielectric layer 260 and the interface layer; intermediate products subsequently generated during the formation of the metal layer are blocked from entering the gate dielectric layer 260 and the interface layer.
Because the second blocking layer 263 has an amorphous structure, the blocking effect of the second blocking layer 263 is stronger than that of the first blocking layer 261, and an intermediate product generated in the process of forming a metal layer can be effectively blocked from entering the gate dielectric layer 260 and the interface layer.
The thickness of the second barrier layer 263 is 10 to 30 angstroms.
In this embodiment, the entire thickness of the first barrier layer 261 is subjected to amorphization. In other embodiments, the partial thickness of the first barrier layer 261 may be amorphized, i.e., only the upper portion of the first barrier layer 261 may be amorphized.
Referring to fig. 11, the silicon layer 262 (refer to fig. 10) is removed.
The process of removing the silicon layer 262 is a wet etching process or a dry etching process. In this embodiment, the silicon layer 262 is removed by a wet etching process.
In a specific embodiment, the parameters of the wet etching process used to remove the silicon layer 262 are: the etching solution is tetramethylammonium hydroxide solution, the mass percent concentration of the tetramethylammonium hydroxide is 10-25%, and the etching temperature is 40-90 ℃.
In the case where the semiconductor device has the interface layer, the amorphization process is performed by: forming a silicon layer 262 covering the first barrier layer 261; performing a second annealing process on the silicon layer 262 and the first barrier layer 261 to make silicon atoms in the silicon layer 262 enter the first barrier layer 261 to form a second barrier layer 263; after the second barrier layer 263 is formed, the silicon layer 262 is removed, and during the second annealing process, the silicon layer 262 can absorb oxygen atoms in the interface layer, so that the equivalent oxide thickness of the interface layer is reduced, thereby improving the performance of the semiconductor device.
Referring to fig. 12, a metal layer 264 covering the second barrier layer 263 is formed, and the entire surface of the metal layer 264 is higher than the surface of the interlayer dielectric layer 250.
The metal layer 264 acts as a metal gate of the semiconductor device.
The metal layer 264 is made of W, Al, Ti, Cu, Mo or Pt. In this embodiment, the metal layer 264 is made of W.
The process of forming the metal layer 264 is a chemical vapor deposition process, a physical vapor deposition process, or an electroplating process. In this embodiment, the metal layer 264 is formed by a chemical vapor deposition process.
In one specific embodiment, the process parameters for forming the metal layer 264 are: the gas used is WF6And SiH4，WF6The flow rate of (1) is 300-800 sccm, SiH4The flow rate of the deposition chamber is 30-100 sccm, the temperature is 350-500 ℃, and the pressure of the deposition chamber is 40-130 torr.
In the process of forming the metal layer 264, a precursor for forming the metal layer 264 is a fluorine-containing precursor, the precursor may generate a fluorine-containing intermediate product, and fluorine atoms in the intermediate product may easily diffuse into the gate dielectric layer 260. However, due to the fact that the first blocking layer 261 is subjected to the amorphization treatment, the first blocking layer 261 is converted into the second blocking layer 263 with an amorphous structure, the blocking effect of the second blocking layer 263 is larger than that of the first blocking layer 261, and in the process of forming the metal layer 264, the second blocking layer 263 can effectively block intermediate products generated by precursors from entering the gate dielectric layer 260 and the interface layer, so that the threshold voltage of the semiconductor device is stable.
In this embodiment, before the metal layer 264 is formed, a work function layer (not shown) covering the second blocking layer 263 may be formed, and after the work function layer is formed, the metal layer 264 covering the work function layer may be formed. The work function layer is capable of adjusting a threshold voltage of the semiconductor device.
When the semiconductor device is a P-type fin field effect transistor, the work function layer is made of TaN; when the semiconductor device is an N-type fin field effect transistor, the work function layer is made of TiAl.
The process for forming the work function layer is a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the work function layer is formed by an atomic layer deposition process, and when the work function layer is made of TaN, the precursor reactants are pentakis (dimethylamino) tantalum (PDMAT) and ammonia (NH)3) (ii) a When the work function layer is made of TiAl, the precursor reactants are titanium chloride (TiCl4) and trimethylaluminum (Tri methyl Al, MTA).
When the work function layer is provided in the semiconductor device, the second blocking layer 263 also has a function of blocking metal atoms in the work function layer from entering the gate dielectric layer 260 and the interface layer.
Particularly, when the semiconductor device is an N-type fin field effect transistor and the work function layer is made of TiAl, aluminum atoms in TiAl are easily diffused into other media, and the second blocking layer 263 has an amorphous structure, so that the aluminum atoms can be effectively blocked from entering the gate dielectric layer 260 and the interface layer. The dielectric constant of the gate dielectric layer 260 is stabilized, and the reliability of the interface layer is enhanced.
Referring to fig. 13, the gate dielectric layer 260, the second barrier layer 263 and the metal layer 264 above the surface of the interlayer dielectric layer 250 are removed.
The process of removing the gate dielectric layer 260, the second barrier layer 263 and the metal layer 264 above the surface of the interlayer dielectric layer 250 is a Chemical Mechanical Polishing (CMP) process.
When the semiconductor device further has an interface layer and a work function layer, the interface layer and the work function layer higher than the surface of the interlayer dielectric layer 250 need to be removed.
In this embodiment, the gate dielectric layer 260, the second blocking layer 263 and the metal layer 264 which are higher than the surface of the interlayer dielectric layer 250 are removed in the same step, so that the process steps are effectively saved. In other embodiments of the present invention, the gate dielectric layer 260, the second barrier layer 263 and the metal layer 264 above the surface of the interlayer dielectric layer 250 may be removed in multiple steps, for example, after each layer is formed, the portion above the surface of the interlayer dielectric layer 230 is removed.
Fig. 14 to 18 are diagrams illustrating a method for forming a semiconductor device according to yet another embodiment. In this embodiment, a semiconductor device is described as an example of a planar MOS transistor.
Referring to fig. 14, a substrate 300 is provided as a base, an interlayer dielectric layer 350 is provided on the surface of the base, and a groove 351 penetrating the thickness of the interlayer dielectric layer 350 is formed in the interlayer dielectric layer 350.
In this embodiment, the substrate surface further has a sidewall 340.
Before the interlayer dielectric layer 350 is formed, a dummy gate structure is formed on the surface of the substrate 300, and the sidewall spacers 340 cover sidewalls of the dummy gate structure; then, forming a source region (not shown) and a drain region (not shown), wherein the source region is located in the substrate 300 on one side of the dummy gate structure and the sidewall spacers 340, and the drain region is located in the substrate 300 on the other side of the dummy gate structure and the sidewall spacers 340; after a source region and a drain region are formed, an interlayer dielectric layer 350 is formed, the interlayer dielectric layer 350 covers the side wall of the side wall 340, and the surface of the interlayer dielectric layer 350 is flush with the surface of the dummy gate structure; after the interlayer dielectric layer 350 is formed, the dummy gate structure is removed, and the groove 351 is formed.
Referring to fig. 15, a gate dielectric layer 360 is formed to cover the bottom and sidewalls of the groove 351 (refer to fig. 14); a first blocking layer 361 covering the gate dielectric layer 360 is formed.
Referring to fig. 16, the first barrier layer 361 (see fig. 15) is subjected to amorphization so that the first barrier layer 361 is converted into a second barrier layer 363.
Referring to fig. 17, a metal layer 364 covering the second barrier layer 363 is formed.
The entire surface of the metal layer 364 is higher than the surface of the interlayer dielectric layer 350.
Referring to fig. 18, the gate dielectric layer 360, the second barrier layer 363 and the metal layer 364 above the surface of the interlayer dielectric layer 350 are removed.
The method for forming the substrate 300, the interlayer dielectric layer 350, the groove 351, the gate dielectric layer 360, the first barrier layer 361, the second barrier layer 363 and the metal layer 364 refers to the foregoing embodiments. The method for removing the gate dielectric layer 360, the second barrier layer 363 and the metal layer 364 above the surface of the interlayer dielectric layer 350 is described in the foregoing embodiments and will not be described in detail.
In this embodiment, an interfacial layer may also be formed at the bottom of the gate dielectric layer 360, where the interfacial layer covers the sidewalls and the bottom of the groove 351; in this embodiment, a work function layer may be further formed between the second barrier layer 363 and the metal layer 364.
The method for forming the interfacial layer and the work function is described in the foregoing embodiments and will not be described in detail.
Another embodiment of the present invention provides a semiconductor device including: the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate; the gate dielectric layer covers the bottom and the side wall of the groove; a second barrier layer covering the gate dielectric layer, wherein the second barrier layer has an amorphous structure; and the surface of the metal layer is flush with the surface of the interlayer dielectric layer.
When the semiconductor device is a fin field effect transistor, referring to fig. 7 and 13, the base includes a substrate 200 and a fin 220 on a surface of the substrate 200; the substrate surface has an interlayer dielectric layer 250, and a groove 251 is formed in the interlayer dielectric layer 250, wherein the groove 251 exposes the top surface and the sidewall of the fin portion 220; a gate dielectric layer 260 covering the bottom and the side wall of the groove 251; a second blocking layer 263 covering the gate dielectric layer 260, wherein the second blocking layer 263 has an amorphous structure; and a metal layer 264 covering the second barrier layer 263, wherein the surface of the metal layer 264 is flush with the surface of the interlayer dielectric layer 250.
The method for forming the substrate 200, the fin 220, the interlayer dielectric layer 250, the groove 251, the gate dielectric layer 260, the second barrier layer 263 and the metal layer 264 is described in the foregoing embodiments and will not be described in detail.
When the semiconductor device is a planar MOS transistor, referring to fig. 14 and 18, the substrate is a substrate 300, an interlayer dielectric layer 350 is disposed on a surface of the substrate 300, a groove 351 is disposed in the interlayer dielectric layer 350, and the groove 351 exposes the surface of the substrate 300; the gate dielectric layer 360 covers the bottom and the side wall of the groove 351; a second barrier layer 363 covering the gate dielectric layer 360, wherein the second barrier layer 363 has an amorphous structure; and a metal layer 364 covering the second barrier layer 363, wherein the surface of the metal layer 364 is flush with the surface of the interlayer dielectric layer 350.
The method for forming the substrate 300, the interlayer dielectric layer 350, the groove 351, the gate dielectric layer 360, the second barrier layer 363 and the metal layer 364 refers to the foregoing embodiments and will not be described in detail.
The semiconductor device may further include: an interface layer (not shown) positioned at the bottom of the gate dielectric layer, wherein the interface layer covers the side wall and the bottom of the groove and the interlayer dielectric layer; a work function layer (not shown) between the second barrier layer and the metal layer.
The method for forming the interfacial layer and the work function layer is described in the foregoing embodiments and will not be described in detail.
The second barrier layer has an amorphous structure, so that the barrier effect of the second barrier layer is strong, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, the second barrier layer can effectively prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.
In summary, the technical scheme of the invention has the following advantages:
according to the forming method of the semiconductor device, the first barrier layer is subjected to non-crystallizing treatment to be converted into the second barrier layer, the second barrier layer has an amorphous structure, so that the blocking effect of the second barrier layer is larger than that of the first barrier layer, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second barrier layer can effectively prevent intermediate products generated by the precursor from entering the gate dielectric layer.
Further, before forming the gate dielectric layer, an interface layer covering the bottom and the side wall of the groove is formed. The interface layer is used as a transition layer between the substrate and the gate dielectric layer, so that the phenomenon that the gate dielectric layer is directly and firmly combined with the substrate is avoided. Meanwhile, the second barrier layer can effectively prevent metal atoms in the metal layer from entering the interface layer, and effectively prevent intermediate products generated by the precursor from entering the interface layer in the process of forming the metal layer.
Further, a work function layer is formed between the second barrier layer and the metal layer. The work function layer is capable of adjusting a threshold voltage of the semiconductor device. Meanwhile, the second barrier layer can effectively prevent metal atoms in the work function layer from entering the gate dielectric layer.
Further, the method for amorphization treatment comprises the following steps: forming a silicon layer covering the first barrier layer; carrying out second annealing treatment on the silicon layer and the first barrier layer to enable silicon atoms in the silicon layer to enter the first barrier layer to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer. The amorphization processing method can enable the first barrier layer to be converted into a second barrier layer; in addition, during the second annealing treatment, the silicon layer can absorb oxygen atoms in the interface layer, so that the equivalent oxide thickness of the interface layer is reduced, and the performance of the semiconductor device is improved.
In the semiconductor device provided by the invention, the second barrier layer has an amorphous structure, so that the barrier effect of the second barrier layer is stronger, and the second barrier layer can effectively prevent metal atoms in the metal layer from entering the gate dielectric layer; in addition, the second barrier layer can effectively prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate;
forming an interface layer, wherein the interface layer covers the bottom and the side wall of the groove;
forming a gate dielectric layer covering the interface layer;
forming a first barrier layer covering the gate dielectric layer;
carrying out non-crystallizing treatment on the first barrier layer to convert the first barrier layer into a second barrier layer;
forming a metal layer covering the second barrier layer, wherein the surface of the metal layer is flush with the surface of the interlayer dielectric layer;
the method for the non-crystallizing treatment comprises the following steps: forming a silicon layer covering the first barrier layer; carrying out second annealing treatment on the silicon layer and the first barrier layer to enable silicon atoms in the silicon layer to enter the first barrier layer to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer.
2. The method for forming a semiconductor device according to claim 1, further comprising: forming a work function layer overlying the second barrier layer prior to forming the metal layer.
3. The method for forming a semiconductor device according to claim 2, wherein when the semiconductor device is an N-type MOS transistor, a material of the work function layer is TiAl; when the semiconductor device is a P-type MOS transistor, the work function layer is made of TaN.
4. The method for forming the semiconductor device according to claim 1 or 2, wherein the base comprises a substrate and a fin portion located on the surface of the substrate; the recess exposes a top surface and sidewalls of the fin.
5. The method according to claim 1 or 2, wherein the base is a substrate, and the groove exposes a surface of the substrate.
6. The method for forming the semiconductor device according to claim 1 or 2, wherein the material of the gate dielectric layer is a high-K dielectric material.
7. The method for forming a semiconductor device according to claim 1 or 2, wherein a material of the first barrier layer is TiN or TaN.
8. The method of claim 1, wherein the silicon layer is formed by a low pressure chemical vapor deposition process, and the specific process parameters are as follows: the gas used is SiH4，SiH4The flow rate of the deposition chamber is 10-60 sccm, the temperature is 350-500 ℃, and the pressure of the deposition chamber is 0.4-2 torr.
9. The method for forming a semiconductor device according to claim 1, wherein the silicon layer has a thickness of 40to 100 angstroms.
10. The method of claim 1, wherein the second annealing process is spike annealing and the gas used is N2Or Ar, the annealing temperature is 800-1000 ℃.
11. The method according to claim 1, wherein when the first barrier layer is TiN, the second barrier layer is TiSiN.
12. The method for forming a semiconductor device according to claim 1 or 2, wherein the second barrier layer has a thickness of 10 to 30 angstroms.
13. The method according to claim 1 or 2, wherein the metal layer is W, Al, Ti, Cu, Mo, or Pt.
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