CN108493246A - Semiconductor devices and its production method - Google Patents
Semiconductor devices and its production method Download PDFInfo
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- CN108493246A CN108493246A CN201810134787.9A CN201810134787A CN108493246A CN 108493246 A CN108493246 A CN 108493246A CN 201810134787 A CN201810134787 A CN 201810134787A CN 108493246 A CN108493246 A CN 108493246A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 125000006850 spacer group Chemical group 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims description 11
- -1 germanium alkene Chemical class 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910005543 GaSe Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 241000219289 Silene Species 0.000 claims description 6
- 229910003090 WSe2 Inorganic materials 0.000 claims description 6
- 229910006247 ZrS2 Inorganic materials 0.000 claims description 6
- 229910052918 calcium silicate Inorganic materials 0.000 claims description 6
- 229910052961 molybdenite Inorganic materials 0.000 claims description 6
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 229910002804 graphite Inorganic materials 0.000 claims description 5
- 239000010439 graphite Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004575 stone Substances 0.000 claims description 3
- 150000001336 alkenes Chemical class 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 21
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000004044 response Effects 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 abstract description 5
- 230000005669 field effect Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021389 graphene Inorganic materials 0.000 description 4
- 230000037230 mobility Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
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- 238000002955 isolation Methods 0.000 description 3
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- 150000001345 alkine derivatives Chemical class 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
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- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
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- 239000002090 nanochannel Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1606—Graphene
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
This application provides a kind of semiconductor devices and its production method.The semiconductor devices includes：Substrate；Fin backgate is located on the part surface of substrate；Spacer medium layer is arranged on the surface of substrate and fin backgate；Gate dielectric layer is arranged on the surface of the separate substrate of spacer medium layer；Two-dimensional material layer is arranged on the surface of the separate spacer medium layer of gate dielectric layer；Two electrodes are arranged on the separate gate dielectric layer surface of two-dimensional material layer, and the both sides of fin backgate are respectively set there are one electrode.In the semiconductor devices, and using two-dimensional material layer as conducting channel so that the dead resistance of device is smaller and response speed is very fast；And using fin as backgate, it is formed since fin backgate can shift photoetching technique by side wall, its size is less than the size of general litho pattern, sub-10 nano can be reached, so that the conducting channel in the device is shorter, parasitic capacitance between source and drain is smaller, ensure that device has preferable performance.
Description
Technical field
This application involves semiconductor applications, in particular to a kind of semiconductor devices and its production method.
Background technology
CMOS integrated circuit micro sustainable developments, device architecture is from two-dimension plane structure (2D planar) to three-dimensional fin
Formula field-effect transistor (3D Fin Field Effect Transisitor, abbreviation 3D Fin FET), then arrive three-dimensional horizontal junction
Ring gate nano line field-effect transistor (the 3D Lateral Gate-All-Around Nanowire Field Effect of structure
Transisitor abbreviation 3D Lateral NW FET) and three-dimensional vertical structure ring gate nano line field-effect transistor (3D
Vertical Gate-All-Around Nanowire Field Effect Transisitor, abbreviation 3D Vertical NW
FET or vertical nanowire transistor), and arrive the channel device of tow -dimensions atom material (2DM).
Two-dimensional material has many advantages, including：Intrinsic effective mobility is high, and device can be improved from physical mechanism
Performance and eigenfrequency；The concentration of carrier is big, is more than 5E12cm-2, thus can be sufficiently conducting, and reduce dead resistance；It
Right two-dimensional structure has very low surface roughness, and then can inhibit mobil-ity degradation；With suitable band gap and band edge, from
And the intrinsic channel leakage of device is reduced, make CMOS scale circuits；Intrinsic surface thereby reduces surface current-carrying without dangling bonds
Son scattering and grid interfacial state, produce the field-effect gated device of high quality；Structure is ultra-thin, it can be achieved that three-dimensional multi-gate structure control
Nano-channel short-channel effect, and then obtain the structure of strong grid-control.
2DM devices are divided into two major classes：Backgate device and top-gated device.They usually have longer channel length, grid
There are larger parasitic capacitances between source and drain, and the production method of the two and the CMOS technology of mainstream are incompatible.
Invention content
The main purpose of the application is to provide a kind of semiconductor devices and its production method, to solve in the prior art
There are problems that larger parasitic capacitance between the grid and source and drain of 2DM devices.
To achieve the goals above, according to the one side of the application, a kind of semiconductor devices is provided, the semiconductor device
Part includes：Substrate；Fin backgate is located on the part surface of above-mentioned substrate；Spacer medium layer, setting above-mentioned substrate and on
On the surface for stating fin backgate；Gate dielectric layer is arranged on the surface far from above-mentioned substrate of above-mentioned spacer medium layer；Two-dimentional material
The bed of material is arranged on the surface far from above-mentioned spacer medium layer of above-mentioned gate dielectric layer；Two electrodes, setting is in above-mentioned two-dimentional material
The bed of material far from above-mentioned gate dielectric layer surface, and the both sides of above-mentioned fin backgate are respectively set that there are one above-mentioned electrodes.
Further, the separate above-mentioned lining on the surface and above-mentioned fin backgate far from above-mentioned substrate of above-mentioned spacer medium layer
The flush at bottom.
Further, the material of above-mentioned two-dimensional material layer is selected from graphene, silene, germanium alkene, graphite alkene, black phosphorus, MoS2、
WS2、ZrS2、SnS2、PtSe2, InSe, h-BN, GaSe and WSe2In it is one or more.
Further, above-mentioned fin backgate is nano level fin backgate.
Further, above-mentioned substrate is structure as a whole with above-mentioned fin backgate, and the material of preferably above-mentioned integral structure is silicon.
According to the another aspect of the application, a kind of production method of semiconductor devices is provided, which includes：Step
Rapid S1, provides substrate；Step S2, the etching removal above-mentioned substrate in part, forms substrate and the fin on above-mentioned substrate surface
Piece backgate；Step S3 is sequentially stacked setting spacer medium layer, grid on above-mentioned substrate and the exposed surface of above-mentioned fin backgate
Dielectric layer and two-dimensional material layer；Step S4 on the separate above-mentioned gate dielectric layer surface of above-mentioned two-dimensional material layer and is corresponded to
An electrode is respectively set in the both sides for stating fin backgate.
Further, the step of above-mentioned spacer medium layer is set on above-mentioned substrate and the exposed surface of above-mentioned fin backgate
Suddenly include：Setting spacer medium material is sequentially stacked on above-mentioned substrate and the exposed surface of above-mentioned fin backgate；To above-mentioned
Spacer medium material is planarized, and above-mentioned spacer medium layer, the surface far from above-mentioned substrate of above-mentioned spacer medium layer are formed
With the flush far from above-mentioned substrate of above-mentioned fin backgate.
Further, the material of above-mentioned two-dimensional material layer is selected from graphene, silene, germanium alkene, graphite alkene, black phosphorus, MoS2、
WS2、ZrS2、SnS2、PtSe2, InSe, h-BN, GaSe and WSe2In it is one or more.
Further, above-mentioned fin backgate is nano level fin backgate.
Further, above-mentioned steps S4 includes：It is arranged on the separate above-mentioned gate dielectric layer surface of above-mentioned two-dimensional material layer
Metal layer；The etching removal above-mentioned metal layer in part, forms the above-mentioned electrode at two intervals.
Using the technical solution of the application, in the semiconductor devices, using fin as backgate, and two-dimensional material layer is used
As conducting channel so that the dead resistance of device is smaller and response speed is very fast；And since fin backgate can be by side wall
Transfer photoetching technique is formed, and size is less than the size of general litho pattern, can reach sub-10 nano, so that the device
Conducting channel in part is shorter so that the parasitic capacitance between source and drain is smaller, ensure that device has preferable performance.
Description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 to Fig. 4 shows the structural schematic diagram in the manufacturing process of the embodiment of the semiconductor devices according to the application.
Wherein, above-mentioned attached drawing includes the following drawings label：
10, substrate；20, fin backgate；30, spacer medium layer；40, gate dielectric layer；50, two-dimensional material layer；60, electrode.
Specific implementation mode
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is also intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.
It should be understood that when element (such as layer, film, region or substrate) is described as in another element "upper", this yuan
Part can be directly on another element, or intermediary element also may be present.Moreover, in specification and following claims
In, when description has element " connected " to another element, which " can be directly connected to " to another element, or pass through third
Element " electrical connection " is to another element.
As background technology is introduced, there are larger parasitisms between the grid and source and drain of 2DM devices in the prior art
The problem of capacitance, in order to solve technical problem as above, present applicant proposes a kind of semiconductor devices and its production method.
In a kind of typical embodiment of the application, a kind of semiconductor devices is provided, as shown in figure 4, the semiconductor
Device includes：Substrate 10, fin backgate 20, spacer medium layer 30, gate dielectric layer 40, two-dimensional material layer 50 and two electrodes
60, wherein fin backgate 20 is located on the part surface of above-mentioned substrate 10；The setting of spacer medium layer 30 in above-mentioned substrate 10 and
On the surface of fin backgate 20；Gate dielectric layer 40 is arranged on the surface far from above-mentioned substrate 10 of above-mentioned spacer medium layer 30；
Two-dimensional material layer 50 is arranged on the surface far from above-mentioned spacer medium layer 30 of above-mentioned gate dielectric layer 40；Two electrodes 60 are arranged
On separate 40 surface of above-mentioned gate dielectric layer of above-mentioned two-dimensional material layer 50, and the both sides of above-mentioned fin backgate 20 are respectively arranged with
One above-mentioned electrode 60.
In above-mentioned semiconductor devices, apply different biass in backgate, by the electric field of gate dielectric layer, incudes different loads
Flow sub- electrons and holes etc. so that two-dimensional semiconductor materials band is bent.Apply the bias of suitable size in source-drain area so that lead
Electric raceway groove conducting or pinch off, and then realize the Push And Release of device, and then realize that backgate controls the switch of the device.
In above-mentioned semiconductor devices, using fin as backgate, and using two-dimensional material layer as conducting channel so that
The dead resistance of device is smaller and response speed is very fast；And it is formed since fin backgate can shift photoetching technique by side wall,
Its size be less than general litho pattern size, sub-10 nano can be reached so that the conducting channel in the device compared with
It is short so that the parasitic capacitance between source and drain is smaller.It ensure that device has preferable performance.
In a kind of embodiment of the application, the surface of the separate above-mentioned substrate 10 of above-mentioned spacer medium layer 30 and above-mentioned fin
The flush far from above-mentioned substrate 10 of backgate 20.Backgate is enabled to be in contact with gate dielectric layer in this way, by backgate
Conducting and the pinch off of conducting channel can preferably be controlled by applying voltage.Also, the spacer medium layer being arranged in this way can be into one
Step reduces the leakage current of device and inhibits the generation of parasitic components.
Certainly, the set-up mode that the above-mentioned spacer medium layer in the application is not limited to, in the unshowned reality of the application
It applies in example, the surface of the separate substrate of above-mentioned spacer medium layer can be above the table far from above-mentioned substrate of above-mentioned fin backgate
Face, alternatively, may also be below the surface far from above-mentioned substrate of above-mentioned fin backgate.
The two-dimensional material layer of the application can be the two-dimensional material layer that any available two-dimensional material is formed in the prior art,
Those skilled in the art can form the two-dimensional material layer of the application according to actual conditions selection suitable material.
In order to further ensure the carrier in conducting channel has higher mobility, so that device is with higher
Response speed, in a kind of embodiment of the application, the material of above-mentioned two-dimensional material layer 50 is selected from graphene, silene, germanium alkene, stone
Black alkynes, black phosphorus, MoS2、WS2、ZrS2、SnS2、PtSe2, InSe, h-BN (hexagonal boron nitride), GaSe and WSe2In one kind or more
Kind.
In order to enable the semiconductor devices meets the needs of integrated circuit small-medium size, high integration, one kind of the application
In embodiment, above-mentioned fin backgate 20 is nano level fin backgate.
In a kind of embodiment of the application, above-mentioned substrate 10 is structure as a whole with above-mentioned fin backgate 20, i.e., above-mentioned substrate
10 and above-mentioned fin backgate 20 are not what two material layers were formed, but were formed by a material layer, and this avoid more
Secondary extension ensure that the interface quality of substrate and backgate is preferable.
Above-mentioned integral structure can select any available material in the prior art to be formed, and those skilled in the art can
To select suitable material to form above-mentioned integral structure according to actual conditions, such as can be Si, Ge, germanium silicon, strained silicon, indigo plant
Jewel, silicon carbide, gallium nitride, GaAs, zinc oxide, diamond, aluminium nitride, metal or metalloid etc..
In order to simplify technique, and it is compatible with the prevailing technology of existing COMS, and the performance of device, the application are improved simultaneously
A kind of embodiment in, the material of above-mentioned integral structure is silicon.
In the typical embodiment of another kind of the application, a kind of production method of semiconductor devices, the making are provided
Method includes：Step S1, provides substrate；Step S2, the etching removal above-mentioned substrate in part form substrate 10 and are located at above-mentioned lining
Fin backgate 20 on 10 surface of bottom, as shown in Figure 1；Step S3, in above-mentioned substrate 10 and the exposed surface of fin backgate 20
On be sequentially stacked setting spacer medium layer 30, gate dielectric layer 40 and two-dimensional material layer 50, sequentially form the structure of Fig. 3 and Fig. 4；
Step S4, in above-mentioned two-dimensional material layer 50 far from 40 surface of the above-mentioned gate dielectric layer and both sides of corresponding above-mentioned fin backgate 20
An electrode 60 is respectively set, as shown in Figure 4.
In above-mentioned production method, direct etching forms fin backgate, and the forming process of substrate and fin backgate is without more
Secondary epitaxy technique so that the interface quality between fin backgate and substrate is preferable；Also, in the production method, noted without source and drain
Enter to form source region and drain region, avoids influence of the forming process in source region and drain region to conducting channel.In addition, the manufacture craft is simple
It is single, it is compatible with the prevailing technology of COMS.
And the above-mentioned prepared semiconductor devices of production method, using two-dimensional material layer as conducting channel so that
The dead resistance of device is smaller and response speed is very fast；Using fin as backgate, since fin backgate can be shifted by side wall
Photoetching technique is formed, and size is less than the size of general litho pattern, can reach sub-10 nano, so that in the device
Conducting channel it is shorter so that the parasitic capacitance between source and drain is smaller.It ensure that device has preferable performance.
In order to form the spacer medium layer of surfacing, and make the surface far from above-mentioned substrate 10 of spacer medium layer
With the flush far from above-mentioned substrate 10 of above-mentioned fin backgate 20, further decreases the leakage current of device and inhibit parasitic device
The generation of part in a kind of embodiment of the application, is arranged above-mentioned on above-mentioned substrate 10 and the exposed surface of fin backgate 20
The step of spacer medium layer 30 includes：Setting isolation is sequentially stacked on above-mentioned substrate 10 and the exposed surface of fin backgate 20
Dielectric material；Above-mentioned spacer medium material is planarized, above-mentioned spacer medium layer 30 shown in Fig. 2 is formed, it specifically can be with
The flatening process is implemented using chemical mechanical polishing method, the surface far from above-mentioned substrate 10 of above-mentioned spacer medium layer 30 with it is upper
State the flush far from above-mentioned substrate 10 of fin backgate 20.
The two-dimensional material layer of the application can be the two-dimensional material layer that any available two-dimensional material is formed in the prior art,
Those skilled in the art can form the two-dimensional material layer of the application according to actual conditions selection suitable material.
In order to further ensure the carrier in conducting channel has higher mobility, so that device is with higher
Response speed, in a kind of embodiment of the application, the material of above-mentioned two-dimensional material layer 50 is selected from graphene, silene, germanium alkene, stone
Black alkynes, black phosphorus, MoS2、WS2、ZrS2、SnS2、PtSe2, InSe, h-BN, GaSe and WSe2In it is one or more.
In order to enable the semiconductor devices meets the needs of integrated circuit small-medium size, high integration, one kind of the application
In embodiment, above-mentioned fin backgate 20 is nano level fin backgate.
Any feasible method in the prior art, people in the art may be used in the forming process of the electrode of the application
Member can select suitable method to form electrode according to actual conditions.
In a kind of specific embodiment, above-mentioned steps S4 includes：In above-mentioned two-dimensional material layer 50 far from above-mentioned gate medium
Metal layer is arranged on 40 surface in layer；The etching removal above-mentioned metal layer in part, forms the above-mentioned electrode 60 at two intervals.
The material of the separation layer of the application can be any material for isolation in existing semiconductor technology, this field skill
Art personnel can select suitable material according to actual conditions.
In order to further ensure that the isolation effect of separation layer, in a kind of embodiment of the application, the material of above-mentioned separation layer
Selected from SiO2And/or Si3N4。
The material of the gate dielectric layer of the application may include silica, silicon oxynitride and/or hafnium, this field skill
Art personnel can select suitable material according to actual conditions.
In order to enable the material of gate dielectric layer has higher dielectric constant, and then backgate is preferably isolated and is partly led with two dimension
Body material layer, in a kind of embodiment of the application, the material of above-mentioned gate dielectric layer includes hafnium, and above-mentioned hafnium is selected from
HfO2、HfSiO、HfSiON、HfLaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2With it is one or more in LaAlO.
Etching process in the application can select suitable lithographic method according to actual conditions, can be dry etching,
It can be wet etching, be specifically as follows RIE etchings or ICP etchings etc., can also be that a variety of lithographic methods are used in combination
Complete some etch step.
It can be seen from the above description that the application the above embodiments realize following technique effect：
1), in the semiconductor devices of the application, using fin as backgate, and using two-dimensional material layer as conductive ditch
Road so that the dead resistance of device is smaller and response speed is very fast；And since fin backgate can shift photoetching skill by side wall
Art is formed, and size is less than the size of general litho pattern, can reach sub-10 nano, so that the conduction in the device
Raceway groove is shorter so that the parasitic capacitance between source and drain is smaller.It ensure that device has preferable performance.
2), the production method of the semiconductor devices of the application, direct etching form fin backgate, substrate and fin backgate
Forming process is not necessarily to multiple epitaxy technique so that the interface quality between fin backgate and substrate is preferable；Also, the production method
In, it injects to form source region and drain region without source and drain, avoids influence of the forming process in source region and drain region to conducting channel.Separately
Outside, the manufacture craft is simple, compatible with the prevailing technology of COMS.
The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field
For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes：
Substrate (10)；
Fin backgate (20) is located on the part surface of the substrate (10)；
Spacer medium layer (30) is arranged on the surface of the substrate (10) and the fin backgate (20)；
Gate dielectric layer (40) is arranged on the surface far from the substrate (10) of the spacer medium layer (30)；
Two-dimensional material layer (50) is arranged on the surface far from the spacer medium layer (30) of the gate dielectric layer (40)；With
And
Two electrodes (60) are arranged on the separate gate dielectric layer (40) surface of the two-dimensional material layer (50), and described
The both sides of fin backgate (20) are respectively set there are one the electrode (60).
2. semiconductor devices according to claim 1, which is characterized in that the separate lining of the spacer medium layer (30)
The flush far from the substrate (10) on the surface at bottom (10) and the fin backgate (20).
3. semiconductor devices according to claim 1, which is characterized in that the material of the two-dimensional material layer (50) is selected from stone
Black alkene, silene, germanium alkene, graphite alkene, black phosphorus, MoS2、WS2、ZrS2、SnS2、PtSe2, InSe, h-BN, GaSe and WSe2In one
Kind is a variety of.
4. semiconductor devices according to claim 1, which is characterized in that the fin backgate (20) is nano level fin
Backgate.
5. semiconductor devices according to claim 1, which is characterized in that the substrate (10) and the fin backgate (20)
It is structure as a whole, the material of the preferably described integral structure is silicon.
6. a kind of production method of semiconductor devices, which is characterized in that the production method includes：
Step S1, provides substrate；
Step S2, the etching removal part substrate, forms substrate (10) and the fin on the substrate (10) surface
Backgate (20)；
Step S3 is sequentially stacked setting spacer medium on the substrate (10) and the exposed surface of the fin backgate (20)
Layer (30), gate dielectric layer (40) and two-dimensional material layer (50)；And
Step S4 on the separate gate dielectric layer (40) surface of the two-dimensional material layer (50) and corresponds to the fin backgate
(20) electrode (60) is respectively set in both sides.
7. production method according to claim 6, which is characterized in that in the substrate (10) and the fin backgate
(20) the step of spacer medium layer (30) are arranged on exposed surface include：
Setting spacer medium material is sequentially stacked on the substrate (10) and the exposed surface of the fin backgate (20)；With
And
The spacer medium material is planarized, the spacer medium layer (30) is formed, the spacer medium layer (30)
The flush far from the substrate (10) on surface and the fin backgate (20) far from the substrate (10).
8. production method according to claim 6, which is characterized in that the material of the two-dimensional material layer (50) is selected from graphite
Alkene, silene, germanium alkene, graphite alkene, black phosphorus, MoS2、WS2、ZrS2、SnS2、PtSe2, InSe, h-BN, GaSe and WSe2In one kind
Or it is a variety of.
9. production method according to claim 6, which is characterized in that the fin backgate (20) is carried on the back for nano level fin
Grid.
10. production method according to claim 6, which is characterized in that the step S4 includes：
Metal layer is set on the separate gate dielectric layer (40) surface of the two-dimensional material layer (50)；And
The etching removal part metal layer, forms the electrode (60) at two intervals.
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Application publication date: 20180904 |