CN107039271B - Transistor and forming method thereof - Google Patents

Transistor and forming method thereof Download PDF

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CN107039271B
CN107039271B CN201610079377.XA CN201610079377A CN107039271B CN 107039271 B CN107039271 B CN 107039271B CN 201610079377 A CN201610079377 A CN 201610079377A CN 107039271 B CN107039271 B CN 107039271B
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material layer
diffusion barrier
transition
groove
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CN107039271A (en
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徐建华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a transistor, comprising: providing a semiconductor substrate, wherein a dielectric layer and a groove penetrating through the dielectric layer are formed on the surface of the semiconductor substrate, and active drain electrodes are formed in the semiconductor substrate on two sides of the groove; forming an interface layer on the bottom surface of the groove; forming a gate dielectric material layer on the interface layer, the side wall of the groove and the surface of the dielectric layer; forming a cap material layer on the gate dielectric material layer; forming a work function material layer on the cap material layer; forming a diffusion barrier material layer on the work function material layer; forming a transition material layer on the diffusion barrier material layer, wherein the transition material layer has diffusion barrier capability and the resistance of the transition material layer is smaller than that of the diffusion barrier material layer; forming a gate material layer which is filled in the groove on the transition material layer; and carrying out planarization treatment by taking the dielectric layer as a stop layer to form a gate structure positioned in the groove. The method is beneficial to improving the performance of the formed transistor.

Description

Transistor and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a transistor and a method for forming the same.
Background
With the continuous improvement of the integration level of a semiconductor device and the reduction of technical nodes, the traditional gate dielectric layer is continuously thinned, the leakage amount of a transistor is increased, and the problems of power consumption waste and the like of the semiconductor device are caused. To solve the above problems, the prior art provides a solution to replace the polysilicon gate with a metal gate. The gate last process is one of the main processes for forming a high-K metal gate transistor.
The existing method for forming a high-K metal gate transistor by adopting a gate-last process comprises the following steps: providing a semiconductor substrate, wherein a dummy gate structure and an interlayer dielectric layer which is positioned on the semiconductor substrate and covers the dummy gate structure are formed on the semiconductor substrate, and the surface of the interlayer dielectric layer is flush with the surface of the dummy gate structure; removing the pseudo gate structure to form a groove; and sequentially forming a metal gate structure in the groove.
Please refer to fig. 1, which is a schematic diagram of a metal gate structure in the prior art.
The metal gate structure includes: the semiconductor device comprises an interface layer 10 positioned at the bottom of a groove (not shown in the figure), a gate dielectric layer 20 positioned on the interface layer 10 and the surface of the side wall of the groove, a capping layer 30 positioned on the surface of the gate dielectric layer, a work function layer 40 positioned on the surface of the capping layer, a diffusion barrier layer 50 positioned on the surface of the work function layer 40, and a gate layer 60 positioned on the surface of the diffusion barrier layer 50 and filling the groove.
The diffusion barrier layer 50 is used to block reactive gas atoms or ions from diffusing into the work function layer 40 during the formation process of the gate layer 60, and simultaneously block atoms in the work function layer 40 from diffusing into the gate layer 60. The thickness of the diffusion barrier layer 50 often has a large influence on the threshold voltage of the NMOS transistor, and if the blocking effect of the diffusion barrier layer is poor, the threshold voltage of the NMOS transistor is obviously increased, which affects the performance of the NMOS transistor.
Therefore, in the prior art, it is generally formed to be thick (larger than)
Figure BDA0000921969250000011
) To improve the diffusion barrier against diffusion. However, the increased thickness of the diffusion barrier layer may result in increased resistance of the metal gate and increased difficulty in depositing the gate layer, which may affect the performance of the transistor formed.
Disclosure of Invention
The invention provides a transistor and a forming method thereof, which can improve the performance of the formed transistor.
In order to solve the above problems, the present invention provides a method for forming a transistor, including: providing a semiconductor substrate, wherein a dielectric layer and a groove penetrating through the dielectric layer are formed on the surface of the semiconductor substrate, and active drain electrodes are formed in the semiconductor substrate on two sides of the groove; forming an interface layer on the bottom surface of the groove; forming a gate dielectric material layer on the interface layer, the side wall of the groove and the surface of the dielectric layer; forming a cap material layer on the gate dielectric material layer; forming a work function material layer on the cap material layer; forming a diffusion barrier material layer on the work function material layer; forming a transition material layer on the diffusion barrier material layer, wherein the transition material layer has diffusion barrier capability and the resistance of the transition material layer is smaller than that of the diffusion barrier material layer; forming a gate material layer which is filled in the groove on the transition material layer; and with the dielectric layer as a stop layer, carrying out planarization treatment to form a gate structure positioned in the groove, wherein the gate structure comprises an interface layer positioned on the bottom surface of the groove, a gate dielectric layer positioned on the surface of the interface layer and the surface of the side wall of the groove, a cap layer positioned on the surface of the gate dielectric layer, a work function layer positioned on the surface of the cap layer, a diffusion barrier layer positioned on the surface of the work function layer, a transition layer positioned on the surface of the diffusion barrier layer and a gate layer positioned on the surface of the transition layer.
Optionally, the material of the diffusion barrier material layer is TiN or TiSiN.
Optionally, the thickness of the diffusion barrier material layer is
Figure BDA0000921969250000021
Optionally, the diffusion barrier material layer is formed by an atomic layer deposition process.
Optionally, the diffusion barrier capability of the transition material layer is greater than the diffusion barrier capability of the diffusion barrier material layer.
Optionally, the material of the transition material layer is tungsten carbide or tungsten carbonitride.
Optionally, the thickness of the transition material layer is
Figure BDA0000921969250000022
Optionally, the transition material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the forming method of the transition material layer includes: by adopting W (CO)6And H2As a reactant, W (CO)6The flow rate of (A) is 0.1 g/min-0.5 g/min, H2The flow rate of the catalyst is 5000sccm to 10000sccm, the temperature is 400 ℃ to 450 ℃, and the pressure is 2Torr～10Torr。
Optionally, the material of the gate material layer is W.
Optionally, the gate material layer is formed by a chemical vapor deposition process.
Optionally, the chemical vapor deposition process employs WF6And H2As reactant, WF6The flow rate of (A) is 250sccm to 350sccm, H2The flow rate of the catalyst is 5000sccm to 10000sccm, the pressure is 30Torr to 50Torr, and the temperature is 375 ℃ to 425 ℃.
Optionally, the capping material layer is made of TiN, TaN or TiSiN, and the thickness of the capping material layer is 1 nm-3 nm.
Optionally, an oxidation process is used to form the interface layer, the interface layer is made of silicon oxide, and the thickness of the interface layer is 1nm to 2 nm.
Optionally, the work function material layer is made of TiAl, TiAlC or TaAlC.
In order to solve the above problem, the present invention further provides a transistor formed by the above method, including: the semiconductor substrate is provided with a dielectric layer and a groove penetrating through the dielectric layer on the surface, and active drain electrodes are formed in the semiconductor substrate on two sides of the groove; an interfacial layer on a bottom surface of the groove; the gate dielectric layer is positioned on the surface of the interface layer and the surface of the side wall of the groove; the cap layer is positioned on the surface of the gate dielectric layer; the work function layer is positioned on the surface of the cap layer; a diffusion barrier layer on the surface of the work function layer; the transition layer is positioned on the surface of the diffusion barrier layer, the transition layer has diffusion barrier capability, and the resistance of the transition layer is smaller than that of the diffusion barrier layer; and the gate layer is positioned on the surface of the transition layer and is filled in the groove.
Optionally, the diffusion barrier layer is made of TiN or TiSiN.
Optionally, the thickness of the diffusion barrier layer is
Figure BDA0000921969250000031
Optionally, the diffusion barrier capability of the transition layer is greater than the diffusion barrier capability of the diffusion barrier layer.
Optionally, the transition layer is made of tungsten carbide or tungsten carbonitride and has a thickness of
Figure BDA0000921969250000032
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, after the diffusion barrier material layer is formed on the surface of the work function material layer, the transition material layer is formed on the surface of the diffusion barrier material layer, and then the grid material layer is formed on the surface of the transition material layer. The transition material layer has a diffusion barrier capability and the transition material layer has a resistance less than the diffusion barrier material layer resistance. The diffusion barrier material layer and the diffusion barrier material layer together block ion diffusion between the work function material layer and the formed gate material layer in the subsequent forming process and between the formed gate material layers. The resistance of the transition material layer is smaller than that of the diffusion barrier material layer, compared with the existing method that a thicker diffusion barrier material layer is adopted to block the ion diffusion between the work function material layer and the subsequently formed grid material layer, the resistance of the composite layer formed by the diffusion barrier material layer and the transition material layer is lower, and the resistance of the finally formed grid is reduced on the premise of not reducing the diffusion barrier effect, so that the performance of the formed transistor is improved.
Furthermore, the transition material layer is made of tungsten carbide or tungsten carbonitride, and can be used as a nucleation layer in the deposition process of the gate material layer, so that the bulk deposition stage can be directly carried out through WF6And H2The reaction forms a bulk W as a layer of gate material. As the forming nucleus layer is not required to be additionally formed, the space to be filled in the groove is enlarged, the deposition process window for forming the grid material layer is enlarged, and the improvement of the deposition quality of the grid material layer is facilitated.
Drawings
FIG. 1 is a schematic diagram of a prior art metal gate structure;
fig. 2to 7 are schematic structural diagrams of a process of forming a transistor according to an embodiment of the present invention.
Detailed Description
As described in the background art, the conventional NMOS transistor has a thicker diffusion barrier layer, which increases the resistance of the metal gate, increases the deposition difficulty of the gate layer, and affects the performance of the formed NMOS transistor.
In the embodiment of the invention, the diffusion barrier layer with smaller thickness is formed, the transition layer is formed on the surface of the diffusion barrier layer, the transition material layer has the diffusion barrier function, and the resistance is smaller than that of the diffusion barrier layer, so that the resistance of the metal gate can be reduced, and the performance of the formed transistor can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, a semiconductor substrate 100 is provided, a dielectric layer 200 and a groove 201 penetrating through the dielectric layer 200 are formed on a surface of the semiconductor substrate 100, and an active drain 101 is formed in the semiconductor substrate 100 on two sides of the groove 201.
The material of the semiconductor substrate 100 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., and the semiconductor substrate 100 may be a bulk material or a composite structure such as silicon-on-insulator. A person skilled in the art may select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100, and therefore the type of the semiconductor substrate 100 should not limit the scope of the present invention.
The method for forming the dielectric layer 200, the groove 201 and the source drain 101 on the surface of the semiconductor substrate 100 comprises the following steps: providing a semiconductor substrate 100; forming a pseudo gate structure on the surface of the semiconductor substrate 100; forming source and drain electrodes 101 in the semiconductor substrate 100 on two sides of the pseudo gate structure; forming a dielectric layer 200 on the surface of the semiconductor substrate 100, wherein the surface of the dielectric layer 200 is flush with the surface of the pseudo gate structure; and removing the pseudo gate structure to form a groove 201 penetrating through the dielectric layer 200. The dielectric layer 200 is made of silicon oxide.
In this embodiment, the transistor to be formed is an N-type fin field effect transistor, the semiconductor substrate 100 includes a bulk silicon substrate and a fin portion located on the surface of the bulk silicon substrate, and the dummy gate structure crosses the fin portion and covers a part of the top and the sidewall of the fin portion, so that the formed groove 201 exposes the bottom and the sidewall surface of a part of the fin portion. FIG. 2 is a cross-sectional view along the length of the fin.
In other embodiments of the present invention, N-type planar transistors may also be formed.
Referring to fig. 3, an interface layer 301 is formed on the bottom surface of the groove 201; forming a gate dielectric material layer 302 on the interface layer 301, the side wall of the groove 201 and the surface of the dielectric layer 200; forming a cap material layer 303 on the gate dielectric material layer 302; a work function material layer 304 is formed on the cap material layer 303.
The surface of the semiconductor substrate 100 at the bottom of the recess 201 may be oxidized by an oxidation process to form the interfacial layer 301. In this embodiment, the interfacial layer 301 is formed by a thermal oxidation process. In other embodiments of the present invention, the interfacial layer 301 may also be formed by a wet oxidation process.
The material of the interface layer 301 is silicon oxide, and the thickness of the interface layer 301 is 1nm to 2 nm. The formation of the interface layer 301 can avoid the problem of lattice mismatch caused by direct contact between a subsequently formed gate dielectric material layer and the surface of the semiconductor substrate 100, thereby reducing defects in the gate dielectric material layer, enabling the quality of the gate dielectric material layer grown on the surface of the interface layer 301 to be better, and improving the quality of a subsequently formed second gate dielectric layer.
The material of the gate dielectric material layer 302 comprises HfO2、ZrO2、La2O3、HfSiON、Al2O3、HfSiO4Or HfAlO2. The gate dielectric material layer 302 may be formed by an atomic layer deposition process, and the thickness of the gate dielectric material layer 302 is 1nm to 3 nm. In other embodiments of the present invention, a chemical vapor deposition process may also be used to form the gate dielectric material layer. The gate dielectric material layer 302 covers the inside of the groove 201 and the surface of the dielectric layer 200.
After the gate dielectric material layer 302 is formed, a cap material layer 303 is formed on the surface of the gate dielectric material layer 302, wherein the cap material layer 303 may be TiN, TaN or TiSiN, and the thickness is 1nm to 3 nm.
The cap material layer 303 may be formed by an atomic layer deposition process, specifically, the atomic layer deposition process uses a reaction gas including: a first titanium-containing precursor gas comprising TiCl4、Ti[N(C2H5CH3)]4、Ti[N(CH3)2]4Or Ti [ N (C)2H5)2]4And a second precursor gas comprising NH3CO or H2And O, the flow rate of the first precursor gas is 50 sccm-200 sccm, the flow rate of the second precursor gas is 50 sccm-200 sccm, and the reaction temperature is 400-600 ℃.
The capping material layer 303 is used to protect the gate dielectric material layer 302 in subsequent processes. In the forming process of the cap material layer 303, the required reaction temperature is high, the energy of the reaction gas is high, the density of the formed cap material layer 303 is high, and the quality of an interface between the formed cap material layer 303 and the gate dielectric material layer 302 is also good.
After the cap material layer 303 is formed, a work function material layer 304 is formed on the surface of the cap material layer 303. In this embodiment, an NMOS transistor is formed, and the work function material layer 304 is an N-type work function material layer, specifically, the work function material layer 304 is made of TiAl, TiAlC, or TaAlC. The work-function material layer 304 may be formed using an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process.
In this embodiment, the work function material layer 304 is made of TiAl, the work function material layer 304 is formed by an atomic layer deposition process, a reaction gas used in the atomic layer deposition process includes a titanium-containing precursor and an aluminum-containing precursor, a reaction temperature is 50to 150 ℃, a flow rate of the titanium-containing precursor is 50to 200sccm, and a flow rate of the aluminum-containing precursor is 30to 900 sccm. Specifically, in the present embodiment,the titanium-containing precursor is TiCl4The aluminum-containing precursor is one or more compounds including dimethyl ethyl amine aluminum. In other embodiments of the present invention, the titanium-containing precursor and the aluminum-containing precursor may also be other suitable materials.
Referring to fig. 4, a diffusion barrier material layer 305 is formed on the work function material layer 304.
The material of the diffusion barrier material layer 305 may be TiN or TiSiN, and the diffusion barrier material layer 305 may be formed by using an atomic layer deposition process, so that the diffusion barrier material layer 305 has high deposition quality. The diffusion barrier material layer 305 has a barrier effect on atomic diffusion, and can block reactive gas atoms from diffusing into the work function material layer 305 in a subsequent gate material layer forming process, and also can block atoms in the work function material layer 305 from diffusing into a subsequently formed gate material layer.
In this embodiment, the diffusion barrier material layer 305 only provides a partial blocking effect, and a transition material layer with a diffusion blocking capability is continuously formed on the surface of the diffusion barrier material layer 305 to achieve a better diffusion blocking effect between the work function material layer 305 and the gate material layer, in this embodiment, the thickness of the diffusion barrier material layer 305 is set as
Figure BDA0000921969250000071
Since the material of the diffusion barrier material layer 305 has a larger resistivity, the thickness of the diffusion barrier material layer 305 in this embodiment is smaller, so that the resistance of the diffusion barrier material layer 305 is smaller, and the influence on the resistance of the whole gate structure is smaller.
Referring to fig. 5, a transition material layer 306 is formed on the diffusion barrier material layer 305, the transition material layer 306 has a diffusion barrier capability, and the resistance of the transition material layer 306 is smaller than the resistance of the diffusion barrier material layer 305.
The diffusion barrier material layer 305 also has a diffusion barrier capability, so the diffusion barrier material layer 305, together with the diffusion barrier material layer 104, blocks ion diffusion between the work function material layer 304 and the gate material layer formed in the subsequent process of forming the gate material layer and between the gate material layers.
The resistance of the transition material layer 306 is smaller than the resistance of the diffusion barrier material layer 305, and compared with the prior art that a thicker diffusion barrier material layer is adopted to block ion diffusion between the work function material layer 304 and a subsequently formed gate material layer, the resistance of the composite layer formed by the diffusion barrier material layer 305 and the transition material layer 306 is lower, and on the premise of not reducing the diffusion barrier effect, the resistance of the finally formed gate is reduced, so that the performance of the formed transistor is improved.
The transition material layer 306 may be formed by an atomic layer deposition process or a chemical vapor deposition process, in this embodiment, the transition material layer 306 is made of tungsten carbide, and the transition material layer 306 is formed by an atomic layer deposition process. Specifically, the reactant adopted by the atomic layer deposition process is W (CO)6And H2，W(CO)6The flow rate of (A) is 0.1 to 0.5g/min, H2The flow rate of the catalyst is 5000sccm to 10000sccm, the temperature is 400 ℃ to 450 ℃, and the pressure is 2Torr to 10 Torr. In other embodiments of the present invention, W (CO) may also be used6And HN3As a reactant, tungsten carbonitride is formed as a transition material layer 306.
The diffusion blocking capability of the transition material layer 306 is greater than that of the diffusion blocking material layer 305, so that to achieve the same diffusion blocking effect, the thickness of the composite layer structure formed by the transition material layer 306 and the diffusion blocking layer 105 is smaller than that when the diffusion blocking is achieved by only using the diffusion blocking material layer. In this embodiment, the thickness of the transition material layer 306 is
Figure BDA0000921969250000081
Referring to fig. 6, a gate material layer 307 is formed on the transition material layer 306 to fill the recess 201.
Can be used forThe gate material layer 307 is formed by a chemical vapor deposition process, the gate material layer 307 is made of a material having a high filling property, and in this embodiment, the gate material layer 307 is made of W. The chemical vapor deposition process adopts WF6And H2As reactant, WF6The flow rate of (A) is 250sccm to 350sccm, H2The flow rate is 5000 sccm-10000 sccm, the pressure is 30 Torr-50 Torr, the temperature is 375-425 ℃, and during the deposition process, the block W which is filled in the groove 201 is directly formed on the surface of the transition material layer 306.
Reactant WF used in the formation of the gate material layer 3076F atoms in the work function material layer 304 have high diffusion performance, and the transition material layer 306 and the diffusion barrier layer 305 can block F from diffusing to a lower layer into the work function material layer 304 in the process of forming the gate material layer 307, so that the work function of the work function material layer 304 is prevented from being changed.
If the gate material layer 307 is formed directly on the surface of the diffusion material layer, the gate material 307 is tungsten, two deposition stages are required: nucleation stage and bulk deposition stage, employing WF in the nucleation stage6And B2H6Or SiH4Reacting at a relatively low temperature (240-330 ℃) to form a forming nucleus layer, and then carrying out a block deposition stage to form a block layer filled with grooves on the surface of the forming nucleus layer. In this embodiment, the surface of the diffusion material layer 305 is formed with a transition material layer 306, the transition material layer 306 is made of tungsten carbide or tungsten carbonitride, and the transition material layer 306 can be used as a nucleation layer in the deposition process of the gate material layer 307, so that the bulk deposition stage can be directly performed through WF6And H2The reaction forms a bulk W as a layer of gate material 307. Since no additional formation of a nucleation layer is required, the space to be filled in the groove is increased, the deposition process window for forming the gate material layer 307 is increased, and the improvement of the deposition quality of the gate material layer 307 is facilitated.
Referring to fig. 7, the dielectric layer 200 is used as a stop layer to perform a planarization process, so as to form a gate structure located in the recess 201 (see fig. 5).
By using the dielectric layer 200 as a stop layer, a chemical mechanical polishing process is performed to planarize the gate dielectric material layer 302 (see fig. 6), the cap material layer 303 (see fig. 6), the work function material layer 304 (see fig. 6), the diffusion barrier material layer 305 (see fig. 6), the transition material layer 306 (see fig. 6), and the gate material layer 307 (see fig. 6), and each material layer on the surface of the dielectric layer 200 is removed to form a gate structure in the recess. The gate structure comprises an interface layer 301 located on the bottom surface of the groove 201, a gate dielectric layer 302a located on the surface of the interface layer 301 and the surface of the side wall of the groove 201, a capping layer 303a located on the surface of the gate dielectric layer 302a, a work function layer 304a located on the surface of the capping layer 303a, a diffusion barrier layer 305a located on the surface of the work function layer 304a, a transition layer 306a located on the surface of the diffusion barrier layer 305a, and a gate layer 307a located on the surface of the transition layer 306 a.
The grid electrode structure formed by the method has lower grid electrode resistance, improves the deposition quality of the grid electrode layer and is beneficial to improving the performance of the formed transistor.
In the embodiment of the invention, the transistor formed by the method is also provided.
Referring to fig. 7, a schematic structural diagram of the transistor includes: the semiconductor device comprises a semiconductor substrate 100, wherein the surface of the semiconductor substrate 100 is provided with a dielectric layer 200 and a groove penetrating through the dielectric layer 200, and active drains 101 are formed in the semiconductor substrate 100 at two sides of the groove; an interfacial layer 301 on a bottom surface of the groove; the gate dielectric layer 302a is positioned on the surface of the interface layer 301 and the surface of the side wall of the groove; a cap layer 303a positioned on the surface of the gate dielectric layer 302 a; a work-function layer 304a on the surface of the cap layer 303 a; a diffusion barrier layer 305a on the surface of the work function layer 304 a; a transition layer 306a located on the surface of the diffusion barrier layer 305a, the transition layer 306a having diffusion barrier capability and the transition layer 306a having a resistance less than the diffusion barrier layer resistance 305 a; and a gate layer 307a located on the surface of the transition layer 306a and filling the recess.
In this embodiment, the material of the diffusion barrier layer 305a is TiN or TiSiN. The diffusion barrier layer 305a has a thickness of
Figure BDA0000921969250000091
The transition layer 306a is made of tungsten carbide or tungsten carbonitride and has a thickness of
Figure BDA0000921969250000092
The transition layer 306 may block atomic diffusion between the work function layer 305a and the gate layer 307 a.
In this embodiment, the diffusion blocking capability of the transition layer 306a is greater than that of the diffusion blocking layer 305 a.
The material of the gate layer 307a is W; the capping layer 303a is made of TiN, TaN or TiSiN and has the thickness of 1 nm-3 nm; the interface layer 301 is made of silicon oxide, and the thickness of the interface layer 301 is 1 nm-2 nm; the work function layer 304a is made of TiAl, TiAl C or TaAlC.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a transistor, comprising:
providing a semiconductor substrate, wherein a dielectric layer and a groove penetrating through the dielectric layer are formed on the surface of the semiconductor substrate, and active drain electrodes are formed in the semiconductor substrate on two sides of the groove;
forming an interface layer on the bottom surface of the groove;
forming a gate dielectric material layer on the interface layer, the side wall of the groove and the surface of the dielectric layer;
forming a cap material layer on the gate dielectric material layer;
forming a work function material layer on the cap material layer;
forming a diffusion barrier material layer on the work function material layer;
forming a transition material layer on the diffusion barrier material layer, wherein the transition material layer has diffusion barrier capability and the resistance of the transition material layer is smaller than that of the diffusion barrier material layer;
forming a gate material layer which is filled in the groove on the transition material layer;
taking the dielectric layer as a stop layer, carrying out planarization treatment to form a gate structure positioned in the groove, wherein the gate structure comprises an interface layer positioned on the bottom surface of the groove, a gate dielectric layer positioned on the surface of the interface layer and the surface of the side wall of the groove, a cap layer positioned on the surface of the gate dielectric layer, a work function layer positioned on the surface of the cap layer, a diffusion barrier layer positioned on the surface of the work function layer, a transition material layer positioned on the surface of the diffusion barrier layer and a gate layer positioned on the surface of the transition material layer;
the diffusion barrier capability of the transition material layer is greater than that of the diffusion barrier material layer.
2. The method according to claim 1, wherein a material of the diffusion barrier material layer is TiN or TiSiN.
3. The method of claim 1, wherein the diffusion barrier material layer has a thickness of
Figure FDA0002387202380000011
4. The method of claim 1, wherein the diffusion barrier material layer is formed using an atomic layer deposition process.
5. The method according to claim 1, wherein a material of the transition material layer is tungsten carbide or tungsten carbonitride.
6. The method of claim 5, wherein the transition material layer has a thickness of
Figure FDA0002387202380000021
7. The method of claim 5, wherein the transition material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
8. The method for forming a transistor according to claim 5, wherein the method for forming the transition material layer comprises: by adopting W (CO)6And H2As a reactant, W (CO)6The flow rate of (A) is 0.1 g/min-0.5 g/min, H2The flow rate of the catalyst is 5000sccm to 10000sccm, the temperature is 400 ℃ to 450 ℃, and the pressure is 2Torr to 10 Torr.
9. The method according to claim 1, wherein a material of the gate material layer is W.
10. The method of claim 9, wherein the gate material layer is formed by a chemical vapor deposition process.
11. The method of claim 10, wherein the chemical vapor deposition process uses WF6And H2As reactant, WF6The flow rate of (A) is 250sccm to 350sccm, H2The flow rate of the catalyst is 5000sccm to 10000sccm, the pressure is 30Torr to 50Torr, and the temperature is 375 ℃ to 425 ℃.
12. The method of claim 1, wherein the capping material layer is TiN, TaN or TiSiN with a thickness of 1nm to 3 nm.
13. The method according to claim 1, wherein the interface layer is formed by an oxidation process, wherein a material of the interface layer is silicon oxide, and a thickness of the interface layer is 1nm to 2 nm.
14. The method according to claim 1, wherein a material of the work function material layer is TiAl, TiAlC, or TaAlC.
15. A transistor, comprising:
the semiconductor substrate is provided with a dielectric layer and a groove penetrating through the dielectric layer on the surface, and active drain electrodes are formed in the semiconductor substrate on two sides of the groove;
an interfacial layer on a bottom surface of the groove;
the gate dielectric layer is positioned on the surface of the interface layer and the surface of the side wall of the groove;
the cap layer is positioned on the surface of the gate dielectric layer;
the work function layer is positioned on the surface of the cap layer;
a diffusion barrier layer on the surface of the work function layer;
the transition layer is positioned on the surface of the diffusion barrier layer, the transition layer has diffusion barrier capability, and the resistance of the transition layer is smaller than that of the diffusion barrier layer;
the gate layer is positioned on the surface of the transition layer and fully fills the groove;
the diffusion barrier capability of the transition layer is greater than the diffusion barrier capability of the diffusion barrier layer.
16. The transistor of claim 15, wherein the material of the diffusion barrier layer is TiN or TiSiN.
17. The transistor of claim 15 wherein the diffusion barrier layer has a thickness of
Figure FDA0002387202380000031
18. The transistor of claim 15, wherein said transistorThe transition layer is made of tungsten carbide or tungsten carbonitride and has a thickness of
Figure FDA0002387202380000032
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