CN107039271A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN107039271A CN107039271A CN201610079377.XA CN201610079377A CN107039271A CN 107039271 A CN107039271 A CN 107039271A CN 201610079377 A CN201610079377 A CN 201610079377A CN 107039271 A CN107039271 A CN 107039271A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 230
- 238000009792 diffusion process Methods 0.000 claims abstract description 116
- 230000004888 barrier function Effects 0.000 claims abstract description 81
- 230000007704 transition Effects 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 19
- 239000003989 dielectric material Substances 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 331
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 229910008482 TiSiN Inorganic materials 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- -1 carbon tungsten nitride Chemical class 0.000 claims description 8
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000000376 reactant Substances 0.000 claims description 7
- 229910010038 TiAl Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 5
- 229910010041 TiAlC Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 125000004429 atom Chemical group 0.000 description 15
- 238000000151 deposition Methods 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- 230000008021 deposition Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000002243 precursor Substances 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000012792 core layer Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910003074 TiCl4 Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 description 1
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- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- DAZXVJBJRMWXJP-UHFFFAOYSA-N n,n-dimethylethylamine Chemical compound CCN(C)C DAZXVJBJRMWXJP-UHFFFAOYSA-N 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of forming method of transistor, including：Semiconductor substrate is provided, the semiconductor substrate surface is formed with dielectric layer, and is formed with source-drain electrode in the groove of the dielectric layer, the Semiconductor substrate of the groove both sides；Boundary layer is formed on the bottom portion of groove surface；In the boundary layer, recess sidewall and dielectric layer surface formation gate dielectric material layer；Cap material layer is formed on gate dielectric material layer；Workfunction material is formed on cap material layer；Diffusion barrier material layer is formed in the workfunction material；Transition material layer is formed on diffusion barrier material layer, there is the transition material layer resistance of diffusion barrier capability and transition material layer to be less than diffusion barrier material layer resistance；The gate material layers of the full groove of filling are formed on transition material layer；Using dielectric layer as stop-layer, planarization process is carried out, the grid structure being located in the groove is formed.Methods described is conducive to improving the performance of the transistor formed.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of transistor and forming method thereof.
Background technology
With the continuous improvement of semiconductor devices integrated level, the reduction of technology node, traditional gate dielectric layer is not
Disconnected thinning, transistor leakage amount increases therewith, the problems such as causing semiconductor devices power wastage.To solve
Above mentioned problem, prior art provides a kind of solution that metal gates are substituted to polysilicon gate.Wherein,
" rear grid (gate last) " technique is the main technique to form high-K metal gate gated transistors.
The method of existing use post tensioned unbonded prestressed concrete technique formation high-K metal gate gated transistors, including：Semiconductor is provided
Pseudo- grid structure is formed with substrate, the Semiconductor substrate and in the Semiconductor substrate and institute is covered
The interlayer dielectric layer of pseudo- grid structure is stated, the surface of the interlayer dielectric layer is flushed with pseudo- grid body structure surface；Go
Except forming groove after dummy gate structure；Metal-gate structures are sequentially formed in the groove.
Fig. 1 is refer to, is the schematic diagram of a metal-gate structures of the prior art.
The metal-gate structures include：Boundary layer 10 positioned at groove (not shown) bottom, positioned at boundary
Surface layer 10 and the gate dielectric layer on recess sidewall surface 20, the cap 30 positioned at gate dielectric layer surface, position
In the work-function layer 40 of block layer surface, positioned at the surface of work-function layer 40 diffusion impervious layer 50 and be located at
The surface of diffusion impervious layer 50 and the grid layer 60 of the full groove of filling.
The diffusion impervious layer 50 be used for stop is formed in the forming process of grid layer 60, reacting gas atom or
Ion spreads into work-function layer 40, while stopping that the atom in work-function layer 40 spreads into grid layer 60.
The threshold voltage of the thickness of the diffusion impervious layer 50 often pair nmos transistor causes large effect,
If the blocking effect of diffusion impervious layer is poor, the threshold voltage of nmos pass transistor can be caused substantially to rise,
Influence the performance of nmos pass transistor.
So, in the prior art, it is usually formed thicker (be more than) diffusion impervious layer, to improve expansion
Dissipate the non-proliferation ability on barrier layer.But, the thickness of diffusion impervious layer, which is improved, can cause the electricity of metal gates
Resistance increase, and the deposition difficulty of grid layer is improved, influence the performance of transistor formed.
The content of the invention
The problem of present invention is solved is to provide a kind of transistor and forming method thereof, improves the transistor formed
Performance.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Offer is partly led
Body substrate, the semiconductor substrate surface is formed with dielectric layer, and through the groove of the dielectric layer, institute
Source-drain electrode is formed with the Semiconductor substrate for stating groove both sides；Boundary layer is formed on the bottom portion of groove surface；
In the boundary layer, recess sidewall and dielectric layer surface formation gate dielectric material layer；In the gate medium
Cap material layer is formed in material layer；Workfunction material is formed on cap material layer；Described
Diffusion barrier material layer is formed in workfunction material；Transition material is formed on diffusion barrier material layer
The bed of material, the transition material layer has diffusion barrier capability and the resistance of transition material layer is less than diffusion
Barrier material layer resistance；The gate material layers of the full groove of filling are formed on transition material layer；With institute
Dielectric layer is stated for stop-layer, planarization process is carried out, the grid structure being located in the groove, institute is formed
Grid structure is stated including the boundary layer positioned at bottom portion of groove surface, positioned at the interface layer surfaces and groove side
The gate dielectric layer of wall surface, the cap positioned at gate dielectric layer surface, the work function positioned at block layer surface
Layer, the diffusion impervious layer positioned at work-function layer surface, the transition zone positioned at diffusion barrier layer surface and position
In the grid layer of transition layer surface.
Optionally, the material of the diffusion barrier material layer is TiN or TiSiN.
Optionally, the thickness of the diffusion barrier material layer is
Optionally, the diffusion barrier material layer is formed using atom layer deposition process.
Optionally, the diffusion barrier capability of the transition material layer is more than the diffusion resistance of diffusion barrier material layer
Gear ability.
Optionally, the material of the transition material layer is tungsten carbide or carbon tungsten nitride.
Optionally, the thickness of the transition material layer is
Optionally, the transition material layer is formed using atom layer deposition process or chemical vapor deposition method.
Optionally, the forming method of the transition material layer includes：Using W (CO)6And H2It is used as reaction
Thing, W (CO)6Flow be 0.1g/min~0.5g/min, H2Flow be 5000sccm~10000sccm,
Temperature is 400 DEG C~450 DEG C, and pressure is 2Torr~10Torr.
Optionally, the material of the gate material layers is W.
Optionally, the gate material layers are formed using chemical vapor deposition method.
Optionally, the chemical vapor deposition method uses WF6And H2It is used as reactant, WF6Flow
For 250sccm~350sccm, H2Flow be 5000sccm~10000sccm, pressure is 30Torr
~50Torr, temperature is 375 DEG C~425 DEG C.
Optionally, the material of the cap material layer is TiN, TaN or TiSiN, and thickness is 1nm~3nm.
Optionally, the boundary layer is formed using oxidation technology, the material of the boundary layer is silica,
The thickness of the boundary layer is 1nm~2nm.
Optionally, the material of workfunction material is TiAl, TiAlC or TaAlC.
To solve the above problems, the present invention also provides a kind of transistor of use above method formation, including：
Semiconductor substrate, the semiconductor substrate surface has dielectric layer and the groove through the dielectric layer, institute
Source-drain electrode is formed with the Semiconductor substrate for stating groove both sides；Boundary layer positioned at the bottom portion of groove surface；
Gate dielectric layer positioned at the interface layer surfaces and recess sidewall surface；Block positioned at gate dielectric layer surface
Layer；Positioned at the work-function layer of block layer surface；Diffusion impervious layer positioned at work-function layer surface；Positioned at expansion
The transition zone of barrier layer surface is dissipated, the transition zone has the resistance of diffusion barrier capability and the transition zone
Less than diffusion impervious layer resistance；Positioned at transition layer surface and the grid layer of the full groove of filling.
Optionally, the material of the diffusion impervious layer is TiN or TiSiN.
Optionally, the thickness of the diffusion impervious layer is
Optionally, the diffusion barrier capability of the transition zone is more than the diffusion barrier capability of diffusion impervious layer.
Optionally, the material of the transition zone is tungsten carbide or carbon tungsten nitride, and thickness is
Compared with prior art, technical scheme has advantages below：
In technical scheme, after work function material layer surface formation diffusion barrier material layer,
Again in diffusion barrier material layer surface formation transition material layer, then again in transition material layer table
Face forms gate material layers.Transition material layer has diffusion barrier capability and transition material layer
Resistance is less than diffusion barrier material layer resistance.Diffusion barrier material layer together with diffusion barrier material layer,
Stop workfunction material and the gate material layers that are subsequently formed during gate material layers and are formed it
Between ion diffusion.The resistance of transition material layer is less than the resistance of diffusion barrier material layer, and existing
The gate material layers for stopping workfunction material using thicker diffusion barrier material layer and being subsequently formed it
Between ion diffusion compare, the resistance of diffusion barrier material layer and the composite bed of transition material layer formation
Value is lower, on the premise of diffusion barrier effect is not reduced, reduces the resistance value of the grid ultimately formed,
So as to improve the performance of the transistor of formation.
Further, the material of the transition material layer is tungsten carbide or carbon tungsten nitride, the transition material layer
Can as the forming core in grid material layer deposition process layer, so, can directly carry out block deposition rank
Section, passes through WF6And H2Reaction forms block W, is used as gate material layers.Due to need not extra shape again
Stratum nucleare is shaped, so, the space to be filled increase of groove forms the depositing operation window of gate material layers
Increase, is conducive to improving the deposition quality of gate material layers.
Brief description of the drawings
Fig. 1 is the structural representation of the metal gates of prior art；
Fig. 2 to Fig. 7 is the structural representation of the forming process of the transistor of embodiments of the invention.
Embodiment
As described in the background art, the thickness of the diffusion impervious layer of existing nmos pass transistor is larger, leads
The resistance increase of metal gates is caused, and the deposition difficulty of grid layer is improved, the NMOS formed is influenceed
The performance of transistor.
In embodiments of the invention, the less diffusion impervious layer of thickness is formed, and in the diffusion barrier
Layer surface formation transition zone, the transition material layer has diffusion barrier effect, and resistance is less than diffusion and hindered
Barrier resistance, so as to reduce metal gates resistance, improves the performance of the transistor formed.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 2 be refer to there is provided Semiconductor substrate 100, the surface of Semiconductor substrate 100 is formed with medium
Layer 200, and through the groove 201 of the dielectric layer 200, the Semiconductor substrate of the both sides of groove 201
Source-drain electrode 101 is formed with 100.
The material of the Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs,
The Semiconductor substrate 100 can be that body material can also be composite construction such as silicon-on-insulator.This area
Technical staff according to the semiconductor devices that is formed in Semiconductor substrate 100 semiconductor can be selected to serve as a contrast
The type at bottom 100, therefore the type of the Semiconductor substrate 100 should not limit the scope of the invention.
Form the dielectric layer 200, groove 201 and source-drain electrode 101 on the surface of Semiconductor substrate 100
Method includes：Semiconductor substrate 100 is provided；Pseudo- grid structure is formed on the surface of Semiconductor substrate 100；Institute
State and source-drain electrode 101 is formed in the Semiconductor substrate 100 of pseudo- grid structure both sides；In the Semiconductor substrate 100
Surface forms dielectric layer 200, and the surface of the dielectric layer 200 is flushed with pseudo- grid body structure surface；Remove described
Pseudo- grid structure, forms the groove 201 through the dielectric layer 200.The material of the dielectric layer 200 is oxygen
SiClx.
In the present embodiment, transistor to be formed is N-type fin formula field effect transistor, the semiconductor lining
Bottom 100 includes body silicon substrate and the fin positioned at the body surface of silicon, and dummy gate structure is across fin
Portion, the top of covering part fin and side wall, so, the groove 201 of formation exposes part fin
Bottom and sidewall surfaces.Fig. 2 is the diagrammatic cross-section along fin length direction.
In other embodiments of the invention, the planar transistor of N-type can also be formed.
Fig. 3 is refer to, in the lower surface of groove 201 formation boundary layer 301；The boundary layer 301,
The side wall of groove 201 and the surface of dielectric layer 200 form gate dielectric material layer 302；In the gate dielectric material
Cap material layer 303 is formed on layer 302；Workfunction material is formed on cap material layer 303
304。
The surface of Semiconductor substrate 100 of the bottom of groove 201 can be aoxidized using oxidation technology,
Form the boundary layer 301.In the present embodiment, the boundary layer 301 is formed using thermal oxidation technology.
In the other embodiment of the present invention, the boundary layer 301 can also be formed by wet process oxidation technology.
The material of the boundary layer 301 is silica, and the thickness of the boundary layer 301 is 1nm~2nm.
Form gate dielectric material layer and the table of Semiconductor substrate 100 that the boundary layer 301 can avoid being subsequently formed
The problem of face directly contacts and produces lattice mismatch, so as to reduce the defect in gate dielectric material layer, makes grid
Layer of dielectric material the superficial growth of boundary layer 301 better quality, so as to improve be subsequently formed
The quality of gate dielectric layer.
The material of the gate dielectric material layer 302 includes HfO2、ZrO2、La2O3、HfSiON、Al2O3、
HfSiO4Or HfAlO2.The gate dielectric material layer 302 can be formed using atom layer deposition process,
The thickness of the gate dielectric material layer 302 is 1nm~3nm.In other embodiments of the invention, may be used also
To form the gate dielectric material layer using chemical vapor deposition method.The gate dielectric material layer 302 covers
The inside of lid groove 201 and the surface of dielectric layer 200.
After the gate dielectric material layer 302 is formed, formed on 302 surface of gate dielectric material layer
Cap material layer 303, the material of the cap material layer 303 can be TiN, TaN or TiSiN, thickness
Spend for 1nm~3nm.
The cap material layer 303 can be formed using atom layer deposition process, specifically, the atom
Layer depositing operation is included using reacting gas：First precursor gas of titaniferous, the precursor gas of titaniferous first
Body includes TiCl4、Ti[N(C2H5CH3)]4、Ti[N(CH3)2]4Or Ti [N (C2H5)2]4, in addition to before second
Purging body, second precursor gas includes NH3, CO or H2O, the flow velocity of first precursor gas
For 50sccm~200sccm, the flow velocity of second precursor gas is 50sccm~200sccm, reaction temperature
For 400 DEG C~600 DEG C.
The cap material layer 303 is used to protect the gate dielectric material layer 302 in subsequent technique.Due to
In the forming process of cap material layer 303, it is necessary to reaction temperature it is higher, the energy of reacting gas
Larger, the material density of the cap material layer 303 of formation is higher, between gate dielectric material layer 302
Interface quality it is also preferable.
After the cap material layer 303 is formed, work content is formed on 303 surface of cap material layer
Number material layer 304.In the present embodiment, nmos pass transistor, the corresponding workfunction material are formed
304 be N-type workfunction material, specifically, the material of the workfunction material 304 be TiAl,
TiAlC or TaAlC.Atom layer deposition process, physical gas-phase deposition or chemical vapor deposition can be used
Product technique forms the workfunction material 304.
In the present embodiment, the material of the workfunction material 304 is TiAl, using ald work
Skill forms the workfunction material 304, and the reacting gas that ald institute technique is used includes containing
Titanium precursor thing and predecessor containing aluminium, reaction temperature are 50 DEG C~150 DEG C, and the flow of titaniferous predecessor is
50sccm~200sccm, the flow of the predecessor containing aluminium is 30sccm~900sccm.Specifically, the present embodiment
In, the titaniferous predecessor is TiCl4, predecessor containing aluminium is to include one kind including dimethylethyl amine aluminium
Or multiple compounds.In other embodiments of the invention, the titaniferous predecessor and predecessor containing aluminium be also
Can be other suitable materials.
Fig. 4 is refer to, diffusion barrier material layer 305 is formed in the workfunction material 304.
The material of the diffusion barrier material layer 305 can be TiN or TiSiN, can use atomic layer deposition
Product technique forms diffusion barrier material layer 305, with cause the diffusion barrier material layer 305 have compared with
High deposition quality.305 pairs of atoms permeating of the diffusion barrier material layer have barrier effect, can hinder
The reacting gas atom that gear is subsequently formed during gate material layers spreads to workfunction material 305,
It can stop that the atom in workfunction material 305 spreads into the gate material layers being subsequently formed.
In the present embodiment, the diffusion barrier material layer 305 only provides part barrier effect, subsequently in institute
State 305 surface of diffusion barrier material layer and continuously form the transition material layer with diffusion barrier capability, with reality
In existing diffusion barrier effect preferable between workfunction material 305 and gate material layers, the present embodiment,
The thickness of diffusion barrier material layer 305 isDue to the material of diffusion barrier material layer 305
Resistivity it is larger, diffusion barrier material described in the present embodiment layer 305 thickness it is smaller so that it is described
The resistance of diffusion barrier material layer 305 is smaller, smaller to the Resistance Influence of whole grid structure.
Fig. 5 is refer to, transition material layer 306, the mistake are formed on diffusion barrier material layer 305
Material layer 306 is crossed with diffusion barrier capability, and the resistance of transition material layer 306 is less than diffusion resistance
The resistance of obstructing material layer 305.
The diffusion barrier material layer 305 equally has diffusion barrier capability, so the diffusion barrier material
The bed of material 305 stops workfunction material 304 and is subsequently formed grid together with diffusion barrier material layer 104
Ion diffusion during the material layer of pole and between the gate material layers of formation.
The resistance of the transition material layer 306 is less than the resistance of diffusion barrier material layer 305, with existing skill
The grid for stopping workfunction material 304 using thicker diffusion barrier material layer in art Yu being subsequently formed
Ion diffusion between material layer is compared, the diffusion barrier material layer 305 and transition material 306 shape of layer
Into composite bed resistance value it is lower, do not reduce diffusion barrier effect on the premise of, reduction is ultimately formed
Grid resistance value, so as to improve the performance of the transistor of formation.
The transition material layer 306 can be formed using atom layer deposition process or chemical vapor deposition method,
In the present embodiment, the material of the transition material layer 306 is tungsten carbide, using atom layer deposition process shape
Into transition material layer 306.Specifically, the reactant that the atom layer deposition process is used is W (CO)6
And H2, W (CO)6Flow be 0.1~0.5g/min, H2Flow be 5000sccm~10000sccm,
Temperature is 400 DEG C~450 DEG C, and pressure is 2Torr~10Torr.In other embodiments of the invention, also may be used
With using W (CO)6And HN3As reactant, carbon tungsten nitride is formed as transition material layer 306.
The diffusion barrier capability of the transition material layer 306 is more than the diffusion resistance of diffusion barrier material layer 305
Gear ability, so, to reach same diffusion barrier effect, transition material layer 306 and diffusion impervious layer
When the thickness of the lamination layer structure of 105 compositions using diffusion barrier material layer less than diffusion barrier is realized merely
Thickness, compared with prior art, groove 201 be not filled part width increase, after can improving
The process window of the continuous gate material layers for forming the full groove 201 of filling, improves the heavy of the gate material layers
Product quality.In the present embodiment, the thickness of the transition material layer 306 is
Fig. 6 is refer to, the gate material layers of the full groove 201 of filling are formed on transition material layer 306
307。
The gate material layers 307, the gate material layers can be formed using chemical vapor deposition method
307 material has in higher filling capacity, the present embodiment, and the material of the gate material layers 307 is
W.The chemical vapor deposition method uses WF6And H2It is used as reactant, WF6Flow be 250sccm
~350sccm, H2Flow be 5000sccm~10000sccm, pressure be 30Torr~50Torr, temperature
Spend for 375 DEG C~425 DEG C, in above-mentioned deposition process, directly form filling on 306 surface of transition material layer
The block W of full groove 201.
The reactant WF used in the forming process of gate material layers 3076In F atom have it is higher
Diffusion, transition material layer 306 and diffusion impervious layer 305 are forming the gate material layers
During 307, it can stop that F is diffused into workfunction material 304 to lower floor, it is to avoid work function
The work function of material layer 304 changes.
If directly in diffusion material layer surface formation gate material layers 307, the grid material 307 is tungsten
When, it is necessary to by two depositional phases：Forming core stage and block depositional phase, WF is used in the forming core stage6
With B2H6Or SiH4(240 DEG C~330 DEG C) reactions form forming core layer at relatively low temperature, then carry out again
The block depositional phase, in the course of blocks of the full groove of forming core layer surface formation filling.Due to the present embodiment
In, the surface of diffusing material layer 305 is formed with transition material layer 306, the transition material layer 306
Material is tungsten carbide or carbon tungsten nitride, and the transition material layer 306 can be heavy as gate material layers 307
Forming core layer during product, so, it can directly carry out the block depositional phase, pass through WF6And H2Reaction
Block W is formed, gate material layers 307 are used as.Due to forming core layer need not be additionally formed again, so,
The space to be filled increase of groove, forms the depositing operation window increase of gate material layers 307, is conducive to
Improve the deposition quality of gate material layers 307.
Fig. 7 is refer to, is stop-layer with the dielectric layer 200, planarization process is carried out, is formed and is located at institute
State the grid structure in groove 201 (refer to Fig. 5).
It is stop-layer with the dielectric layer 200 using chemical mechanical milling tech, to the gate medium material
The bed of material 302 (refer to Fig. 6), 303 (refer to Fig. 6) of cap material layer, workfunction material 304
305 (refer to Fig. 6) of (refer to Fig. 6), diffusion barrier material layer, transition material layer 306 (please join
Examine Fig. 6) and gate material layers 307 (refer to Fig. 6) planarized, remove be located at dielectric layer 200
Each material layer on surface, forms the grid structure being located in groove.The grid structure includes being located at groove
The boundary layer 301 of 201 lower surfaces, positioned at the surface of boundary layer 301 and the sidewall surfaces of groove 201
Gate dielectric layer 302a, the cap 303a positioned at gate dielectric layer 302a surfaces, positioned at cap 303a tables
The work-function layer 304a in face, the diffusion impervious layer 305a positioned at work-function layer 304a surfaces, positioned at diffusion resistance
The transition zone 306a on the barrier 305a surfaces and grid layer 307a positioned at transition zone 306a surfaces.
The resistance of the grid structure of above method formation is relatively low, and the deposition quality of grid layer is improved, and is had
Beneficial to the performance for improving the transistor formed.
In embodiments of the invention, a kind of transistor of use above method formation is also provided.
Fig. 7 is refer to, is the structural representation of the transistor, including：Semiconductor substrate 100, it is described
The surface of Semiconductor substrate 100 has dielectric layer 200 and the groove through the dielectric layer 200, described recessed
Source-drain electrode 101 is formed with the Semiconductor substrate 100 of groove both sides；Interface positioned at the bottom portion of groove surface
Layer 301；Gate dielectric layer 302a positioned at the surface of boundary layer 301 and recess sidewall surface；Positioned at grid
The cap 303a on dielectric layer 302a surfaces；Work-function layer 304a positioned at cap 303a surfaces；Position
Diffusion impervious layer 305a in work-function layer 304a surfaces；Transition positioned at diffusion impervious layer 305a surfaces
Layer 306a, the transition zone 306a has diffusion barrier capability and the resistance of the transition zone 306a is less than
Diffusion impervious layer resistance 305a；Positioned at transition zone 306a surfaces and the grid layer 307a of the full groove of filling.
In the present embodiment, the material of the diffusion impervious layer 305a is TiN or TiSiN.The diffusion resistance
Barrier 305a thickness is
The material of the transition zone 306a is tungsten carbide or carbon tungsten nitride, and thickness isIt is described
Transition zone 306 can stop the atoms permeating between work-function layer 305a and grid layer 307a.
In the present embodiment, the diffusion barrier capability of the transition zone 306a is more than diffusion impervious layer 305a expansion
Dissipate blocking capability.
The material of the grid layer 307a is W；The material of the cap 303a be TiN, TaN or
TiSiN, thickness is 1nm~3nm；The material of the boundary layer 301 is silica, the boundary layer 301
Thickness be 1nm~2nm；The material of the work-function layer 304a is TiAl, TiAlC or TaAlC.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of transistor, it is characterised in that including：
Semiconductor substrate is provided, the semiconductor substrate surface is formed with dielectric layer, and through the medium
Source-drain electrode is formed with the groove of layer, the Semiconductor substrate of the groove both sides；
Boundary layer is formed on the bottom portion of groove surface；
In the boundary layer, recess sidewall and dielectric layer surface formation gate dielectric material layer；
Cap material layer is formed on gate dielectric material layer；
Workfunction material is formed on cap material layer；
Diffusion barrier material layer is formed in the workfunction material；
Transition material layer is formed on diffusion barrier material layer, the transition material layer has diffusion resistance
The resistance of gear ability and transition material layer is less than diffusion barrier material layer resistance；
The gate material layers of the full groove of filling are formed on transition material layer；
Using the dielectric layer as stop-layer, planarization process is carried out, the grid being located in the groove is formed
Structure, the grid structure is including the boundary layer positioned at bottom portion of groove surface, positioned at the interface layer surfaces
Gate dielectric layer with recess sidewall surface, the cap positioned at gate dielectric layer surface, positioned at block layer surface
Work-function layer, the diffusion impervious layer positioned at work-function layer surface, the transition positioned at diffusion barrier layer surface
Layer and positioned at the grid layer of transition layer surface.
2. the forming method of transistor according to claim 1, it is characterised in that the diffusion barrier material
The material of the bed of material is TiN or TiSiN.
3. the forming method of transistor according to claim 1, it is characterised in that the diffusion barrier material
The thickness of the bed of material is
4. the forming method of transistor according to claim 1, it is characterised in that use ald
Technique forms the diffusion barrier material layer.
5. the forming method of transistor according to claim 1, it is characterised in that the transition material layer
Diffusion barrier capability be more than diffusion barrier material layer diffusion barrier capability.
6. the forming method of transistor according to claim 5, it is characterised in that the transition material layer
Material be tungsten carbide or carbon tungsten nitride.
7. the forming method of transistor according to claim 6, it is characterised in that the transition material layer
Thickness be
8. the forming method of transistor according to claim 6, it is characterised in that use ald
Technique or chemical vapor deposition method form the transition material layer.
9. the forming method of transistor according to claim 6, it is characterised in that the transition material layer
Forming method include：Using W (CO)6And H2It is used as reactant, W (CO)6Flow be 0.1
G/min~0.5g/min, H2Flow be 5000sccm~10000sccm, temperature be 400 DEG C~450 DEG C,
Pressure is 2Torr~10Torr.
10. the forming method of transistor according to claim 1, it is characterised in that the gate material layers
Material be W.
11. the forming method of transistor according to claim 10, it is characterised in that use chemical vapor deposition
Product technique forms the gate material layers.
12. the forming method of transistor according to claim 11, it is characterised in that the chemical vapor deposition
Product technique uses WF6And H2It is used as reactant, WF6Flow be 250sccm~350sccm, H2
Flow be 5000sccm~10000sccm, pressure be 30Torr~50Torr, temperature be 375 DEG C
~425 DEG C.
13. the forming method of transistor according to claim 1, it is characterised in that the cap material layer
Material be TiN, TaN or TiSiN, thickness be 1nm~3nm.
14. the forming method of transistor according to claim 1, it is characterised in that use oxidation technology shape
Into the boundary layer, the material of the boundary layer is silica, and the thickness of the boundary layer is
1nm~2nm.
15. the forming method of transistor according to claim 1, it is characterised in that workfunction material
Material is TiAl, TiAlC or TaAlC.
16. a kind of transistor, it is characterised in that including：
Semiconductor substrate, the semiconductor substrate surface has dielectric layer and the groove through the dielectric layer,
Source-drain electrode is formed with the Semiconductor substrate of the groove both sides；
Boundary layer positioned at the bottom portion of groove surface；
Gate dielectric layer positioned at the interface layer surfaces and recess sidewall surface；
Cap positioned at gate dielectric layer surface；
Positioned at the work-function layer of block layer surface；
Diffusion impervious layer positioned at work-function layer surface；
Positioned at the transition zone of diffusion barrier layer surface, the transition zone has diffusion barrier capability and the mistake
The resistance for crossing layer is less than diffusion impervious layer resistance；
Positioned at transition layer surface and the grid layer of the full groove of filling.
17. transistor according to claim 16, it is characterised in that the material of the diffusion impervious layer is
TiN or TiSiN.
18. transistor according to claim 16, it is characterised in that the thickness of the diffusion impervious layer is
19. transistor according to claim 16, it is characterised in that the diffusion barrier capability of the transition zone
More than the diffusion barrier capability of diffusion impervious layer.
20. transistor according to claim 19, it is characterised in that the material of the transition zone is tungsten carbide
Or carbon tungsten nitride, thickness is
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| CN115287629A (en) * | 2021-07-09 | 2022-11-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
| CN117238848A (en) * | 2023-11-15 | 2023-12-15 | 合肥晶合集成电路股份有限公司 | Contact hole structure and forming method thereof |
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| CN110634952B (en) * | 2018-06-25 | 2023-06-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN115287629A (en) * | 2021-07-09 | 2022-11-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
| CN115287629B (en) * | 2021-07-09 | 2024-02-13 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
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