KR102276546B1 - Moisture blocking structure and/or guard ring, semiconductor device including the same, and method of manufacturing the same - Google Patents

Abstract

The moisture barrier structure includes an active fin, a gate structure, and a conductive structure. The active fin is formed on a sealing region of a substrate including a chip region and a sealing region surrounding the chip region, and continuously surrounds the chip region in a curved shape when viewed from the top. The gate structure surrounds the chip area while covering the active fin. A conductive structure is formed on the gate structure and surrounds the chip area.

Description

Moisture-proof structure and/or guard ring, semiconductor device including same, and manufacturing method thereof

The present invention relates to a moisture barrier structure and/or a guard ring, a semiconductor device including the same, and a method for manufacturing the same.

In a sealing area around the chip area, a moisture preventing structure for protecting the chip from moisture or cracks generated in the wafer dicing process, and a guard ring for grounding the chip (guard ring) may be formed. A finFET may be formed in the chip region according to the recent trend of high integration, and for this purpose, the chip region is separated from the chip region by a dishing phenomenon in a chemical mechanical polishing (CMP) process for forming active fins. A step of the insulating film is generated between the sealing regions, so that it is difficult to form a moisture preventing structure and/or a guard ring in the sealing region.

It is an object of the present invention to provide a moisture barrier structure and/or a guard ring having excellent properties.

Another object of the present invention is to provide a semiconductor device including the moisture barrier structure and/or a guard ring.

Another object of the present invention is to provide a method of manufacturing a semiconductor device including the moisture barrier structure and/or the guard ring.

The moisture barrier structure according to the embodiments of the present invention includes an active fin, a gate structure, and a conductive structure. The active fin is formed on the sealing region of the substrate including a chip region and a sealing region surrounding the chip region, and continuously surrounds the chip region in a curved shape when viewed from the top. The gate structure surrounds the chip region while covering the active fin. The conductive structure is formed on the gate structure and surrounds the chip region.

In example embodiments, the active fins may be formed in plurality, and the gate structure may cover two active fins adjacent to each other among the plurality of active fins.

In example embodiments, the two active fins adjacent to each other may be parallel to each other.

In example embodiments, the conductive structure may include a contact plug formed on the gate structure to surround the chip region and a via formed on the contact plug to surround the chip region. have.

In example embodiments, the active fin, the gate structure, and the conductive structure may each be formed in plurality, and the moisture barrier structure further includes a metal plate formed on the plurality of conductive structures. can do.

In example embodiments, the moisture barrier structure may further include a blocking layer pattern including an insulating material between the gate structure and the conductive structure.

In example embodiments, the gate structure may include a gate insulating layer pattern and a gate electrode sequentially stacked on the active fin.

In example embodiments, the gate insulating layer pattern may include a high-k material, and the gate electrode may include a metal.

In example embodiments, the active fin includes first portions each extending in a first direction parallel to the upper surface of the substrate and a second direction parallel to the upper surface of the substrate and substantially perpendicular to the first direction. Each of the second portions may be extended, and the first and second portions may have their ends connected to each other.

In example embodiments, the active fin may extend in a wave shape.

A guard ring according to embodiments for achieving the object of the present invention includes an active fin and a conductive structure. The active fin is formed on the sealing region of the substrate including a chip region and a sealing region surrounding the chip region, and continuously surrounds the chip region in a curved shape when viewed from the top. The conductive structure is formed on the active fin to surround the chip region.

In example embodiments, the active fins may be formed in plurality, and the conductive structure may cover two active fins adjacent to each other among the plurality of active fins.

In example embodiments, the two active fins adjacent to each other may be parallel to each other.

In example embodiments, the conductive structure may include a contact plug formed on the active fin to surround the chip region and a via formed on the contact plug to surround the chip region. have.

In example embodiments, the active fin and the conductive structure may each be formed in plurality, and the guard ring may further include a metal plate formed on the plurality of conductive structures.

In example embodiments, the guard ring may further include a source/drain layer and a metal silicide pattern sequentially stacked between the active fin and the conductive structure.

In example embodiments, the source/drain layer may be an epitaxial layer doped with impurities.

In example embodiments, the source/drain layer may include silicon-germanium or silicon carbide.

In example embodiments, the active fin includes first portions each extending in a first direction parallel to the upper surface of the substrate and a second direction parallel to the upper surface of the substrate and substantially perpendicular to the first direction. Each of the second portions may be extended, and the first and second portions may have their ends connected to each other.

In example embodiments, the active fin may extend in a wave shape.

A semiconductor device according to embodiments for achieving another object of the present invention includes a substrate, a first active fin, a first guard ring, and a moisture barrier structure. The substrate includes a first area, a second area surrounding the first area, and a third area surrounding the second area. The first active fin is formed on a first region of the substrate. The first guard ring is formed on a second active fin formed on the second region of the substrate and continuously surrounding the first region in a curved shape when viewed from the top, and is formed on the second active fin to form the second active fin. and a first conductive structure surrounding the first region. The moisture barrier structure is formed on the third region and includes a third active fin that continuously surrounds the second region in a curved shape when viewed from the top, and a third active fin that covers the third active fin and surrounds the second region. a second gate structure; and a second conductive structure formed on the second gate structure to surround the second region.

In example embodiments, each of the second and third active fins may be formed in plurality, and the first conductive structure is formed on two second active fins adjacent to each other among the plurality of second active fins. may be formed, and the second gate structure may cover two third active fins adjacent to each other among the plurality of third active fins.

In example embodiments, the two second active fins adjacent to each other and the two third active fins adjacent to each other may be parallel to each other, respectively.

In example embodiments, the first conductive structure includes a first contact plug formed on the second active fin to surround the first region, and a first contact plug formed on the first contact plug to surround the first region. may include a first via surrounding the , wherein the second conductive structure is formed on the first gate structure, a second contact plug surrounding the second region, and on the second contact plug and a second via surrounding the second region.

In example embodiments, the first and second contact plugs may include a material substantially the same as each other, and upper surfaces thereof may be positioned at a substantially same height, and the first and second vias may include substantially the same material as each other. material may be included.

In example embodiments, each of the first to third active fins, the first and second conductive structures, and the second gate structure may be formed in plurality, and the semiconductor device includes the plurality of first and a metal plate formed on the second conductive structures.

In example embodiments, the semiconductor device may further include a source/drain layer and a metal silicide pattern sequentially stacked between the second active fin and the first conductive structure.

In example embodiments, the semiconductor device may further include a blocking layer pattern including an insulating material between the second gate structure and the second conductive structure.

In example embodiments, the second gate structure may include a second gate insulating layer pattern and a second gate electrode sequentially stacked on the third active fin.

In example embodiments, the first active fin may extend in a first direction parallel to the upper surface of the substrate, and the second active fin may include first portions each extending in the first direction and the and second portions each extending in a second direction parallel to the upper surface of the substrate and substantially perpendicular to the first direction, and ends of the first and second portions may be connected to each other.

In example embodiments, the third active fin may include third portions respectively extending in the first direction and fourth portions extending in the second direction, respectively, and the third and third The 4 parts may have their ends connected to each other.

In example embodiments, the semiconductor device may further include a first gate structure including a first gate insulating layer pattern sequentially stacked on the first active fin and a first gate electrode.

In example embodiments, the first and second gate structures may include substantially the same material.

In example embodiments, each of the second and third active fins may extend in a wave shape.

In example embodiments, the third active fin may be formed in plurality, and the semiconductor device is formed on at least one of the plurality of third active fins and the at least one third active fin. A second guard ring including a third conductive structure surrounding the second region may be further included.

In example embodiments, the first region may be a chip region in which a semiconductor chip is formed, and the second and third regions may be a sealing region surrounding and protecting the chip region.

In the method of manufacturing a semiconductor device according to embodiments for achieving another object of the present invention, the method includes a first region, a second region surrounding the first region, and a third region surrounding the second region. A device isolation layer pattern is formed on a substrate to form a device isolation layer pattern, and a field region whose upper surface is covered by the device isolation layer pattern and the first to third active fins protruding above the device isolation layer pattern without a top surface not covered by the device isolation layer pattern are respectively formed on the first to third regions. In this case, the second active fin is formed to continuously surround the first region in a curved shape when viewed from the top, and the third active fin continuously surrounds the second region in a curved shape when viewed from the top. is formed to A second gate structure is formed to cover the third active fin and surround the second region. First and second conductive structures respectively surrounding the first and second regions are formed on the second active fin and the second gate structure, respectively.

In example embodiments, when the first to third active fins are formed on the first to third regions of the substrate, first to third regions on the first to third regions of the substrate, respectively 3 masks can be formed. By etching the substrate using the first to third masks as etch masks, first to third trenches may be formed on the first to third regions of the substrate. A device isolation layer sufficiently filling the first to third trenches may be formed on the substrate. The device isolation layer may be planarized through a mechanical chemical polishing (CMP) process until the top surface of the substrate is exposed. An upper portion of the device isolation layer may be removed.

In example embodiments, when the first to third masks are respectively formed on the first to third regions of the substrate, a mask layer may be formed on the substrate. First to third sacrificial layer patterns are formed on the first to third regions on the mask layer, and the second and third sacrificial layer patterns are respectively curved in the first and second regions. It may be formed so as to continuously surround it. First to third spacers may be respectively formed on both sidewalls of the first to third sacrificial layer patterns. After removing the first to third sacrificial layer patterns, the mask layer may be etched using the first to third spacers as etch masks.

In example embodiments, each of the second and third active fins may be formed in plurality, and when the second gate structure is formed, two third active fins adjacent to each other among the plurality of third active fins may be formed. The second gate structure may be formed to cover the active fins. When forming the first conductive structure, the first conductive structure may be formed on two second active fins adjacent to each other among the plurality of second active fins.

In example embodiments, the two second active fins adjacent to each other and the two third active fins adjacent to each other may be formed to be parallel to each other, respectively.

In example embodiments, each of the first active fins may extend in a first direction substantially parallel to the upper surface of the substrate, and may extend in a first direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction. It may be formed in plurality in two directions.

In example embodiments, when forming the second gate structure, a first gate structure extending in the second direction may be formed on the first active fins and the device isolation layer pattern.

In example embodiments, when the first and second conductive structures are formed, first and second regions surrounding the first and second regions on the second active fin and the second gate structure, respectively Contact plugs may be formed. First and second vias may be formed on the first and second contact plugs to surround the first and second regions, respectively.

In the semiconductor device manufacturing method according to the exemplary embodiments, the active fins formed in the sealing region extend in a curved shape instead of linearly, so that the double patterning process for forming these fine patterns can be stably performed. have. In addition, by forming the active fins not only in the chip area but also in the sealing area, a planarization process performed later may be easily performed. On the other hand, the guard ring and the moisture preventing structure can be easily formed in the sealing region through the same process as the transistor formed in the chip region, and the guard ring and the moisture preventing structure are stably formed to provide a ground function and moisture and moisture resistance. It can faithfully perform the shock propagation prevention function.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 to 4 are plan views and cross-sectional views for explaining the moisture prevention structure and the first guard ring according to exemplary embodiments, and FIGS. 5 to 11 illustrate the structure of the moisture prevention structure and the first guard ring These are enlarged floor plans for
12 to 16 are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments.
17 to 65 are plan views and cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 to 4 are plan and cross-sectional views for explaining a moisture blocking structure and a first guard ring according to example embodiments, and FIGS. 5 to 11 are the moisture blocking structure and It is an enlarged plan view for explaining the structure of the first guard ring. Specifically, FIG. 1 is a plan view for explaining the moisture preventing structure and the first guard ring, and FIGS. 2 to 4 are cross-sectional views taken along line L-L' of FIG. 1 . 5 and 7 to 11 are enlarged plan views of region Z of FIG. 1 , and FIG. 6 is an enlarged plan view of region Y of FIG. 1 .

Referring first to FIGS. 1 to 3 and 5 to 7 , the first guard ring 404 and the first moisture barrier structure 406 are formed in the second region II of the substrate 100 .

The substrate 100 may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a group III-V compound such as GaP, GaAs, and GaSb. According to some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The substrate 100 may include first and second regions I and II, and the second region II may include third and fourth regions III and IV. Also, the third region III may include fifth to seventh regions V, VI, and VII, and the fourth region IV includes eighth to tenth regions VIII, IX, and X. may include.

In this case, the first region I may be a chip region in which a semiconductor chip is formed, and the second region II may be a sealing region surrounding and protecting the semiconductor chip. Among the second regions II, the third region III may be a guard ring region in which a first guard ring 404 for grounding the semiconductor chip is formed, and the fourth region IV is disposed on a wafer. A first moisture-preventing structure 406 protecting the semiconductor chips so that moisture does not penetrate or crack the semiconductor chips in a dicing process for separating the semiconductor chips after manufacturing them. It may be a formed region.

On the other hand, the third region III may surround the first region I, and although illustrated to have an octagonal shape exemplarily in the drawings, the present invention is not limited thereto, and may surround the first region I. Any shape is possible if possible. When the third region III has the octagonal shape, a fifth region V extending in a first direction substantially parallel to the upper surface of the substrate 100 , substantially parallel to the upper surface of the substrate 100 and extending in the second direction A sixth region VI extending in a second direction substantially perpendicular to the first direction, and a direction connecting the fifth and sixth regions V and VI and forming an acute angle with the first and second directions It may include a seventh region (VII) extending to

In addition, the fourth region IV may surround the third region III, and in the drawing, an exemplary rectangular shape and a bar shape extending to cover the outside of the seventh region VII in addition to the rectangular shape are shown in the drawing. Although shown to have, it is not necessarily limited thereto, and any shape is possible as long as it can surround the third region III. The fourth region IV illustrated in the drawing includes an eighth region VII extending in the first direction, a ninth region IX extending in the second direction, and the eighth and ninth regions. A tenth region (X) connected to (VIII, IX) and extending in substantially the same direction as the seventh region (VII) may be included.

The first guard ring 404 may be formed on the third region III of the substrate 100 and may continuously surround the first region I in a curved shape when viewed from the top.

In example embodiments, the first guard ring 404 may include first portions extending in the first direction and second portions extending in the second direction, each of the first portions extending in the second direction. Both ends and both ends of the second parts may have a shape connected to each other.

In example embodiments, the first guard ring 404 may be formed in plurality, and they may be arranged in an outward direction from the center of the first region (I). Since each of the first guard rings 404 extends in a curved shape, irregularities may be formed, and in one embodiment, a concave portion formed in one first guard ring 404 based on the same direction. and the convex part may be disposed to face each of the convex part and the concave part formed in the other first guard ring 404 adjacent thereto. However, the concept of the present invention is not necessarily limited thereto. That is, referring to FIG. 10 , the concave portion and the convex portion formed in one first guard ring 404 may be disposed to face the concave portion and the convex portion formed in the other adjacent guard ring 404 , respectively. . Also, the concave portions and the convex portions included in the first guard rings 404 may not exactly correspond to each other along one direction.

In other embodiments, referring to FIG. 8 , the first guard ring 404 includes third and fourth portions extending in third and fourth directions forming an acute angle with the first and second directions, respectively. and may have a shape in which both ends of the third parts and both ends of the fourth parts are connected to each other.

In still other embodiments, referring to FIG. 9 , the first guard ring 404 may extend in a curved shape instead of a straight line, for example, a wave type.

That is, the first guard ring 404 may have any curved shape other than a straight line or a bar shape in each of the fifth to seventh regions V, VI, and VII.

In example embodiments, the first guard ring 404 may include a second active fin 104 and a first conductive structure sequentially stacked on the third region III of the substrate 100 . . In this case, the second active fin 104 may continuously surround the first region I in a curved shape, and the first conductive structure may have a shape corresponding to the second active fin 104 . Since the second active fin 104 has a curved shape rather than a straight shape, as will be described later, a mandrel or a mask spacer can be stably formed without collapsing during the double patterning process for forming it, In addition, polishing stress may be efficiently dispersed in a mechanical chemical polishing (CMP) process for forming the device isolation layer pattern 125 , so that the second active fin 104 may be stably formed.

The second active fin 104 may protrude above the substrate 100 , a lower sidewall may be covered by the device isolation layer pattern 125 , and the upper portion may protrude onto the device isolation layer pattern 125 . Second spacers 184 including, for example, a nitride such as silicon nitride or an oxide such as silicon oxide may be formed on both sidewalls of the second active fin 104 .

The second active fin 104 may include substantially the same material as the substrate 100 . In an embodiment, the second active fin 104 may be doped with an impurity such as boron or phosphorus.

In example embodiments, a plurality of second active fins 104 may be formed along an outward direction from the center of the first region I, among which two second active fins 104 are adjacent to each other. One of the first conductive structures may be formed thereon.

The first conductive structure may include a first contact plug 294 and a first via 314 sequentially stacked. The first contact plug 294 is formed on the first interlayer insulating layer 200 formed on the substrate 100 while covering the second active fin 104 and the second spacer 184 and on the first interlayer insulating layer 200 . The formed second interlayer insulating layer 270 may be penetrated. The first via 314 may pass through the third interlayer insulating layer 300 formed on the second interlayer insulating layer 270 . The first contact plug 294 and the first via 314 may include a metal such as tungsten, copper, aluminum, or doped polysilicon.

In example embodiments, a plurality of first conductive structures may be formed along an outward direction from the center of the first region I, and a metal plate 320 may be formed on the plurality of first conductive structures. ) can be formed. Accordingly, the plurality of first conductive structures may be electrically connected to each other through the metal plate 320 . That is, through the first guard ring 404 including the second active pin 104 , the first contact plug 294 and the first via 314 , the metal plate 320 and other upper wirings ( (not shown) may be grounded to the substrate 100 .

Meanwhile, a second source/drain layer 204 and a second metal silicide pattern 284 may be further formed between the second active fin 104 and the first contact plug 294 .

The second source/drain layer 204 may be formed on the second active fin 204 and the second spacer 104 , and may be epitaxially grown (SEG) using the second active fin 204 as a seed. It can be formed by performing a process. In example embodiments, the second source/drain layer 204 may be a single crystal silicon-germanium layer doped with an impurity, a silicon carbide layer doped with an impurity, a silicon layer doped with an impurity, or the like.

The second metal silicide pattern 284 may be formed by reacting the second source/drain layer 204 with a metal layer. The second metal silicide pattern 284 may include, for example, cobalt silicide, nickel silicide, or the like.

The second source/drain layer 204 and the second metal silicide pattern 284 may not be formed in some cases and may be omitted. In this case, the first contact plug 294 is directly connected to the second active fin 104 . can be contacted

The first moisture barrier structure 406 may be formed on the fourth region IV of the substrate 100 and may continuously surround the third region III in a curved shape when viewed from the top.

The first moisture barrier structure 406 may have a shape similar to that of the first guard ring 404 when viewed from the top. That is, for example, referring to FIG. 11 , the first moisture barrier structure 406 formed in the eighth region IIIV may have a shape similar to that of the first guard ring 404 described with reference to FIG. 5 . . Accordingly, the first moisture barrier structure 406 may include fifth portions extending in the first direction and sixth portions extending in the second direction, and both ends of the fifth portions and the second portion Each both ends of the 6 parts may have a shape connected to each other. In addition, the shape of the portion of the first moisture barrier structure 406 formed in the ninth and tenth regions IX and X is that of the portion of the first guard ring 404 formed in the fifth and sixth regions V and VI. Each may be similar to the shape.

The first moisture preventing structure 406 may be formed in plurality and may be arranged in an outward direction from the center of the first region (I). In addition, the first moisture-preventing structure 406 may extend in a curved shape instead of a straight line, for example, in a wave shape. That is, the first moisture-preventing structure 406 may have any curved shape other than a straight line or a bar shape in each of the eighth to tenth regions IIIV, IX, and X. .

In example embodiments, the first moisture barrier structure 406 includes the third active fin 106 , the second gate structure 256 and the third active fin 106 sequentially stacked on the fourth region IV of the substrate 100 , and A second conductive structure may be included.

In this case, the third active fin 106 may continuously surround the third region III in a curved shape, and the second gate structure 256 and the second conductive structure are connected to the third active fin 106 . It may have a corresponding shape. Since the third active fin 106 has a curved shape rather than a linear shape, a mandrel or a mask spacer can be stably formed without falling over during the double patterning process for forming the third active fin 106, and also the device isolation layer pattern ( In the mechanical chemical polishing (CMP) process for forming 125 , polishing stress is also efficiently dispersed, so that the third active fin 106 may be stably formed.

The third active fin 106 may protrude above the substrate 100 , a lower sidewall may be covered by the device isolation layer pattern 125 , and the upper portion may protrude onto the device isolation layer pattern 125 . The third active fin 106 may include substantially the same material as the substrate 100 and the second active pattern 104 . In an embodiment, the third active fin 106 may be doped with an impurity such as boron or phosphorus.

In example embodiments, a plurality of third active fins 106 may be formed along an outward direction from the center of the first region I, among which two third active fins 106 are adjacent to each other. One second gate structure 256 may be formed to cover the . In this case, the second gate structure 256 may also cover a portion of the device isolation layer pattern 125 between the two third active fins 106 and portions of the device isolation layer pattern 125 adjacent to the outside thereof.

The second gate structure 256 may include a second interface layer pattern 226 , a second gate insulating layer pattern 236 , and a second gate electrode 246 sequentially stacked on the third active fin 106 . have. Meanwhile, second gate spacers 176 may be formed on both sidewalls of the second gate structure 256 , and second blocking layer patterns ( 266) can be formed.

The second interface layer pattern 226 may include, for example, an oxide such as silicon oxide. In an embodiment, the second interface layer pattern 226 may be formed only on the top surface of the third active pattern 106 . Alternatively, although not shown, the second interface layer pattern 226 may be formed on the device isolation layer pattern 125 as well as the third active pattern 106 . Alternatively, the second interface layer pattern 226 may not be formed.

The second gate insulating layer pattern 236 may include, for example, a metal oxide having a high dielectric constant, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), or zirconium oxide (ZrO2). The second gate insulating layer pattern 236 may be formed on inner walls of the second interface layer pattern 226 , the device isolation layer pattern 125 , and the second gate spacer 176 , and of the second gate electrode 246 . It can cover the bottom and side walls.

The second gate electrode 246 may include, for example, a low-resistance metal such as a metal such as aluminum (Al), copper (Cu), or tantalum (Ta), or polysilicon doped with impurities.

Meanwhile, the second gate structure 256 has a dummy gate insulating layer pattern including, for example, silicon oxide instead of the second interface layer pattern 226 , the second gate insulating layer pattern 236 , and the second gate electrode 246 . (not shown) and a dummy gate electrode (not shown) including polysilicon.

The second gate spacer 176 and the second blocking layer pattern 266 may include, for example, a nitride such as silicon nitride.

The second conductive structure may include a second contact plug 296 and a second via 316 sequentially stacked. The second contact plug 296 may penetrate the second interlayer insulating layer 270 . The second via 316 may pass through the third interlayer insulating layer 300 . The second contact plug 296 and the second via 316 are made of substantially the same material as the first contact plug 294 and the first via 314 , that is, a metal such as tungsten, copper, aluminum, or doped polysilicon. may include

In example embodiments, a plurality of second conductive structures may be formed along an outward direction from the center of the first region I, and upper surfaces thereof may contact the metal plate 320 . Accordingly, the plurality of second conductive structures may be electrically connected to each other through the metal plate 320 , and may also be electrically connected to the first conductive structures.

A first moisture barrier structure 406 including a third active fin 106 , a second gate structure 256 , a second blocking layer pattern 266 , a second contact plug 296 , and a second via 316 . In this case, since the second gate structure 256 is formed to cover the two third active fins 106 , the moisture inflow path from the outside is lengthened to effectively block moisture and effectively prevent shock propagation from the outside. .

Meanwhile, referring to FIG. 4 , the second moisture barrier structure 407 may not include a blocking layer pattern on the second gate structure 256 , and in this case, the second gate structure 256 may include the fourth gate structure 256 . It may be in direct contact with the contact plug 297 .

So far, it has been described that the guard ring is formed only on the third region III of the substrate 100 , but the guard ring may also be formed on the fourth region IV of the substrate 100 , which is the second guard ring. It will be referred to as a ring (not shown). That is, the second guard ring may be formed to include the third active fin 106 , the first contact plug 294 , and the first via 314 that are sequentially stacked, and the fourth region of the substrate 100 . Formed on the (IV) phase, it can perform not only the function of grounding current, but also the function of preventing moisture and shock propagation.

12 to 16 are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments. Specifically, FIG. 12 is a plan view for explaining the semiconductor device, FIG. 13 is an enlarged cross-sectional view including enlarged cross-sections of regions X, Y, and Z of FIG. 12 , and FIGS. 14 to 16 are AA′ of FIG. 13 . , BB' and C-C' are cross-sectional views, respectively. Since the semiconductor device includes the first moisture preventing structure and the first guard ring described with reference to FIGS. 1 to 11 , the same reference numerals are assigned to the same components, and a detailed description thereof will be omitted.

12 to 16 , the semiconductor device includes a transistor formed on a substrate 100 , a first guard ring 404 , and a first moisture barrier structure 406 .

The substrate 100 may include first to tenth regions I to X. In this case, the first region I may be a chip region in which the semiconductor chip including the transistor is formed, and the second region II may be a sealing region that surrounds and protects the semiconductor chip. Also, the third region III of the second region II may be a guard ring region in which a first guard ring 404 for grounding the semiconductor chip is formed, and the fourth region IV is the semiconductor chip. It may be a region in which the first moisture-preventing structure 406 protecting the semiconductor chips is formed so that moisture does not penetrate or cracks do not occur.

The transistor includes a first active fin 102 formed on the first region I of the substrate 100 , a first gate structure 252 formed on the first active fin 102 , and a first gate structure 252 . ) and a first source/drain layer 202 formed on the first active fin 102 to be adjacent.

In example embodiments, the first active fins 102 may extend in a first direction substantially parallel to the upper surface of the substrate 100 , and may extend in the first direction and substantially parallel to the upper surface of the substrate 100 . and may be formed in plurality in a second direction substantially perpendicular to the first direction. First spacers 182 including, for example, a nitride such as silicon nitride or an oxide such as silicon oxide may be formed on both sidewalls of the first active fin 102 .

The first gate structure 252 may include a first interface layer pattern 222 , a first gate insulating layer pattern 232 , and a first gate electrode 242 sequentially stacked on the first active fin 102 . have. Meanwhile, first gate spacers 172 may be formed on both sidewalls of the first gate structure 252 , and first blocking layer patterns ( 262) can be formed. However, the first blocking layer pattern 262 may not be formed.

The first interface layer pattern 222 may include, for example, an oxide such as silicon oxide. In an embodiment, the first interface layer pattern 222 may be formed only on the upper surface of the first active pattern 102 . Alternatively, although not shown, the first interface layer pattern 222 may be formed on the device isolation layer pattern 125 as well as the first active pattern 102 . Alternatively, the first interface layer pattern 222 may not be formed.

The first gate insulating layer pattern 232 may include, for example, a metal oxide having a high dielectric constant, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), or zirconium oxide (ZrO2). The first gate insulating layer pattern 232 may be formed on inner walls of the first interface layer pattern 222 , the device isolation layer pattern 125 , and the first gate spacer 172 , and of the first gate electrode 242 . It can cover the bottom and side walls.

The first gate electrode 242 may include, for example, a low-resistance metal such as a metal such as aluminum (Al), copper (Cu), or tantalum (Ta), or polysilicon doped with impurities. The first gate spacer 172 and the first blocking layer pattern 262 may include, for example, a nitride such as silicon nitride.

The first source/drain layer 202 may be formed on the first active fin 102 and the first spacer 182 , and may be epitaxially grown (SEG) using the first active fin 102 as a seed. It can be formed by performing a process. In example embodiments, the first source/drain layer 202 may be a single crystal silicon-germanium layer doped with an impurity, a silicon carbide layer doped with an impurity, a silicon layer doped with an impurity, or the like.

A first metal silicide pattern 282 may be formed on the first source/drain layer 202 . The first metal silicide pattern 282 may include, for example, cobalt silicide, nickel silicide, or the like.

The transistor may be formed inside the first interlayer insulating layer 200 , and second and third interlayer insulating layers 270 and 300 may be sequentially stacked on the first interlayer insulating layer 200 . A third contact plug 292 may be formed through the first and second interlayer insulating layers 200 and 270 to contact the first metal silicide pattern 282 , and penetrate through the third interlayer insulating layer 300 to contact the first metal silicide pattern 282 . A third via 316 contacting the third contact plug 292 may be formed. The third contact plug 292 and the third via 316 may include, for example, a metal such as tungsten, copper, aluminum, or doped polysilicon. A metal plate 320 may be formed on an upper surface of the third via 316 .

Although not shown, a fifth contact plug (not shown) passing through the first and second interlayer insulating layers 200 and 270 and contacting the first gate structure 252 and the third interlayer insulating layer 300 are formed A fifth via (not shown) may be further formed to pass through and contact the upper surface of the fifth contact plug and the lower surface of the metal plate 320 .

Meanwhile, the first guard ring 404 may be formed on the third region III of the substrate 100 and may continuously surround the first region I in a curved shape when viewed from the top. The first guard ring 404 may have any curved shape other than a straight line or a bar shape in each of the fifth to seventh regions V, VI, and VII.

In example embodiments, the first guard ring 404 may include a second active fin 104 and a first conductive structure sequentially stacked on the third region III of the substrate 100 . . In this case, the second active fin 104 may continuously surround the first region I in a curved shape, and the first conductive structure may have a shape corresponding to the second active fin 104 .

The second active fin 104 may protrude above the substrate 100 , and may include substantially the same material as the substrate 100 and the first active fin 102 . In an embodiment, the second active fin 104 may be doped with an impurity such as boron or phosphorus. Second spacers 184 may be formed on both sidewalls of the second active fin 104 . In this case, the second spacer 184 may include substantially the same material as the first spacer 182 .

The first conductive structure may include a first contact plug 294 and a first via 314 sequentially stacked. The first contact plug 294 and the first via 314 may include substantially the same material as the third contact plug 292 and the third via 312 .

In example embodiments, a plurality of first conductive structures may be formed along an outward direction from the center of the first region I, and a metal plate 320 may be formed on the plurality of first conductive structures. ) can be formed. Accordingly, the plurality of first conductive structures may be electrically connected to each other through the metal plate 320 , and may also be electrically connected to the third via 312 and the third contact plug 292 . Accordingly, the metal plate 320 and the chip region I connected thereto through the first guard ring 404 including the second active pin 104 , the first contact plug 294 and the first via 314 . ) and other upper wirings (not shown) may be grounded to the substrate 100 .

Meanwhile, a second source/drain layer 204 and a second metal silicide pattern 284 may be further formed between the second active fin 104 and the first contact plug 294 . In this case, the second source/drain layer 204 and the second metal silicide pattern 284 may include substantially the same material as the first source/drain layer 202 and the first metal silicide pattern 282 . However, the second source/drain layer 204 and the second metal silicide pattern 284 may not be formed in some cases and may be omitted. In this case, the first contact plug 294 is formed by the second active fin 104 . can be contacted directly.

The first moisture barrier structure 406 may be formed on the fourth region IV of the substrate 100 and may continuously surround the third region III in a curved shape when viewed from the top. The first moisture barrier structure 406 may have any shape other than a straight line or a bar shape in each of the eighth to tenth regions IIIV, IX, and X, and may have any curved shape.

In example embodiments, the first moisture barrier structure 406 includes the third active fin 106 , the second gate structure 256 and the third active fin 106 sequentially stacked on the fourth region IV of the substrate 100 , and A second conductive structure may be included. In this case, the third active fin 106 may continuously surround the third region III in a curved shape, and the second gate structure 256 and the second conductive structure are connected to the third active fin 106 . It may have a corresponding shape.

The third active fin 106 may protrude above the substrate 100 , a lower sidewall may be covered by the device isolation layer pattern 125 , and the upper portion may protrude onto the device isolation layer pattern 125 . The third active fin 106 may include substantially the same material as the substrate 100 and the first and second active patterns 102 and 104 . In an embodiment, the third active fin 106 may be doped with an impurity such as boron or phosphorus.

The second gate structure 256 may include a second interface layer pattern 226 , a second gate insulating layer pattern 236 , and a second gate electrode 246 sequentially stacked on the third active fin 106 . have. Meanwhile, second gate spacers 176 may be formed on both sidewalls of the second gate structure 256 , and second blocking layer patterns ( 266) can be formed.

The second interface layer pattern 226 , the second gate insulating layer pattern 236 , and the second gate electrode 246 are the first interface layer pattern 222 , the first gate insulating layer pattern 232 , and the first gate electrode 242 . ) and each substantially the same material. However, the second gate structure 256 has a dummy gate insulating layer pattern including, for example, silicon oxide instead of the second interface layer pattern 226 , the second gate insulating layer pattern 236 , and the second gate electrode 246 . (not shown) and a dummy gate electrode (not shown) including polysilicon.

The second gate spacer 176 and the second blocking layer pattern 266 may include substantially the same material as the first gate spacer 172 and the first blocking layer pattern 262 , respectively.

The second conductive structure may include a second contact plug 296 and a second via 316 sequentially stacked. The second contact plug 296 and the second via 316 may include substantially the same material as the first contact plug 294 and the first via 314 .

In example embodiments, a plurality of second conductive structures may be formed along an outward direction from the center of the first region I, and upper surfaces thereof may contact the metal plate 320 . Accordingly, the plurality of second conductive structures may be electrically connected to each other through the metal plate 320 , and the first conductive structures and the third via 312 and the third contact plug ( 292) may also be electrically connected.

A first moisture barrier structure 406 including a third active fin 106 , a second gate structure 256 , a second blocking layer pattern 266 , a second contact plug 296 , and a second via 316 . In this case, since the second gate structure 256 is formed to cover the two third active fins 106 , the moisture inflow path from the outside is lengthened to effectively block moisture and effectively prevent shock propagation from the outside. .

In an embodiment, the first moisture barrier structure 406 may not include the second blocking layer pattern 266 on the second gate structure 256 , and in this case, the second gate structure 256 . The second contact plug 296 may be in direct contact.

Meanwhile, a second guard ring (not shown) may be formed on the fourth region IV of the substrate 100 . In this case, the second guard ring may be formed to include a third active fin 106 , a first contact plug 294 , and a first via 314 that are sequentially stacked, and a fourth region of the substrate 100 . Formed on the (IV) phase, it can perform not only the function of grounding current, but also the function of preventing moisture and shock propagation.

17 to 65 are plan views and cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments. Specifically, FIGS. 17, 19, 22, 27, 31, 35, 39, 43, 47, 51, 54, 57, and 61 are plan views for explaining steps of the method of manufacturing the semiconductor device, and FIGS. 18 and 20-21 . , 23-26, 28, 32, 36, 40, 44, 48, 52, 55, 58 and 62 are cross-sectional views taken along line A-A' of corresponding respective plan views, and FIGS. 29, 33, 37, 41 , 45, 50, 59, 63 and 65 are cross-sectional views taken along line B-B' of corresponding respective plan views, and FIGS. 30, 34, 38, 42, 46, 49, 53, 56, 60 and 64 are corresponding These are cross-sectional views taken along the line C-C' of each of the plan views. However, in each of FIGS. 31, 35, 39, 43, 47, 51, 54, 57 and 61, instead of showing an entire plan view for convenience of explanation, X in each of the first, third and fourth regions, It shows enlarged cross-sectional views of the Y and Z regions.

The method of manufacturing the semiconductor device may be used for manufacturing the semiconductor device described with reference to FIGS. 12 to 17 , but is not limited thereto.

17 to 18 , a mask layer 500 is formed on the substrate 100 , and first to third sacrificial layer patterns 512 , 514 , and 516 are first formed on the mask layer 500 . , formed on the third and fourth regions I, III, and IV, respectively. The first to third sacrificial layer patterns 512 , 514 , and 516 may serve as mandrels in the double patterning process.

In example embodiments, the first sacrificial layer pattern 512 may extend in the first direction, and the second and third sacrificial layer patterns 514 and 516 may be in the first and third regions, respectively. It may be formed to continuously surround the ones (I, III) in a curved shape. In this case, each of the first to third sacrificial layer patterns 512 , 514 , and 156 may be formed in plurality.

Since the first sacrificial layer pattern 512 linearly extends in the first direction, it may fall over when formed to have a length greater than a predetermined length. Accordingly, since it is difficult to form one first sacrificial layer pattern 512 to cross the first region I in the first direction, a plurality of first sacrificial layer patterns 512 are formed along the first direction. On the other hand, since each of the second and third sacrificial layer patterns 514 and 516 extends curvedly rather than linearly in one direction, they may be stably formed without falling over even if they have a long overall length.

The mask layer 500 may include, for example, a nitride such as silicon nitride, and the first to third sacrificial layer patterns 512 , 514 , and 516 may include, for example, polysilicon or an amorphous carbon layer. Layer: ACL), spin-on organic hardmask (SOH), etc. may be formed to include.

19 to 20 , first to third mask spacers 522 , 524 , and 526 may be formed on both sidewalls of the first to third sacrificial layer patterns 512 , 514 , and 516 , respectively. .

In example embodiments, the first to third mask spacers 522 , 524 , and 526 may be a mask spacer layer covering the first to third sacrificial layer patterns 512 , 514 , and 516 for the mask layer 500 . ), after conformally formed on it, it can be formed by anisotropic etching. Accordingly, each of the first to third mask spacers 522 , 524 , and 526 may be formed to have a width smaller than the width of the first to third sacrificial layer patterns 512 , 514 , and 516 . Although the first to third mask spacers 522 , 524 , and 526 have a smaller width than the first to third sacrificial layer patterns 512 , 514 , and 516 , the first to third sacrificial layer patterns ( 512, 514, and 516), it can be formed stably without falling down.

Meanwhile, the mask spacer layer may be formed through, for example, an atomic layer deposition (ALD) process using an oxide.

Referring to FIG. 21 , after removing the first to third sacrificial layer patterns 512 , 514 , and 516 , the first to third mask spacers 522 , 524 , and 526 are used as etch masks to form a lower mask. By etching the layer 500 , first to third masks 502 , 504 , and 506 may be formed on the first, third, and fourth regions I, III, and IV, respectively.

In example embodiments, the first to third sacrificial layer patterns 512 , 514 , and 516 may be removed through a wet etching process or a dry etching process, and the mask layer 500 may be removed through a dry etching process. can be etched.

In example embodiments, the first to third masks 502 , 504 , and 506 may be formed to have the same shape as the first to third mask spacers 522 , 524 , and 526 , respectively.

22 to 23 , the first to third active fins 102 and 104 are etched by etching the lower substrate 100 using the first to third masks 502 , 504 and 506 as etch masks. , 106 are formed on the first, third, and fourth regions I, III, and IV, respectively. Accordingly, a first trench 110 may be formed between the first to third active fins 102 , 104 , and 106 on the substrate 100 . In the etching process, the first to third mask spacers 522 , 524 , and 526 may be removed.

The first to third active fins 102 , 104 , and 106 may be formed to have the same shape as the first to third masks 502 , 504 and 506 , respectively. That is, the first active fins 102 may extend along the first direction on the first region I of the substrate 100 and may be formed in plurality along the first and second directions. The second active fin 104 may be formed on the third region III of the substrate 100 to continuously surround the first region I in a curved shape, and may be formed in an outward direction from the first region I. may be formed in plurality. The third active fin 106 may be formed on the fourth region IV of the substrate 100 to continuously surround the third region III in a curved shape, and may be formed in an outward direction from the first region I. may be formed in plurality.

After the etching process, the first to third masks 502 , 504 , and 506 may be removed.

Referring to FIG. 24 , the device isolation layer 120 filling the first trench 110 is formed.

In example embodiments, after the device isolation layer 120 is formed on the substrate 100 , the device isolation layer 120 may be planarized until the upper surface of the substrate 100 is exposed. The device isolation layer 120 may be formed to include, for example, an oxide such as silicon oxide. The planarization process may be performed, for example, through a mechanical chemical polishing (CMP) process. When the mechanical chemical polishing (CMP) process is performed, the first to third active fins 102 , 104 , and 106 are formed on the first, third, and fourth regions I, III, and IV of the substrate 100 . Since these are formed respectively, there is little difference in the density of the structure between the first, third, and fourth regions I, III, and IV. Accordingly, the mechanical chemical polishing (CMP) process may be easily performed without occurrence of a dishing phenomenon.

Referring to FIG. 25 , the device isolation layer pattern 125 may be formed by removing the upper portion of the device isolation layer 120 so that the upper portion of the first trench 110 is exposed. In example embodiments, the etching process may be performed through an etch-back process.

As the device isolation layer pattern 125 is formed, each of the first, third, and fourth regions I, III, and IV of the substrate 100 has a field region whose upper surface is covered by the device isolation layer pattern 125 ; and an active region whose upper surface is not covered by the device isolation layer pattern 125 and protrudes upward from the device isolation layer pattern 125 may be defined.

Referring to FIG. 26 , a dummy gate insulating layer 130 , a dummy gate electrode layer 140 , and a hard mask layer 150 are sequentially formed on the substrate 100 on which the device isolation layer pattern 125 is formed.

The dummy gate insulating layer 130 may be formed to include an oxide such as silicon oxide, and the dummy gate electrode layer 140 may be formed to include, for example, polysilicon, and a hard mask layer ( 150) may be formed to include, for example, a nitride such as silicon nitride.

The dummy gate insulating layer 130 may be formed through a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like. Alternatively, the dummy gate insulating layer 130 may be formed through a thermal oxidation process on the upper portions of the first to third active fins 102 , 104 , and 106 of the substrate 100 . In this case, the dummy gate insulating layer 130 may be formed. ) may not be formed on the device isolation layer pattern 125 . Meanwhile, the dummy gate electrode layer 140 and the hard mask layer 150 may also be formed through a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like.

27 to 30 , the hard mask layer 150 is patterned through an etching process using a photoresist pattern (not shown) as an etching mask to form the first and second hard masks 152 and 156 . is formed on the first and fourth regions I and IV, respectively, and the lower dummy gate electrode layer 140 and the dummy gate insulating layer 130 are etched using this as an etch mask to etch the first and fourth regions. First and second dummy gate structures 162 and 166 are respectively formed in the regions I and IV.

In example embodiments, the first dummy gate structure 162 may extend to cover the first active fins 102 formed in the second direction, and the second dummy gate structure 166 may have a lower portion of the first dummy gate structure 166 . It may extend in a similar shape to cover the third active fins 106 . In example embodiments, the second dummy gate structure 166 covers two third active fins 106 adjacent to each other among the plurality of third active fins 106 , and a device isolation layer pattern ( 125) and a portion of the device isolation layer pattern 125 adjacent thereto in an outward direction may also be formed.

The first dummy gate structure 162 may be formed to include the sequentially stacked first dummy gate insulating layer pattern 132 , the first dummy gate electrode 142 , and the first hard mask 152 , and the second dummy The gate structure 166 may be formed to include the sequentially stacked second dummy gate insulating layer pattern 136 , the second dummy gate electrode 146 , and the second hard mask 156 .

Meanwhile, the second active fins 104 of the third region III may be exposed without being covered by the dummy gate structure.

Thereafter, an ion implantation process is performed to form an impurity region (not shown) on the first and second active fins 102 and 104 that are not covered by the first and second dummy gate structures 162 and 166 . can be formed

31 to 34 , first and second gate spacers 172 and 176 are formed on sidewalls of the first and second dummy gate structures 162 and 166, respectively, and first and second active First and second spacers 182 and 184 are formed on sidewalls of the fins 102 and 104 .

In example embodiments, the first and second gate spacers 172 and 176 , and the first and second spacers 182 and 184 are the first and second dummy gate structures 162 and 166 . , by forming a spacer layer on the first and second active fins 102 and 104 , and the device isolation layer pattern 125 and anisotropically etching the spacer layer. The spacer layer may be formed to include, for example, a nitride such as silicon nitride (SiN) or silicon oxycarbonitride (SiOCN).

35 to 38 , first and second dummy gate structures 162 and 166 , first and second gate spacers 172 and 176 , and first and second spacers 182 and 184 . ) as an etch mask to etch the upper portions of the first and second active fins 102 and 104 not covered by them, thereby forming the second and third trenches in the first and third regions I and III. forms 192 and 194, respectively.

The second and third trenches 192 and 194 may be formed to have a constant depth toward the inside of the substrate 100 .

Although it is shown in the drawing that the second and third trenches 192 and 194 are formed on the upper portion of the first and second active fins 102 and 104 whose sidewall is not covered by the device isolation layer pattern 125, The present invention is not necessarily limited thereto, and may be formed to extend under the first and second active fins 102 and 104 whose sidewalls are covered by the device isolation layer pattern 125 . In addition, the second and third trenches 192 and 194 may be formed to have various shapes, such as a square shape, a U shape, a partial shape of a circle, a sigma shape, etc. in cross-section.

Meanwhile, the etching process for forming the second and third trenches 192 and 194 may be performed in-situ with the anisotropic etching process for the spacer layer described with reference to FIGS. 31 to 34 . have.

39 to 42 , first and second source/drain layers 202 and 204 filling the second and third trenches 192 and 194, respectively, are formed.

In example embodiments, the first and second source/drain layers 202 , 204 are exposed by the second and third trenches 192 , 194 with the first and second active fins 102 , 104 . ) may be formed by performing a selective epitaxial growth (SEG) process using the upper surface of the seed as a seed.

In an embodiment, the selective epitaxial growth (SEG) process comprises a silicon source gas, such as _{dichlorosilane (SiH 2} Cl ₂ ) gas, and a germanium source, such as germanium _{(GeH 4 ) gas, for example.} This may be performed using a gas, and thus a single crystal silicon-germanium layer may be formed. In this case, in the selective epitaxial growth (SEG) process, a p-type impurity source gas, for example, diborane (B ₂ H ₆ ) gas, is used together to form a single crystal silicon-germanium layer doped with p-type impurities. can be formed. Accordingly, the first source/drain layer 202 may function as a source/drain region of a positive metal oxide semiconductor (PMOS) transistor.

In example embodiments, each of the first and second source/drain layers 202 and 204 may grow in vertical and horizontal directions, and the upper portion thereof may be formed to have a pentagonal or hexagonal cross-section. have. In this case, each of the first and second source/drain layers 202 and 204 has a top surface higher than a top surface of the first and second active fins 102 and 104, so that the so-called elevated source/drain layer (Elevated Source). /Drain: ESD) layer can be formed.

In other embodiments, the selective epitaxial growth (SEG) process may be formed using, for example, a silicon source gas such as disilane (Si2H6) gas and a carbon source gas such as SiH3CH3 gas, Accordingly, a single crystal silicon carbide (SiC) layer may be formed. Alternatively, the selective epitaxial growth (SEG) process may be formed using only a silicon source gas such as disilane (Si2H6) gas, and thus a single crystal silicon layer may be formed. In this case, an n-type impurity source gas, for example, a phosphine (PH3) gas, etc. may be used together to form a single crystal silicon carbide layer doped with impurities or a single crystal silicon layer doped with impurities. Accordingly, the first and source/drain layers 202 may function as a source/drain region of a Negative Metal Oxide Semiconductor (NMOS) transistor.

In still other embodiments, some of the plurality of first source/drain layers 202 may be formed to function as a source/drain region of a PMOS transistor, and other portions may be formed as a source/drain region of an NMOS transistor. It can be configured to perform a function.

43 to 46 , first and second dummy gate structures 162 and 166 , first and second gate spacers 172 and 176 , and first and second spacers 182 and 184 . , the first and second source/drain layers 202 and 204, and the first interlayer insulating layer 200 covering the device isolation layer pattern 125 are formed to a sufficient height, and then the first and second dummy gate structures ( The first interlayer insulating layer 200 is planarized until top surfaces of the first and second dummy gate electrodes 142 and 146 of the 162 and 166 are exposed. In this case, the first and second hard masks 152 and 156 formed on the first and second dummy gate electrodes 142 and 146 , and upper portions of the first and second gate spacers 172 and 176 . can also be removed. In example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process and/or an etch-back process.

47 to 49 , the exposed first and second dummy gate electrodes 142 and 146 and the first and second dummy gate insulating layer patterns 132 and 136 are removed to remove the first and third First and second openings 212 and 214 exposing upper surfaces of the active fins 102 and 106 and the portion of the device isolation layer pattern 125 adjacent thereto are formed, respectively.

In example embodiments, the first and second dummy gate electrodes 142 and 146 , and the first and second dummy gate insulating layer patterns 132 and 136 are first subjected to a dry etching process. , may be sufficiently removed by performing a second wet etching process, in which case the wet etching process may be performed using HF as an etchant.

Alternatively, referring to FIG. 50 , the second dummy gate electrode 146 and the second dummy gate are formed by forming a photoresist pattern (not shown) covering the fourth region IV and then performing the etching process. The insulating layer pattern 136 may not be removed. That is, in the chip region (I), a so-called gate replacement process for forming a gate electrode including a metal is performed in order to form a gate structure that actually operates as a transistor, but in the sealing region (II), the actual gate structure is actually formed. Since there is no need to operate as a transistor, the dummy gate structure may be maintained without performing the gate replacement process in the fourth region IV.

51 to 53 , a first interface layer pattern 222 , a first gate insulating layer pattern 232 , and a first gate electrode 242 are formed to fill each of the first openings 212 , and each A second interface layer pattern 226 , a second gate insulating layer pattern 236 , and a second gate electrode 246 are formed to fill the second openings 214 .

Specifically, the first and second thermal oxidation processes are performed on the upper surfaces of the first and third active fins 102 and 106 of the substrate 100 exposed by the first and second openings 212 and 214 . After the interface layer patterns 222 and 226 are formed, respectively, the first and second interface layer patterns 222 and 226 , inner walls of the first and second gate spacers 172 and 176 , and the first interlayer A gate insulating layer is formed on the insulating layer 200 , and a gate electrode layer sufficiently filling the remaining portions of the first and second openings 212 and 214 is formed on the gate insulating layer.

In example embodiments, the first and second interface layer patterns 222 and 226 may be formed to include silicon oxide, and the gate insulating layer may include, for example, hafnium oxide (HfO2), tantalum oxide ( Ta2O5) and zirconium oxide (ZrO2) may be formed to include a metal oxide having a high dielectric constant, and the gate electrode layer may be formed of a metal such as aluminum (Al), copper (Cu), tantalum (Ta), and the like. It may be formed to include the same low-resistance metal or polysilicon doped with impurities.

In example embodiments, the gate insulating layer and the gate electrode layer may be formed through a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or the like. However, the first and second interface layer patterns 222 and 226 are formed through a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, etc. instead of the thermal oxidation process. In this case, each of the first and second interface layer patterns 222 and 226 may be formed on the upper surfaces of the first and third active fins 102 and 106 of the substrate 100 as well as the device isolation layer pattern 125 . It may also be formed on the top surface and sidewalls of the first and second gate spacers 172 and 176 .

Meanwhile, the first and second interface layer patterns 222 and 226 may not be formed and may be omitted in some cases. In addition, a work function control layer may be further formed between the gate insulating layer and the gate electrode layer. The work function control layer is formed to include, for example, a metal nitride or an alloy such as titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), etc. can be

Thereafter, the gate electrode layer and the gate insulating layer are planarized until the top surface of the first interlayer insulating layer 200 is exposed, and the first and second gate electrodes 242 and 246 , and the first and second gates Insulation layer patterns 232 and 236 may be formed. In example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process and/or an etch-back process.

Accordingly, a first interface layer pattern 222 may be formed on the upper surface of the first active fin 102 exposed by each of the first openings 212 formed in the first region I, and the first interface layer may be formed. A first gate insulating layer pattern 232 may be formed on the top surface of the pattern 222 and the inner wall of the first gate spacer 172 , and a first gate electrode ( 242) may be formed. In addition, a second interface layer pattern 226 may be formed on the upper surface of the third active fin 106 exposed by each of the second openings 214 formed in the fourth region IV, and the second interface layer pattern A second gate insulating layer pattern 236 may be formed on the top surface of the 226 and the inner wall of the second gate spacer 176 , and the second gate electrode 246 filling the remaining portions of each of the second openings 214 . ) can be formed.

The first interface layer pattern 222 , the first gate insulating layer pattern 232 , and the first gate electrode 242 sequentially stacked may form a first gate structure 252 , and the first gate structure 252 . may form a PMOS transistor or an NMOS transistor together with the first source/drain layer 202 . In addition, the second interface layer pattern 226 , the second gate insulating layer pattern 236 , and the second gate electrode 246 sequentially stacked may form a second gate structure 256 .

In example embodiments, the first gate structure 252 formed to fill the first opening 212 may be formed to extend in the first direction, and may be formed to fill the second opening 214 . The second gate structure 256 may be formed to continuously surround the third region III in a curved shape.

54 to 56 , first and second blocking layer patterns 262 on the first and second gate structures 252 and 256 and on the first and second gate spacers 172 and 176 , 266), respectively.

The first and second blocking layer patterns 262 and 266 may be formed to include, for example, a nitride such as silicon nitride, and may not be formed in some cases and may be omitted.

57 to 60 , after forming the second interlayer insulating layer 270 on the first and second blocking layer patterns 262 and 266 and the first interlayer insulating layer 200 , the first and second Third to fifth openings 272 and 274 that penetrate through the insulating interlayers 200 and 270 to expose the first and second source/drain layers 202 and 204 and the second blocking layer pattern 266, respectively; 276) is formed.

In example embodiments, the fourth opening 274 may be formed to expose two second source/drain layers 204 adjacent to each other.

Thereafter, the exposed upper surfaces of the first and second source/drain layers 202 and 204 and the second blocking layer pattern 266 , the sidewalls of the third to fifth openings 272 , 274 and 276 , and the second interlayer insulating layer First and second metal silicide patterns 282 and 284 may be formed on the first and second source/drain layers 202 and 204 by annealing after forming a metal layer on the 270 , respectively. . Meanwhile, the non-reacted portion of the metal film may be removed.

61 to 64 , third to fifth openings 272 , 274 and 276 are formed on the first and second metal silicide patterns 282 and 284 and the second blocking layer pattern 266 , respectively. Filling first to third contact plugs 294 , 296 , and 292 may be formed. In this case, the first contact plug 294 may fill the fourth opening 274 and be formed on the second metal silicide pattern 284 , and the second contact plug 296 may fill the fifth opening 276 and fill the fifth opening 276 . The second blocking layer pattern 266 may be formed, and the third contact plug 292 may be formed on the first metal silicide pattern 282 to fill the third opening 272 .

In example embodiments, the first to third contact plugs 294 , 296 , and 292 include first and second metal silicide patterns 282 and 284 , a second blocking layer pattern 266 , and a second After forming a first conductive layer sufficiently filling the third to fifth openings 272 , 274 and 276 on the interlayer insulating layer 270 , the first conductive layer is formed until the top surface of the second interlayer insulating layer 270 is exposed. It can be formed by planarization. The first conductive layer may be formed to include, for example, doped polysilicon, metal, or metal nitride.

Meanwhile, referring to FIG. 65 , the second contact plug 296 may be formed to penetrate the second blocking layer pattern 266 and contact the upper surface of the second gate structure 256 .

12 to 16 again, a third interlayer insulating layer 300 is formed on the first to third contact plugs 294 , 296 , and 292 and the second interlayer insulating layer 270 , and the third interlayer insulating layer 300 passes therethrough. After forming sixth to eighth openings (not shown) exposing the first to third contact plugs 294 , 296 and 292 , respectively, first to third vias 314 and 316 , respectively filling them 312) is formed.

Thereafter, the semiconductor device may be completed by forming the metal plate 320 on the first to third vias 314 , 316 , and 312 .

As described above, in the method of manufacturing a semiconductor device according to exemplary embodiments, the second and third active fins 104 and 106 extend in a curved shape rather than linearly, thereby forming these fine patterns. It is possible to stably perform the double patterning process for In addition, by forming the second and third active fins 104 and 106 in the sealing region II as well as the chip region I, a planarization process performed later may be easily performed. Meanwhile, the first guard ring 404 and the first moisture barrier structure 406 may be easily formed in the sealing region II through the same process as the transistor formed in the chip region I.

The above-described moisture preventing structure and/or guard ring, a semiconductor device including the same, and a method for manufacturing the same may be used in various semiconductor devices requiring formation of a fine pattern having a width of about 25 nm or less. For example, the semiconductor device manufacturing method includes a logic device such as a central processing unit (CPU, MPU), an application processor (AP), etc., a volatile memory device such as an SRAM device, a DRAM device, and a flash memory. It may be applied to a nonvolatile memory device such as a device, a PRAM device, an MRAM device, and an RRAM device, and a method for manufacturing the same.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

100: substrate
102, 104, 106: first, second, third active pins
110, 192, 194, first, second, third trench
120: device isolation layer 125: device isolation layer pattern
130: dummy gate insulating film
132 and 136: first and second dummy gate insulating layer patterns
140: dummy gate electrode layers 142 and 146: first and second dummy gate electrodes
150: hard mask film 152, 156: first and second hard masks
162, 166: first and second dummy gate structures
172, 176: first and second gate spacers
182, 184: first and second spacers
200, 270, 300: first, second, and third interlayer insulating layers
212, 214, 272, 274, 276: first, second, third, fourth, fifth openings
222, 226; first and second interface layer patterns
232, 236: first and second gate insulating film patterns
242, 246: first and second gate electrodes
252, 256: first and second gate structures
262, 266: first and second blocking film patterns
282, 284: first and second metal silicide film patterns
294, 296, 292: first, second and third contact plugs
314, 316, 312: first, second, third via

Claims (44)

an active fin formed on the sealing region of a substrate including a chip region and a sealing region surrounding the chip region, the active fin continuously surrounding the chip region in a curved shape when viewed from the top;
a gate structure surrounding the chip region while covering the active fin; and
a conductive structure formed on the gate structure and surrounding the chip region;
The active pin is
first portions respectively extending in a first direction parallel to the upper surface of the substrate and spaced apart from each other in a third direction parallel to the upper surface of the substrate and forming an acute angle with the first direction; and
and second portions each extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction,
The first and second portions of the moisture blocking structure (moisture blocking structure) the ends are connected to each other. The method of claim 1, wherein the active fins are formed in plurality,
The gate structure is a moisture preventing structure that covers two active fins adjacent to each other among the plurality of active fins. delete According to claim 1, wherein the conductive structure,
a contact plug formed on the gate structure and surrounding the chip region; and
and a via formed on the contact plug and surrounding the chip region. The method of claim 1, wherein the active fin, the gate structure, and the conductive structure are each formed in plurality,
Moisture prevention structure further comprising a metal plate (metal plate) formed on the plurality of conductive structures. delete delete delete delete The moisture barrier structure according to claim 1, wherein the active fins extend in a wave shape. an active fin formed on the sealing region of a substrate including a chip region and a sealing region surrounding the chip region, the active fin continuously surrounding the chip region in a curved shape when viewed from the top; and
a conductive structure formed on the active fin and surrounding the chip region;
The active pin is
first portions respectively extending in a first direction parallel to the upper surface of the substrate and spaced apart from each other in a third direction parallel to the upper surface of the substrate and forming an acute angle with the first direction; and
and second portions each extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction,
The first and second portions are a guard ring whose ends are connected to each other. 12. The method of claim 11, wherein the active fins are formed in plurality,
The conductive structure is a guard ring that covers two active fins adjacent to each other among the plurality of active fins. 13. The guard ring of claim 12, wherein the two active fins adjacent to each other are parallel to each other. 12. The method of claim 11, wherein the conductive structure,
a contact plug formed on the active fin to surround the chip region; and
and a via formed on the contact plug and surrounding the chip area. The method of claim 11, wherein the active fin and the conductive structure are each formed in plurality,
The guard ring further comprising a metal plate (metal plate) formed on the plurality of conductive structures. The guard ring of claim 11 , further comprising a source/drain layer sequentially stacked between the active fin and the conductive structure and a metal silicide pattern. delete delete delete 12. The guard ring of claim 11, wherein the active fins extend in a wave type. a substrate including a first region, a second region surrounding the first region, and a third region surrounding the second region;
a first active fin formed on a first region of the substrate;
a second active fin formed on the second region of the substrate and continuously surrounding the first region in a curved shape when viewed from the top; and
a first guard ring formed on the second active fin and including a first conductive structure surrounding the first region;
a third active fin formed on the third region and continuously surrounding the second region in a curved shape when viewed from the top;
a second gate structure surrounding the second region while covering the third active fin; and
a second conductive structure formed on the second gate structure and surrounding the second region;
the first active fins extend in a first direction parallel to the upper surface of the substrate;
The second active pin is
first portions respectively extending in the first direction and spaced apart from each other in a third direction parallel to the upper surface of the substrate and forming an acute angle with the first direction; and
and second portions each extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction,
The first and second portions of the semiconductor device are provided with a moisture barrier structure, the ends of which are connected to each other. 22. The method of claim 21, wherein each of the second and third active fins are formed in plurality,
The first conductive structure is formed on two second active fins adjacent to each other among the plurality of second active fins, and the second gate structure is formed on two third active fins adjacent to each other among the plurality of third active fins. A semiconductor device that covers the fins. delete The method of claim 21, wherein the first conductive structure,
a first contact plug formed on the second active fin to surround the first area; and
a first via formed on the first contact plug and surrounding the first region;
The second conductive structure,
a second contact plug surrounding the second region on the second gate structure; and
and a second via formed on the second contact plug and surrounding the second region. delete delete delete delete delete delete delete delete delete delete 22. The method of claim 21, wherein the third active fin is formed in plurality,
at least one of the plurality of third active fins; and
and a second guard ring formed on the at least one third active fin and including a third conductive structure surrounding the second region. The semiconductor device of claim 21 , wherein the first region is a chip region in which a semiconductor chip is formed, and the second and third regions are sealing regions surrounding and protecting the chip region. delete delete delete delete delete delete delete delete

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