CN108321153B

CN108321153B - Electrostatic discharge protection structure and forming method thereof

Info

Publication number: CN108321153B
Application number: CN201710030460.2A
Authority: CN
Inventors: 陶佳佳
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-16
Filing date: 2017-01-16
Publication date: 2020-10-09
Anticipated expiration: 2037-01-16
Also published as: CN108321153A

Abstract

An electrostatic discharge protection structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part, the substrate comprises a first area, a second area and a third area, and the fin part comprises a first fin part, a second fin part and a third fin part; forming a first doped layer; forming a second doped layer and a third doped layer; a first electrode, a second electrode and a third electrode are formed. According to the technical scheme, the PN junction forming position can be controlled by controlling the contact positions of the first doping layer, the second doping layer and the third doping layer, so that the technical scheme can effectively reduce the difficulty in controlling the PN junction forming position, is favorable for reducing the difficulty in forming the electrostatic discharge protection structure, and is favorable for improving the yield and the performance of forming the electrostatic discharge protection structure.

Description

Electrostatic discharge protection structure and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to an electrostatic discharge protection structure and a forming method thereof.

Background

With the continuous improvement of the technological capability of semiconductor process, the size of semiconductor devices is continuously reduced. The more significant the damage to semiconductor integrated circuits by Electrostatic Discharge (ESD) becomes. Moreover, with the widespread use of semiconductor chips, the factors causing electrostatic damage to the semiconductor chips are increasing. Statistically, 35% of the products with integrated circuit failures are due to electrostatic discharge problems. Therefore, in the existing chip design, the design of the esd protection structure of the integrated circuit becomes very important.

At present, the design and application of the esd protection structure include: a gate grounded N-type field effect Transistor (GGNMOS) protection circuit, a shallow trench isolation diode (STI diode) protection circuit, a Gated diode protection circuit, a Laterally Diffused MOS (LDMOS) protection circuit, a Bipolar Junction Transistor (BJT) protection circuit, and the like.

With the continuous reduction of the size of a semiconductor device and the continuous improvement of the device density, the existing electrostatic discharge protection structure cannot meet the technical requirements, and a fin field effect transistor needs to be introduced into the electrostatic discharge protection structure. However, as the size of the semiconductor device is further reduced, the electrical performance of the finfet is still to be improved even though the finfet is used in the esd protection structure.

Disclosure of Invention

The invention provides an electrostatic discharge protection structure and a forming method thereof, which are used for improving the performance of the electrostatic discharge protection structure.

In order to solve the above problems, the present invention provides a method for forming an esd protection structure, comprising:

providing a substrate, wherein the substrate is provided with a plurality of discrete fin parts, the substrate comprises a first area, a second area which is positioned at one side of the first area and is adjacent to the first area, and a third area which is arranged opposite to the second area and is adjacent to the first area, the fin parts positioned on the substrate in the first area are first fin parts, the fin parts positioned on the substrate in the second area are second fin parts, and the fin parts positioned on the substrate in the third area are third fin parts; forming a first doping layer located on the first fin portion, wherein first type ions are arranged in the first doping layer; forming a second doping layer located on the second fin portion and a third doping layer located on the third fin portion, wherein the second doping layer and the third doping layer are internally provided with second type ions, the second doping layer is in contact with the first doping layer, and the third doping layer is in contact with the first doping layer; and forming a first electrode on the first doping layer, a second electrode on the second doping layer and a third electrode on the third doping layer, wherein one of the second electrode and the third electrode is used for being electrically connected with a first bias voltage, and the other one of the second electrode and the third electrode is used for being electrically connected with a second bias voltage.

Correspondingly, the invention also provides an electrostatic discharge protection structure, which comprises:

the substrate comprises a first area, a second area which is positioned on one side of the first area and is adjacent to the first area, and a third area which is arranged opposite to the second area and is adjacent to the first area, wherein the fin part positioned on the substrate in the first area is a first fin part, the fin part positioned on the substrate in the second area is a second fin part, and the fin part positioned on the substrate in the third area is a third fin part; a first doped layer located on the first fin portion, the first doped layer having first type ions therein; a second doping layer located on the second fin portion, wherein the second doping layer is internally provided with second type ions and is in contact with the first doping layer; a third doped layer located on the third fin portion, wherein the third doped layer is internally provided with second type ions and is in contact with the first doped layer; a first electrode on the first doped layer; a second electrode on the second doped layer; and a third electrode on the third doped layer, one of the second electrode and the third electrode being for electrical connection to a first bias voltage, and the other being for electrical connection to a second bias voltage.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the technical scheme, a first doping layer with first type ions is formed on the first fin portion; and forming a second doping layer and a third doping layer which are positioned on the second fin part and the third fin part and respectively provided with second type ions, wherein the second doping layer and the third doping layer are in contact with the first doping layer to form a PN junction. The first doping layer, the second doping layer and the third doping layer are respectively formed on different fin parts, so that the PN junction forming position can be controlled by controlling the contact positions of the first doping layer, the second doping layer and the third doping layer.

In an alternative aspect of the present invention, in the step of forming the first epitaxial layer on the first fin portion, the first epitaxial layer has a sidewall perpendicular to the surface of the substrate; and then forming a second epitaxial layer and a third epitaxial layer, and enabling the second epitaxial layer and the third epitaxial layer to be respectively contacted with the first epitaxial layer, so that the appearance of the contact positions of the formed second doped layer and the third doped layer with the first doped layer can be effectively improved, the performance of the formed PN junction can be improved, and the yield and the performance of the formed electrostatic discharge protection structure can be improved.

In the alternative scheme of the invention, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer can be formed by an epitaxial growth process, and a first doping layer, a second doping layer and a third doping layer can be respectively formed in an in-situ ion doping or ion implantation mode; the material of the first doping layer is P-type doped Si or SiGe; the material of the second doped layer and the third doped layer is N-type doped Si or SiC. Therefore, the technical scheme of the invention can complete production without greatly changing the existing production line, has better compatibility with the existing process, and does not need to add extra process and cost.

In an alternative aspect of the invention, the plurality of discrete fin portions are parallel to one another; the second region and the third region are located on two sides of the first region along a direction perpendicular to the extending direction of the fin portion; or, along the extending direction of the fin portion, the second region and the third region are located on two sides of the first region. Therefore, the sizes and the positions of the first doping layer, the second doping layer and the third doping layer are controlled by changing the number and the sizes of the first fin part, the second fin part and the third fin part so as to meet the design requirements of the electrostatic discharge protection structure, the process difficulty of forming the electrostatic discharge protection structure is favorably reduced, and the yield and the performance of the formed electrostatic discharge protection structure are favorably improved.

Drawings

FIG. 1 is a schematic structural diagram of an ESD protection structure;

fig. 2 to 7 are schematic structural diagrams corresponding to steps of an esd protection structure forming method according to an embodiment of the invention.

Detailed Description

As can be seen from the background, as the size of the semiconductor device is further reduced, the electrical performance of the finfet is still to be improved even though the finfet is used in the esd protection structure. The reason why the electrical performance of the electrostatic discharge protection structure with the fin field effect transistor structure needs to be improved is analyzed in combination:

referring to fig. 1, a schematic diagram of an esd protection structure is shown.

As shown in fig. 1, the esd protection structure includes:

a substrate 10, the substrate 10 having a discrete fin 11 thereon; an epitaxial layer 12 located on the fin 11, wherein the epitaxial layer 12 spans the fin 11 and covers the top and the surface of the sidewall of the fin 11; the epitaxial layer 12 includes a first region 12P and second regions 12N located at two sides of the first region 12P, the first region 12P and the second regions 12N are arranged along the extending direction of the fin portion 11, P-type ions are provided in the epitaxial layer 12 of the first region 12P, and N-type ions are provided in the epitaxial layer 12 of the second region 12N.

The epitaxial layer 12 of the first region 12p and the epitaxial layer 12 of the second region 12n form a PN junction at the position of contact, and thus the electrostatic discharge protection structure is used to constitute a bipolar junction transistor protection circuit having an NPN structure.

The step of forming the epitaxial layer 12 of the first region 12p and the epitaxial layer 12 of the second region 12n includes: forming an epitaxial material layer on the fin portion 11 through an epitaxial deposition process; after the epitaxial material layer is formed, P-type ion doping is performed on the epitaxial material layer of the first region 12P to form the epitaxial layer 12 of the first region 12P, and N-type ion doping is performed on the epitaxial material layer of the second region 12N to form the epitaxial layer 12 of the second region 12N.

The epitaxial layer 12 of the first region 12p and the epitaxial layer 12 of the second region 12n are arranged along the extending direction of the fin 11. Therefore, in the step of performing ion doping, different types of ions are doped to the epitaxial material layers in different regions on the same fin portion 11, and therefore, the doped ions may diffuse or move during the doping process, so that it is difficult to control the junction forming position of the formed PN junction and the position of the formed NPN structure, which may cause the performance degradation of the formed esd protection structure, and affect the performance and yield of the formed esd protection structure.

In order to solve the technical problem, the invention provides a method for forming an electrostatic discharge protection structure, which comprises the following steps:

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 2 to 7, schematic structural diagrams corresponding to each step of an embodiment of a method for forming an esd protection structure according to the invention are shown.

Referring to fig. 2, a substrate 100 is provided, where the substrate 100 has a plurality of discrete fins 101, the substrate includes a first region 110, a second region 120 located on one side of the first region 110 and adjacent to the first region 110, and a third region 130 located opposite to the second region 120 and adjacent to the first region 110, the fins 101 located on the substrate 100 in the first region 110 are first fins 111, the fins 101 located on the substrate 100 in the second region 120 are second fins 121, and the fins 101 located on the substrate 100 in the third region 130 are third fins 131. Wherein fig. 3 is a schematic cross-sectional view taken along line AA in fig. 2.

The substrate 100 is used to provide a process platform.

In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.

The fin 101 is used to provide a channel of the finfet.

In this embodiment, the material of the fin 101 is the same as that of the substrate 100, and is also monocrystalline silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.

Specifically, the substrate 100 and the fin 101 may be formed simultaneously. The steps of forming the substrate 100 and the fin 101 include: providing an initial substrate; forming a fin mask layer (not shown) on the surface of the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask to form the substrate 100 and a fin part 101 positioned on the substrate 100.

The fin mask layer is used to define the size and position of the fin 101.

The step of forming the fin mask layer includes: forming a mask material layer on the initial substrate; forming a pattern layer on the mask material layer; and etching the mask material layer by taking the pattern layer as a mask to expose the initial substrate so as to form the fin part mask layer.

The pattern layer is used for patterning the mask material layer so as to define the size and the position of the fin portion.

In this embodiment, the pattern layer is a patterned photoresist layer and may be formed through a coating process and a photolithography process. In other embodiments of the present invention, the patterned layer may also be a mask formed by a multi-patterning mask process, so as to reduce the feature size of the fin portion and the distance between adjacent fin portions, and improve the integration level of the formed semiconductor structure. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.

It should be noted that, in this embodiment, after the substrate 100 and the fin 101 are formed, the fin mask layer on the top of the fin 101 is retained. The fin mask layer is made of silicon nitride and is used for defining the position of a stop layer of a planarization process in a subsequent process and playing a role in protecting the fin 101.

In this embodiment, after the substrate 100 and the fin 101 are formed, the forming method further includes: an isolation layer (not shown) is formed on the substrate 100 not covered by the fin 101, and the top of the isolation layer is lower than the top of the fin 101 and covers a part of the surface of the sidewall of the fin 101.

The isolation layer is used to achieve electrical isolation between adjacent fins 101 and between adjacent semiconductor structures.

In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.

The step of forming the isolation layer includes: forming an isolation material layer on the substrate 100 which is not covered by the fin 101 by a chemical vapor deposition (for example: fluid chemical vapor deposition) method, and the like, wherein the isolation material layer covers the fin mask layer; removing the isolation material layer higher than the fin mask layer by chemical mechanical polishing and the like; and removing part of the thickness of the residual isolating material layer by back etching to form the isolating layer.

The substrate 100 of the second region 120 and the substrate 100 of the third region 130 and the substrate 100 of the first region 110 are respectively used for forming different types of doped layers for forming a PN junction. The first fin portion 111 on the substrate 100 in the first region 110 is used to provide a process base for forming a first doped layer; the second fin 121 on the substrate 100 in the second region 120 is used to provide a process foundation for the subsequent formation of a second doped layer; the third fin 131 on the third region 130 substrate 100 is used to provide a process foundation for a subsequent third doped layer.

The number of the first fins 111 is one or more, the number of the second fins 121 is one or more, and the number of the third fins 131 is one or more. In this embodiment, the first fin portions 111, the second fin portions 121, and the third fin portions 131 are all multiple, the multiple first fin portions 111 are parallel to each other, the multiple second fin portions 121 are parallel to each other, and the multiple third fin portions 131 are parallel to each other. Specifically, the substrate 100 has 3 first fins 111, 3 second fins 121, and 3 third fins 131 that are parallel to each other.

In addition, in this embodiment, the number of the first fin portion 111, the second fin portion 121, and the third fin portion 131 is equal. However, in other embodiments of the present invention, the numbers of the first fin 111, the second fin 121, and the third fin 131 may not be equal.

The first fin portion 111 is used for providing a process basis for forming a first doping layer subsequently; the second fin portion 121 is used for providing a process foundation for forming a second doping layer subsequently; the third fin 131 is used to provide a process basis for a subsequent third doping layer, so that the sizes and positions of the first doping layer, the second doping layer and the third doping layer can be controlled by respectively changing the sizes and the numbers of the first fin 111, the second fin 121 and the third fin 131. The number and size of the first fin 111, the second fin 121, and the third fin 131 may be changed in a layout design (GDS layout) process, so as to meet the design requirement of the esd protection structure. Therefore, the technical scheme of the invention can effectively reduce the process difficulty of forming the electrostatic discharge protection structure and is beneficial to improving the yield and the performance of the formed electrostatic discharge protection structure.

It should be noted that, in this embodiment, the plurality of discrete fins 101 are parallel to each other, and the second region 120 and the third region 130 are located on two sides of the first region 110 along a direction perpendicular to an extending direction of the fins 101.

It should be noted that, in other embodiments of the present invention, along the extending direction of the fin portion, the second region and the third region are located on two sides of the first region.

Referring to fig. 4, a first doping layer 112 is formed on the first fin portion 111, and the first doping layer 112 has first type ions therein.

The first doped layer 112 is used to form a PN junction.

The first doped layer 112 has a first type of ions therein. In this embodiment, the first type ions are P-type ions, such as B, Ga or In; the material of the first doped layer 112 is therefore a P-type doped semiconductor material for providing a P-type semiconductor in a PN junction.

Since the material of the first doped layer 112 is a P-type doped semiconductor material, the material of the first doped layer 112 in this embodiment is P-type doped SiGe. In other embodiments of the present invention, the material of the first doped layer may also be P-type doped Si.

In other embodiments of the present invention, the first type of ion may also be an N-type ion, such as P, As or Sb; the material of the first doped layer is thus an N-type doped semiconductor material for providing an N-type semiconductor in a PN junction. When the material of the first doping layer is an N-type doped semiconductor material, the material of the first doping layer is N-type doped SiC or Si.

In this embodiment, the number of the first fin portions 111 is multiple, so the step of forming the first doping layer 112 on the first fin portions 111 includes: forming a first doping layer 112 on the plurality of first fins 111, wherein the first doping layer 112 spans the plurality of first fins 111 and covers the top and the surface of the sidewall of the first fins 111.

Therefore, the projection area of the first doping layer 112 on the surface of the substrate 100 is related to the number and size of the first fin portions 111 and the distance between adjacent first fin portions 111, so that the area of the first doping layer 112 can be changed by changing the number and size of the first fin portions 111 and the distance between adjacent first fin portions 111 to adapt to the design requirement of the esd protection structure, which is beneficial to reducing the process difficulty of forming the esd protection structure and improving the yield and performance of the formed esd protection structure.

Specifically, as shown in fig. 4, the step of forming the first doping layer 112 on the first fin portion 111 includes: forming a first mask 124 on the substrate 100 in the second region 120 and the substrate 100 in the third region 130, wherein the first mask 124 exposes the first fin 111; forming a first epitaxial layer on the first fin portion 111 by using the first mask 124 as a mask; the first epitaxial layer is ion doped to form the first doped layer 112.

The first mask 124 is used to protect the substrate 100 of the second region 120 and the third region 130, and define the formation position of the first epitaxial layer, so as to avoid forming the first epitaxial layer on the substrate 100 of the second region 120 and the third region.

In this embodiment, in the step of forming the first epitaxial layer on the first fin portion 111, the first epitaxial layer has a sidewall perpendicular to the surface of the substrate 100.

Specifically, in the step of forming the first mask 124 on the substrate 100 in the second region 120 and the substrate 100 in the third region 130, the sidewall of the first mask 124 facing the first region 110 is perpendicular to the surface of the substrate 100; in the step of forming the first epitaxial layer on the first fin 111, the first epitaxial layer is in contact with the sidewall of the first mask 124, so that the shape of the sidewall of the formed first epitaxial layer corresponds to the shape of the sidewall of the first mask 124. In this embodiment, the first mask 124 is also used to define the shape of the first epitaxial layer sidewall.

In this embodiment, the material of the first mask 124 is a photoresist, and may be formed through a coating process and a photolithography process. In other embodiments of the present invention, the material of the first mask may also be a mask of other materials.

The first epitaxial layer is used to form a first doped layer 112 after ion doping.

In this embodiment, since the material of the first doping layer 112 is P-type doped SiGe, the material of the first epitaxial layer is SiGe, and the first epitaxial layer may be formed on the first fin portion 111 through an epitaxial growth process. In other embodiments of the present invention, the material of the first epitaxial layer may also be P-type doped Si. In another embodiment of the present invention, since the material of the first doping layer is N-type doped SiC or Si, the material of the first epitaxial layer may also be SiC or Si.

SiGe, SiC or Si materials are epitaxial layer materials which are frequently used in the existing production line, so that the technical scheme of the invention can complete production without greatly changing the existing production line, has better compatibility, and does not need to increase additional process and cost.

The step of ion doping the first epitaxial layer serves to dope a first type of ions into the first epitaxial layer to form the first doped layer 112.

The step of ion doping the first epitaxial layer comprises: in-situ ion doping is performed during the epitaxial growth process. Specifically, the first type ions are P-type ions, so that in-situ P-type ion doping is performed during the epitaxial growth process, thereby forming the P-type doped first doping layer 112. Therefore, in this embodiment, the doping ions in the P-type doped first doping layer 112 are B ions or BF ions₂The doping concentration of the common P-type ions such as ions is 1E16atom/cm³To 1E22atom/cm³Within the range.

In other embodiments of the present invention, the first type ions are N-type ions, and thus in-situ N-type ion doping is performed during the epitaxial growth process, so as to form an N-type doped first doping layer. Therefore, in the first doping layer of N-type doping, the doping ions are common N-type ions such As P ions or As ions, and the doping concentration is 1E16atom/cm³To 1E22atom/cm³Within the range.

It should be noted that, the method of performing in-situ ion doping during the epitaxial growth process is only an example, and in other embodiments of the present invention, the step of performing ion doping on the first epitaxial layer includes: after the epitaxial layer is formed, ion doping is performed by means of ion implantation.

Therefore, the step of ion doping the first epitaxial layer comprises: after the first epitaxial layer is formed, ion implantation is performed on the first epitaxial layer to form the first doping layer. In the process of forming the first doping layer by adopting an ion implantation mode, the first mask is further used for protecting the substrates of the second region and the third region and the second fin portion and the third fin portion, and reducing the number of first type ions in the substrates of the second fin portion, the third fin portion, the second region and the third region.

Specifically, in the step of forming the first doping layer by ion implantation, the first type ions are P-type ionsIons, so the implanted ions are B ions or BF₂The implantation dose of the commonly used P-type ions such as ions is 1E10atom/cm²To 1E17atom/cm²In the range, the implantation energy is in the range of 0KeV to 50KeV, and the process temperature is in the range of-120 ℃ to 120 ℃; the first type ion is N type ion, so the implanted ion is P ion or As ion and other common N type ion, and the implantation dosage is 1E10atom/cm²To 1E17atom/cm²The implantation energy is in the range of 0KeV to 50KeV, and the process temperature is in the range of-120 ℃ to 120 ℃.

Referring to fig. 5 in combination, a second doped layer 122 located on the second fin 121 and a third doped layer 132 located on the third fin 131 are formed, the second doped layer 122 and the third doped layer 132 have ions of the second type therein, the second doped layer 122 is in contact with the first doped layer 112, and the third doped layer 132 is in contact with the first doped layer 112.

The second doped layer 122 and the third doped layer 132 are respectively in contact with the first doped layer 112 to respectively form PN junctions.

The second doped layer 122 and the third doped layer 132 both have ions of the second type therein. In this embodiment, the second type of ions are N-type ions, such as P, As or Sb; therefore, the materials of the second doped layer 122 and the third doped layer 132 are both N-type doped semiconductor materials for providing an N-type semiconductor in a PN junction.

Since the material of the second doped layer 122 and the third doped layer 132 is an N-type doped semiconductor material, in this embodiment, the material of the second doped layer 122 and the material of the third doped layer 132 are both N-type doped SiC. In other embodiments of the present invention, the material of the second doped layer and the third doped layer may also be N-type doped Si.

In other embodiments of the present invention, the second type of ions may also be P-type ions, such as B, Ga or In; the material of the second doped layer is therefore a P-type doped semiconductor material for providing a P-type semiconductor in a PN junction. When the materials of the second doping layer and the third doping layer are P-type doped semiconductors, the materials of the second doping layer and the third doping layer are P-type doped SiGe or Si.

In this embodiment, the number of the second fins 121 is multiple, and the number of the third fins 131 is multiple, so the step of forming the second doping layer 122 on the second fins 121 includes: forming a second doping layer 122 located on the plurality of second fins 121, wherein the second doping layer 122 spans the plurality of second fins 121 and covers the top and the surface of the sidewall of the second fin 121; the step of forming the third doping layer 132 on the third fin 131 includes: forming a third doping layer 132 on the plurality of third fins 131, wherein the third doping layer 132 spans the plurality of third fins 131 and covers the top and the sidewall surfaces of the third fins 131.

Therefore, the projected area of the second doped layer 122 on the surface of the substrate 100 is related to the number and size of the second fins 121 and the distance between adjacent second fins 121; the projected area of the third doped layer 132 on the surface of the substrate 100 is related to the number and size of the third fins 131 and the distance between adjacent third fins 131. Therefore, the area of the second doping layer 122 can be changed by changing the number and size of the second fins 121 and the distance between adjacent second fins 121, and the area of the third doping layer 132 can be changed by changing the number and size of the third fins 131 and the distance between adjacent third fins 131, so that the areas of the second doping layer 122 and the third doping layer 132 can meet the design requirements of the electrostatic discharge protection structure, the process difficulty of forming the electrostatic discharge protection structure is reduced, and the yield and the performance of the formed electrostatic discharge protection structure are improved.

It should be noted that, in this embodiment, the second region 120 and the third region 130 are located on two sides of the first region 110 along a direction perpendicular to the extending direction of the fin 101. The second doped layer 122 and the third doped layer 132 are located on two sides of the first doped layer 112 along a direction perpendicular to the extending direction of the fin 101. Firstly, the contact positions of the second doped layer 122 and the third doped layer 132 with the first doped layer 112 can be well controlled, so that the control of the junction forming position of the PN junction is facilitated, and the influence of process factors (process temperature and the like) on the junction forming position is reduced; secondly, the junction forming area of the formed PN junction can be changed by changing the lengths of the first fin portion 111, the second fin portion 121 and the third fin portion 131, which is beneficial to reducing the process difficulty; moreover, the process difficulty of forming the first fin portion 111, the second fin portion 121, and the third fin portion 131 is low, which is beneficial to reducing the process cost.

In other embodiments of the present invention, along the extending direction of the fin portion, the second region and the third region are located on two sides of the first region. Therefore, the second doping layer and the third doping layer are located on two sides of the first doping layer along the extending direction of the fin portion.

Specifically, as shown in fig. 5, the step of forming the second doping layer 122 on the second fin 121 and the third doping layer 132 on the third fin 131 includes: forming a second mask 114 on the first doping layer 112, wherein the second mask 114 exposes the second fin 121 and the third fin 131; forming a second epitaxial layer on the second fin portion 121 and a third epitaxial layer on the third fin portion 131 by using the second mask 114 as a mask, wherein the second epitaxial layer is in contact with the first epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer; ion doping is performed on the second epitaxial layer and the third epitaxial layer to form the second doped layer 122 and the third doped layer 132, respectively.

The second mask 114 is used for protecting the first doping layer 112, the first fin 111 and the substrate 100 of the first region 110, and defining a forming position of the second epitaxial layer to avoid forming the second epitaxial layer on the substrate 100 of the first region 110.

In this embodiment, the second mask 114 is made of photoresist and may be formed by a coating process and a photolithography process. In other embodiments of the present invention, the material of the second mask may also be a mask of other materials.

As shown in fig. 4 and 5, in this embodiment, the forming method further includes: after the first doping layer 112 on the first fin 111 is formed, before the second doping layer 122 on the second fin 121 and the third doping layer 132 on the third fin 131 are formed, the first cap layer 113 on the first doping layer 112 is formed.

The first cap layer 113 is used to protect the first doped layer 112, and prevent the first doped layer 112 from being exposed to the air, thereby achieving the purpose of improving the stability of the formed electrostatic discharge protection structure. Specifically, the material of the first cap layer 113 is a semiconductor material having the same type of doped ions as the first doped layer 112. In this embodiment, the material of the first cap layer 113 is Si with P-type doping. In the step of forming the second mask 114, the second mask 114 is located on the first cap layer 113.

The second epitaxial layer and the third epitaxial layer are used to form the second doping layer 122 and the third doping layer 132 after ion doping.

In this embodiment, since the second doping layer 122 and the third doping layer 132 are made of N-type doped SiC, the second epitaxial layer and the third epitaxial layer are made of SiC and may be formed on the second fin 121 or the third fin 131 by an epitaxial growth process. In other embodiments of the present invention, the material of the second epitaxial layer and the third epitaxial layer may also be Si. In another embodiment of the present invention, the material of the second doped layer and the material of the third doped layer are P-type doped SiGe or Si, so the material of the second epitaxial layer may also be SiGe or Si.

It should be noted that the second epitaxial layer is in contact with the first epitaxial layer, the third epitaxial layer is in contact with the first epitaxial layer, and the first epitaxial layer has a sidewall perpendicular to the surface of the substrate 100. The sidewalls of the second epitaxial layer and the third epitaxial layer, which are in contact with the first epitaxial layer, respectively, are also perpendicular to the surface of the substrate 100. By the method, the appearance of the contact positions of the second doping layer 122 and the third doping layer 132 with the first doping layer 112 can be effectively improved, the performance of the formed PN junction can be improved, and the yield and the performance of the formed electrostatic discharge protection structure can be improved.

The step of ion doping the second epitaxial layer and the third epitaxial layer is for doping ions of a first type into the second epitaxial layer and the third epitaxial layer to form the second doped layer 122 and the third doped layer 132.

The step of ion doping the second epitaxial layer and the third epitaxial layer comprises: in-situ ion doping is performed during the epitaxial growth process. Specifically, the second type ions are N-type ions, so that in-situ N-type ion doping is performed during the epitaxial growth process, thereby forming the N-type doped second doping layer 122 and the N-type doped third doping layer 132. Therefore, in this embodiment, the doping ions in the N-doped second doping layer 122 and the third doping layer 132 are commonly N-type ions such As P ions or As ions, and the doping concentration is 1E16atom/cm³To 1E22atom/cm³Within the range.

In other embodiments of the present invention, the second type ions are P type ions, so that in the epitaxial growth process, in-situ P type ion doping is performed to form a P type doped second doping layer and a P type doped third doping layer. Therefore, in the second doping layer and the third doping layer of the P-type doping, the doping ions are B ions or BF₂The doping concentration of the common P-type ions such as ions is 1E16atom/cm³To 1E22atom/cm³Within the range.

It should be noted that, the method of performing in-situ ion doping during the epitaxial growth process is only an example, and in other embodiments of the present invention, the step of performing ion doping on the second epitaxial layer and the third epitaxial layer includes: after the epitaxial layer is formed, ion doping is performed by means of ion implantation.

Therefore, the step of ion doping the second epitaxial layer and the third epitaxial layer comprises: after the second epitaxial layer and the third epitaxial layer are formed, ion implantation is performed on the second epitaxial layer and the third epitaxial layer to form the second doped layer and the third doped layer. In the process of forming the second doping layer and the third doping layer by adopting an ion implantation mode, the second mask is also used for protecting the first doping layer, the substrate in the first region and the first fin portion, and the number of second-type ions in the first doping layer, the substrate in the first region and the first fin portion is reduced.

Specifically, in the step of forming the second doping layer and the third doping layer by ion implantation, when the second type of ions are N-type ions, the implanted ions are commonly N-type ions such As P ions or As ions, and the implantation dose is 1E10atom/cm²To 1E17atom/cm²In the range, the implantation energy is in the range of 0KeV to 50KeV, and the process temperature is in the range of-120 ℃ to 120 ℃; when the second type ions are P type ions, the implanted ions are B ions or BF ions₂The implantation dose of the commonly used P-type ions such as ions is 1E10atom/cm²To 1E17atom/cm²The implantation energy is in the range of 0KeV to 50KeV, and the process temperature is in the range of-120 ℃ to 120 ℃.

Referring to fig. 6 and 7 in combination, a first electrode on the first doped layer 112 (shown in fig. 7), a second electrode on the second doped layer 122 (shown in fig. 7), and a third electrode on the third doped layer 132 (shown in fig. 7) are formed, one of the second electrode and the third electrode is used for electrical connection with a first bias voltage, and the other is used for electrical connection with a second bias voltage.

The second electrode and the third electrode are used for realizing the connection of the electrostatic discharge protection structure and an external circuit. In this embodiment, the second electrode is connected to the electrostatic input terminal, and is configured to input a first bias electrical signal; the third electrode is used for being connected with the electrostatic output end and inputting a second bias electric signal, and the first bias electric signal is not equal to the second bias electric signal.

As shown in fig. 5 to 7, in this embodiment, the forming method further includes: after forming the second doping layer 122 located on the second fin 121 and the third doping layer 132 located on the third fin 131, before forming the first electrode located on the first doping layer 112, the second electrode located on the second doping layer 122, and the third electrode located on the third doping layer 132, forming the second cap layer 123 located on the second doping layer 122 and the third cap layer 133 located on the third doping layer 132.

The second cap layer 123 is used for protecting the second doped layer 122 and preventing the second doped layer 122 from being exposed to the air; the third cap layer 133 is used to protect the third doped layer 132 and prevent the third doped layer 132 from being exposed to the air, so that the arrangement of the second cap layer 123 and the third cap layer 133 can effectively improve the stability of the formed electrostatic discharge protection structure. Specifically, the material of the second cap layer 123 is a semiconductor material having the same type of doped ions as the second doped layer 122; the material of the third cap layer 133 is a semiconductor material having the same type of doped ions as the third doped layer 132. In this embodiment, the material of the second cap layer 123 and the third cap layer 133 is N-type doped Si.

The steps of forming a first electrode on the first doped layer 112, a second electrode on the second doped layer 122, and a third electrode on the third doped layer 132 include: a first electrode on the first cap layer 113, a second electrode on the second cap layer 123, and a third electrode on the third cap layer 133 are formed.

Specifically, as shown in fig. 6 and 7, the step of forming a first electrode on the first doped layer 112, a second electrode on the second doped layer 122, and a third electrode on the third doped layer 132 includes: forming a plurality of first plugs 115 on the first doping layer 112, a plurality of second plugs 125 on the second doping layer 122, and a plurality of third plugs 135 on the third doping layer 132, wherein the plurality of first plugs 115 are arranged in a direction parallel to the extending direction of the first fin 111, the plurality of second plugs 125 are arranged in a direction parallel to the extending direction of the second fin 121, and the plurality of third plugs 135 are arranged in a direction parallel to the extending direction of the third fin 131.

In this embodiment, the material of the first plug 115, the second plug 125, and the third plug 135 is W. In other embodiments of the present invention, the material of the first plug, the second plug, and the third plug may further be one or more selected from metal materials such as tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper.

The first plug 115, the second plug 125, and the third plug 135 may be formed through the same process, and the process steps for forming the first plug 115, the second plug 125, and the third plug 135 are the same as those in the prior art, and are not described herein again.

In another embodiment of the present invention, the step of forming a first electrode on the first doped layer, a second electrode on the second doped layer, and a third electrode on the third doped layer includes: and forming a first interconnecting line on the first doping layer, a second interconnecting line on the second doping layer and a third interconnecting line on the third doping layer, wherein the first interconnecting line is arranged in parallel with the first fin portion, the second interconnecting line is arranged in parallel with the second fin portion, and the third interconnecting line is arranged in parallel with the third fin portion.

Correspondingly, the invention also provides an electrostatic discharge protection structure.

Referring to fig. 6 and 7, schematic structural diagrams of an embodiment of the esd protection structure of the present invention are shown. Fig. 6 is a schematic three-dimensional structure diagram of an embodiment of the esd protection structure, and fig. 7 is a schematic cross-sectional structure diagram along the BB line in the embodiment shown in fig. 6.

A substrate 100, where the substrate 100 has a plurality of discrete fins 101 (as shown in fig. 6), the substrate 100 includes a first region 110, a second region 120 located on one side of the first region 110 and adjacent to the first region 110, and a third region 130 located opposite to the second region 120 and adjacent to the first region 110, the fin 101 located on the substrate 100 in the first region 110 is a first fin 111 (as shown in fig. 7), the fin 101 located on the substrate 100 in the second region 120 is a second fin 121 (as shown in fig. 7), and the fin 101 located on the substrate 100 in the third region 130 is a third fin 131 (as shown in fig. 7); a first doped layer 112 (shown in fig. 7) on the first fin 111, the first doped layer 112 having a first type of ions therein; a second doped layer 122 (as shown in fig. 7) on the second fin 121, the second doped layer 122 having the second type of ions therein, the second doped layer 122 being in contact with the first doped layer 112; a third doped layer 132 (shown in fig. 7) on the third fin 131, the third doped layer 132 having the second type of ions therein, the third doped layer 132 being in contact with the first doped layer 112; a first electrode on the first doped layer 112; a second electrode on the second doped layer 122; and a third electrode on the third doped layer 132, wherein one of the second electrode and the third electrode is electrically connected to a first bias voltage, and the other is electrically connected to a second bias voltage.

The substrate 100 is used to provide a process platform.

The fin 101 is used to provide a channel of the finfet.

In this embodiment, the semiconductor structure further includes: an isolation layer (not shown) on the substrate 100 is exposed by the fin 101, and the top of the isolation layer is lower than the top of the fin 101 and covers a portion of the surface of the sidewall of the fin 101.

The isolation layer is used to achieve electrical isolation between adjacent fins 101 and between adjacent semiconductor structures. In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.

The substrate 100 of the second region 120 and the substrate 100 of the third region 130 and the substrate 100 of the first region 110 are respectively used for forming different types of doped layers for forming a PN junction. The first fin 111 on the substrate 100 in the first region 110 is used to provide a process base for forming the first doped layer 112; the second fin 121 on the substrate 100 in the second region 120 is used to provide a process foundation for forming the second doped layer 122; the third fin 131 on the third region 130 substrate 100 is used to provide a process foundation for forming the third doped layer 132.

Since the first fin 111 is used to provide a process foundation for the formation of the first doping layer 112; the second fin 121 is used for providing a process foundation for forming the second doping layer 122; the third fin 131 is used to provide a process basis for forming the third doping layer 132, so that the sizes and the positions of the first doping layer 112, the second doping layer 122 and the third doping layer 132 can be controlled by respectively changing the sizes and the numbers of the first fin 111, the second fin 121 and the third fin 131. The number and size of the first fin 111, the second fin 121, and the third fin 131 may be changed in a layout design (GDS layout) process, so as to meet the design requirement of the esd protection structure. Therefore, the technical scheme of the invention can effectively reduce the process difficulty of forming the electrostatic discharge protection structure and is beneficial to improving the yield and the performance of the formed electrostatic discharge protection structure.

In other embodiments of the present invention, the second region and the third region may also be located on two sides of the first region along the extending direction of the fin portion.

The first doped layer 112 is used to form a PN junction.

Specifically, in this embodiment, in the P-type doped first doped layer 112, the doped ions are B ions or BF ions₂The doping concentration of the common P-type ions such as ions is 1E16atom/cm³To 1E22atom/cm³Within the range.

In another embodiment of the present invention, in the N-type doped first doped layer, the doping ions are P ions or As ions and other common N-type ions, and the doping concentration is 1E16atom/cm³To 1E22atom/cm³Within the range.

In this embodiment, the number of the first fin portions 111 is multiple, so the first doping layer 112 spans the multiple first fin portions 111 and covers the top and the sidewall surfaces of the first fin portions 111.

Specifically, the second type ions are N-type ions, and the doping ions in the N-type doped second doping layer 122 and the N-type doped third doping layer 132 are common N-type ions such As P ions or As ions, and the doping concentration is 1E16atom/cm³To 1E22atom/cm³Within the range.

In other embodiments of the present invention, the second type ions are P-type ions, and the doped ions in the second doped layer and the third doped layer doped with P-type ions are B ions or BF ions₂The doping concentration of the common P-type ions such as ions is 1E16atom/cm³To 1E22atom/cm³Within the range.

In this embodiment, the number of the second fins 121 is multiple, and the number of the third fins 131 is multiple, so that the second doping layers 122 on the second fins 121 cross the second fins 121 and cover the top and the sidewall surfaces of the second fins 121; the third doping layer 132 on the plurality of third fins 131 spans the plurality of third fins 131 and covers the top and the sidewall surfaces of the third fins 131.

Therefore, the projected area of the second doped layer 122 on the surface of the substrate 100 is related to the number and size of the second fins 121 and the distance between adjacent second fins 121; the projected area of the third doped layer 132 on the surface of the substrate 100 is related to the number and size of the third fins 131 and the distance between adjacent third fins 131. Therefore, the area of the second doping layer 122 can be changed by changing the number and size of the second fins 121 and the distance between adjacent second fins 121, and the area of the third doping layer 132 can be changed by changing the number and size of the first fins 131 and the distance between adjacent third fins 131, so that the areas of the second doping layer 122 and the third doping layer 132 can meet the design requirements of the electrostatic discharge protection structure, the process difficulty of forming the electrostatic discharge protection structure is reduced, and the yield and performance of the formed electrostatic discharge protection structure are improved.

In other embodiments of the present invention, the second region and the third region are located on two sides of the first region along the extending direction of the fin portion. Therefore, the second doping layer and the third doping layer are located on two sides of the first doping layer along the extending direction of the fin portion.

In addition, since the first doped layer has a sidewall perpendicular to the surface of the substrate, the second doped layer is in contact with the first doped layer, and the third doped layer is in contact with the first doped layer, the sidewalls of the second doped layer and the third doped layer in contact with the first doped layer, respectively, are also perpendicular to the surface of the substrate 100. The method can effectively improve the appearance of the contact positions of the second doping layer and the third doping layer with the first doping layer, is beneficial to improving the performance of the formed PN junction, and is beneficial to improving the yield and the performance of the formed electrostatic discharge protection structure.

As shown in fig. 6 and 7, in this embodiment, the semiconductor structure further includes: a first cap layer 113 on the first doped layer 112, wherein the first electrode is located on the first cap layer 113; a second cap layer 123 on the second doped layer 122, wherein the second electrode is located on the second cap layer 123; a third cap layer 133 on the third doped layer 132, and the third electrode is on the third cap layer 133.

The first cap layer 113 is used to protect the first doped layer 112, and prevent the first doped layer 112 from being exposed to the air, so as to achieve the purpose of improving the stability of the esd protection structure. Specifically, the material of the first cap layer 113 is a semiconductor material having the same type of doped ions as the first doped layer 112. In this embodiment, the material of the first cap layer 113 is Si with P-type doping.

The second cap layer 123 is used for protecting the second doped layer 122 and preventing the second doped layer 122 from being exposed to the air; the third cap layer 133 is used to protect the third doped layer 132 and prevent the third doped layer 132 from being exposed to the air, so that the arrangement of the second cap layer 123 and the third cap layer 133 can effectively improve the stability of the esd protection structure. Specifically, the material of the second cap layer 123 is a semiconductor material having the same type of doped ions as the second doped layer 122; the material of the third cap layer 133 is a semiconductor material having the same type of doped ions as the third doped layer 132. In this embodiment, the material of the second cap layer 123 and the third cap layer 133 is N-type doped Si.

Specifically, as shown in fig. 6 and 7, in this embodiment, the first electrode on the first doped layer 112 includes: a plurality of first plugs 115 located on the first doping layer 112, wherein the plurality of first plugs 115 are arranged along a direction parallel to the extending direction of the first fin 111; the second electrode on the second doped layer 122 includes: a plurality of second plugs 125 disposed on the second doped layer 122, wherein the second plugs 125 are arranged along a direction parallel to the extending direction of the second fin 121; the third electrode on the third doped layer 132 includes: a plurality of third plugs 135 disposed on the third doped layer 132, wherein the plurality of third plugs 135 are arranged along a direction parallel to the extending direction of the third fin 131.

In other embodiments of the present invention, the first electrode on the first doped layer includes: the first interconnecting wire is positioned on the first doping layer and arranged in parallel with the first fin part; a second electrode on the second doped layer comprising: the second interconnecting wire is positioned on the second doping layer and arranged in parallel with the second fin part; a third electrode on the third doped layer comprising: and the third interconnecting wire is positioned on the third doping layer and is arranged in parallel with the third fin part.

In summary, in the technical solution of the present invention, a first doped layer having first type ions is formed on the first fin portion; and forming a second doping layer and a third doping layer which are positioned on the second fin part and the third fin part and respectively provided with second type ions, wherein the second doping layer and the third doping layer are in contact with the first doping layer to form a PN junction. The first doping layer, the second doping layer and the third doping layer are respectively formed on different fin parts, so that the PN junction forming position can be controlled by controlling the contact positions of the first doping layer, the second doping layer and the third doping layer. In an alternative aspect of the present invention, in the step of forming the first epitaxial layer on the first fin portion, the first epitaxial layer has a sidewall perpendicular to the surface of the substrate; and then forming a second epitaxial layer and a third epitaxial layer, and enabling the second epitaxial layer and the third epitaxial layer to be respectively contacted with the first epitaxial layer, so that the appearance of the contact positions of the formed second doped layer and the third doped layer with the first doped layer can be effectively improved, the performance of the formed PN junction can be improved, and the yield and the performance of the formed electrostatic discharge protection structure can be improved. In addition, in the alternative of the invention, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer can be formed by an epitaxial growth process, and the first doped layer, the second doped layer and the third doped layer can be respectively formed by in-situ ion doping or ion implantation; the material of the first doping layer is P-type doped Si or SiGe; the material of the second doped layer and the third doped layer is N-type doped Si or SiC. Therefore, the technical scheme of the invention can complete production without greatly changing the existing production line, has better compatibility with the existing process, and does not need to add extra process and cost. Additionally, in an alternative aspect of the present invention, the plurality of discrete fins are parallel to one another; the second region and the third region are located on two sides of the first region along a direction perpendicular to the extending direction of the fin portion; or, along the extending direction of the fin portion, the second region and the third region are located on two sides of the first region. Therefore, the sizes and the positions of the first doping layer, the second doping layer and the third doping layer are controlled by changing the number and the sizes of the first fin part, the second fin part and the third fin part so as to meet the design requirements of the electrostatic discharge protection structure, the process difficulty of forming the electrostatic discharge protection structure is favorably reduced, and the yield and the performance of the formed electrostatic discharge protection structure are favorably improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming an electrostatic discharge protection structure, comprising:

providing a substrate, wherein the substrate is provided with a plurality of discrete fin parts which are parallel to each other, the substrate comprises a first area, a second area which is positioned on one side of the first area and is adjacent to the first area, and a third area which is arranged opposite to the second area and is adjacent to the first area, the second area and the third area are positioned on two sides of the first area along a direction perpendicular to the extending direction of the fin parts, the fin parts positioned on the substrate in the first area are first fin parts, the fin parts positioned on the substrate in the second area are second fin parts, and the fin parts positioned on the substrate in the third area are third fin parts;

forming a first doping layer located on the first fin portion, wherein first type ions are arranged in the first doping layer;

forming a second doping layer located on the second fin portion and a third doping layer located on the third fin portion, wherein the second doping layer and the third doping layer are internally provided with second type ions, the second doping layer is in contact with the first doping layer, and the third doping layer is in contact with the first doping layer;

and forming a first electrode on the first doping layer, a second electrode on the second doping layer and a third electrode on the third doping layer, wherein one of the second electrode and the third electrode is used for being electrically connected with a first bias voltage, and the other one of the second electrode and the third electrode is used for being electrically connected with a second bias voltage.

2. The method of claim 1, wherein the step of forming the first doped layer on the first fin comprises: forming a first mask on the second area substrate and the third area substrate, wherein the first mask exposes the first fin part; forming a first epitaxial layer on the first fin portion by taking the first mask as a mask; carrying out ion doping on the first epitaxial layer to form the first doping layer;

the step of forming a second doped layer on the second fin and a third doped layer on the third fin includes: forming a second mask on the first doping layer, wherein the second mask exposes the second fin portion and the third fin portion; forming a second epitaxial layer on the second fin portion and a third epitaxial layer on the third fin portion by using the second mask as a mask, wherein the second epitaxial layer is in contact with the first epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer; and carrying out ion doping on the second epitaxial layer and the third epitaxial layer to form the second doped layer and the third doped layer respectively.

3. The method of forming an esd-protection structure of claim 2, wherein one or both of the step of forming a first epitaxial layer on the first fin and the step of forming a second epitaxial layer on the second fin and a third epitaxial layer on the third fin comprises: and forming the first epitaxial layer, the second epitaxial layer or the third epitaxial layer by an epitaxial growth process.

4. The method of forming an esd-protection structure of claim 3, wherein one or both of the steps of ion doping the first epitaxial layer and the second and third epitaxial layers comprises:

carrying out in-situ ion doping in the process of the epitaxial growth process; alternatively, after the epitaxial layer is formed, ion doping is performed by means of ion implantation.

5. The method of claim 2, wherein the step of forming the first epitaxial layer on the first fin has a sidewall perpendicular to the surface of the substrate.

6. The method of claim 1, wherein in the step of providing a substrate, the number of the first fin portions is one or more, the number of the second fin portions is one or more, and the number of the third fin portions is one or more;

when the number of the first fin portions is multiple, the step of forming a first doping layer on the first fin portions includes: forming a first doping layer located on the plurality of first fin portions, wherein the first doping layer spans the plurality of first fin portions and covers the tops of the first fin portions and the surfaces of the side walls;

when the number of the second fin portions is multiple, the step of forming a second doping layer on the second fin portions includes: forming a second doping layer located on the plurality of second fin portions, wherein the second doping layer spans the plurality of second fin portions and covers the tops of the second fin portions and the surfaces of the side walls;

when the number of the third fin portions is multiple, the step of forming a third doping layer on the third fin portions includes: and forming a third doping layer located on the plurality of third fin portions, wherein the third doping layer spans the plurality of third fin portions and covers the tops of the third fin portions and the surfaces of the side walls.

7. The method of claim 6, wherein in the step of providing the substrate, the number of the first fin portions is plural, the number of the second fin portions is plural, the number of the third fin portions is plural, the first fin portions are parallel to each other, the second fin portions are parallel to each other, and the third fin portions are parallel to each other.

8. The method of claim 1, wherein forming a first electrode on the first doped layer, a second electrode on the second doped layer, and a third electrode on the third doped layer comprises: and forming a plurality of first plugs positioned on the first doping layer, a plurality of second plugs positioned on the second doping layer and a plurality of third plugs positioned on the third doping layer, wherein the plurality of first plugs are arranged along the direction parallel to the extending direction of the first fin portion, the plurality of second plugs are arranged along the direction parallel to the extending direction of the second fin portion, and the plurality of third plugs are arranged along the direction parallel to the extending direction of the third fin portion.

9. The method of claim 1, wherein the first type of ions are P-type ions, comprising B, BF₂Ga or In; the second type of ions are N-type ions, including P, As or Sb.

10. The method as claimed in claim 9, wherein the material of the first doped layer is P-type doped Si or SiGe; the material of the second doping layer is N-type doped Si or SiC.

11. The method of forming an esd-protection structure of claim 1, further comprising:

after a first doping layer located on the first fin portion is formed, before a second doping layer located on the second fin portion and a third doping layer located on the third fin portion are formed, a first cap layer located on the first doping layer is formed;

after a second doping layer located on the second fin portion and a third doping layer located on the third fin portion are formed, a first electrode located on the first doping layer, a second electrode located on the second doping layer and a third electrode located on the third doping layer are formed, and a second cap layer located on the second doping layer and a third cap layer located on the third doping layer are formed;

the step of forming a first electrode on the first doped layer, a second electrode on the second doped layer, and a third electrode on the third doped layer comprises: and forming a first electrode on the first cap layer, a second electrode on the second cap layer and a third electrode on the third cap layer.

12. An electrostatic discharge protection structure, comprising:

the substrate comprises a first area, a second area which is positioned on one side of the first area and is adjacent to the first area, and a third area which is arranged opposite to the second area and is adjacent to the first area, wherein the second area and the third area are positioned on two sides of the first area along a direction perpendicular to the extending direction of the fin parts;

a first doped layer located on the first fin portion, the first doped layer having first type ions therein;

a second doping layer located on the second fin portion, wherein the second doping layer is internally provided with second type ions and is in contact with the first doping layer;

a third doped layer located on the third fin portion, wherein the third doped layer is internally provided with second type ions and is in contact with the first doped layer;

a first electrode on the first doped layer;

a second electrode on the second doped layer;

and a third electrode on the third doped layer, one of the second electrode and the third electrode being for electrical connection to a first bias voltage, and the other being for electrical connection to a second bias voltage.

13. The esd-protection structure of claim 12, wherein the first doped layer has sidewalls perpendicular to the substrate surface.

14. The esd-protection structure of claim 12, wherein the number of the first fin portions is one or more, the number of the second fin portions is one or more, and the number of the third fin portions is one or more;

the number of the first fin parts is multiple, and the first doping layer stretches across the multiple first fin parts and covers the tops of the first fin parts and the surfaces of the side walls;

the number of the second fin parts is multiple, and the second doping layer stretches across the multiple second fin parts and covers the tops of the second fin parts and the surfaces of the side walls;

the number of the third fin parts is multiple, and the third doping layer stretches across the multiple third fin parts and covers the tops of the third fin parts and the surfaces of the side walls.

15. The esd-protection structure of claim 14, wherein the first fin portion is plural in number, the second fin portion is plural in number, and the third fin portion is plural in number;

the plurality of first fin portions are parallel to each other, the plurality of second fin portions are parallel to each other, and the plurality of third fin portions are parallel to each other.

16. The esd-protection structure of claim 12, wherein the first electrode on the first doped layer comprises: a plurality of first plugs located on the first doping layer, the plurality of first plugs being arranged in a direction parallel to the extending direction of the first fin portion;

a second electrode on the second doped layer comprising: a plurality of second plugs located on the second doping layer, the plurality of second plugs being arranged in a direction parallel to the extending direction of the second fin portion;

a third electrode on the third doped layer comprising: and the plurality of third plugs are arranged on the third doping layer along the direction parallel to the extension direction of the third fin portion.

17. The esd-protection structure of claim 12, further comprising: the first cap layer is positioned on the first doping layer, and the first electrode is positioned on the first cap layer;

the second cap layer is positioned on the second doping layer, and the second electrode is positioned on the second cap layer;

and the third cap layer is positioned on the third doping layer, and the third electrode is positioned on the third cap layer.

18. The esd-protection structure of claim 12, wherein the material of the first doped layer is P-type doped Si or SiGe; the second doping layer is N-type doped Si or SiC.